[PATCH v2 0/2] clk: sunxi-ng: H6 related clock fixes

[PATCH v2 0/2] clk: sunxi-ng: H6 related clock fixes

[Jernej Skrabec]

During linux-next testing on Allwinner H6, I found several issues with
clock driver. This patch series fixes them.

Patch 1 allows video and vpu related clocks to set parent rate.
Patch 2 adds a comment with short explanation why zero width check is
needed.

Please take a look.

Best regards,
Jernej

Changes from v1:
- removed already applied patches
- fixed commit message
- added new patch which adds comment with explanation why zero width
  check is needed

Jernej Skrabec (2):
  clk: sunxi-ng: h6: Allow video & vpu clocks to change parent rate
  clk: sunxi-ng: nkmp: Explain why zero width check is needed

 drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 6 +++---
 drivers/clk/sunxi-ng/ccu_nkmp.c      | 6 ++++++
 2 files changed, 9 insertions(+), 3 deletions(-)

-- 
2.21.0


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[PATCH v2 1/2] clk: sunxi-ng: h6: Allow video & vpu clocks to change parent rate

[Jernej Skrabec]

Video related clocks need to set rate as close as possible to the
requested one, so they should be able to change parent clock rate.

When processing 4K video, VPU clock has to be set to higher rate than it
is default parent rate. Because of that, VPU clock should be able to
change parent clock rate.

Add CLK_SET_RATE_PARENT flag to tcon-lcd0, tcon-tv0 and ve.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
 drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
index 33980067b06e..3c32d7798f27 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
@@ -311,7 +311,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690,
 				       0, 3,	/* M */
 				       24, 1,	/* mux */
 				       BIT(31),	/* gate */
-				       0);
+				       CLK_SET_RATE_PARENT);
 
 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb1-ahb2",
 		      0x69c, BIT(0), 0);
@@ -691,7 +691,7 @@ static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0",
 			       tcon_lcd0_parents, 0xb60,
 			       24, 3,	/* mux */
 			       BIT(31),	/* gate */
-			       0);
+			       CLK_SET_RATE_PARENT);
 
 static SUNXI_CCU_GATE(bus_tcon_lcd0_clk, "bus-tcon-lcd0", "ahb3",
 		      0xb7c, BIT(0), 0);
@@ -706,7 +706,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0",
 				  8, 2,		/* P */
 				  24, 3,	/* mux */
 				  BIT(31),	/* gate */
-				  0);
+				  CLK_SET_RATE_PARENT);
 
 static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb3",
 		      0xb9c, BIT(0), 0);
-- 
2.21.0


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[PATCH v2 2/2] clk: sunxi-ng: nkmp: Explain why zero width check is needed

[Jernej Skrabec]

Add an explanation why zero width check is needed when generating factor
mask using GENMASK() macro.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
 drivers/clk/sunxi-ng/ccu_nkmp.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.c b/drivers/clk/sunxi-ng/ccu_nkmp.c
index 69dfc6de1c4e..cbcdf664f336 100644
--- a/drivers/clk/sunxi-ng/ccu_nkmp.c
+++ b/drivers/clk/sunxi-ng/ccu_nkmp.c
@@ -186,6 +186,12 @@ static int ccu_nkmp_set_rate(struct clk_hw *hw, unsigned long rate,
 
 	ccu_nkmp_find_best(parent_rate, rate, &_nkmp);
 
+	/*
+	 * If width is 0, GENMASK() macro may not generate expected mask (0)
+	 * as it falls under undefined behaviour by C standard due to shifts
+	 * which are equal or greater than width of left operand. This can
+	 * be easily avoided by explicitly checking if width is 0.
+	 */
 	if (nkmp->n.width)
 		n_mask = GENMASK(nkmp->n.width + nkmp->n.shift - 1,
 				 nkmp->n.shift);
-- 
2.21.0


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Re: [PATCH v2 0/2] clk: sunxi-ng: H6 related clock fixes

[Maxime Ripard]

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On Wed, Apr 03, 2019 at 05:14:02PM +0200, Jernej Skrabec wrote:
> During linux-next testing on Allwinner H6, I found several issues with
> clock driver. This patch series fixes them.
>
> Patch 1 allows video and vpu related clocks to set parent rate.
> Patch 2 adds a comment with short explanation why zero width check is
> needed.

Applied both, thanks!
Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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