From: Catalin Marinas <catalin.marinas@arm.com>
To: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: john.garry@huawei.com, Will Deacon <will.deacon@arm.com>,
qiuzhenfa@hisilicon.com, linux-arm-kernel@lists.infradead.org,
guohanjun@huawei.com
Subject: Re: [PATCH 2/2] arm64: cacheinfo: Update cache_line_size detected from PPTT
Date: Sat, 27 Apr 2019 17:16:37 +0100 [thread overview]
Message-ID: <20190427161636.blc7dqsq7os4wvho@mbp> (raw)
In-Reply-To: <1556242821-5080-2-git-send-email-zhangshaokun@hisilicon.com>
On Fri, Apr 26, 2019 at 09:40:21AM +0800, Shaokun Zhang wrote:
> diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h
> index 926434f413fa..f120d48b27ac 100644
> --- a/arch/arm64/include/asm/cache.h
> +++ b/arch/arm64/include/asm/cache.h
> @@ -91,11 +91,7 @@ static inline u32 cache_type_cwg(void)
>
> #define __read_mostly __attribute__((__section__(".data..read_mostly")))
>
> -static inline int cache_line_size(void)
> -{
> - u32 cwg = cache_type_cwg();
> - return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
> -}
> +extern int cache_line_size(void);
Nitpick: no need for 'extern' on function prototypes.
> /*
> * Read the effective value of CTR_EL0.
> diff --git a/arch/arm64/kernel/cacheinfo.c b/arch/arm64/kernel/cacheinfo.c
> index 0bf0a835122f..0b26d53790a8 100644
> --- a/arch/arm64/kernel/cacheinfo.c
> +++ b/arch/arm64/kernel/cacheinfo.c
> @@ -28,6 +28,21 @@
> #define CLIDR_CTYPE(clidr, level) \
> (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level))
>
> +int cache_line_size(void)
> +{
> + u32 cwg = cache_type_cwg();
> +
> + if (cwg == 0)
> + return ARCH_DMA_MINALIGN;
> +#ifdef CONFIG_ACPI
> + /* compare cache line size detected from PPTT with CWG reporting */
> + if (coherency_max_size > (4 << cwg))
> + return coherency_max_size;
> +#endif
> +
> + return 4 << cwg;
> +}
I'd rather have cache_line_size() report the PPTT information if
available, ignoring CWG with a fallback to the latter if not available.
We don't use cache_line_size() for DMA cache coherency, only
performance, so I think it's safe to return a value smaller than CWG in
cache_line_size().
--
Catalin
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next prev parent reply other threads:[~2019-04-27 16:16 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-26 1:40 [PATCH 1/2] ACPI/PPTT: Add variable to record max cache line size Shaokun Zhang
2019-04-26 1:40 ` [PATCH 2/2] arm64: cacheinfo: Update cache_line_size detected from PPTT Shaokun Zhang
2019-04-26 17:18 ` Jeremy Linton
2019-04-27 16:12 ` Catalin Marinas
2019-04-29 11:12 ` Sudeep Holla
2019-04-29 11:06 ` Sudeep Holla
2019-04-27 16:16 ` Catalin Marinas [this message]
2019-04-30 1:32 ` Zhangshaokun
2019-04-26 17:02 ` [PATCH 1/2] ACPI/PPTT: Add variable to record max cache line size Jeremy Linton
2019-04-29 11:26 ` Sudeep Holla
2019-04-30 2:19 ` Zhangshaokun
2019-04-30 2:13 ` Zhangshaokun
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