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From: Maxime Ripard <maxime.ripard@bootlin.com>
To: "Clément Péron" <peron.clem@gmail.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
	devicetree <devicetree@vger.kernel.org>,
	linux-sunxi <linux-sunxi@googlegroups.com>,
	linux-kernel <linux-kernel@vger.kernel.org>,
	Chen-Yu Tsai <wens@csie.org>, Rob Herring <robh+dt@kernel.org>,
	Mauro Carvalho Chehab <mchehab@kernel.org>,
	linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
	linux-media@vger.kernel.org
Subject: Re: [PATCH v4 04/13] media: rc: sunxi: Add RXSTA bits definition
Date: Wed, 5 Jun 2019 22:00:20 +0200	[thread overview]
Message-ID: <20190605200020.tmyom3lg3inu6vvf@flea> (raw)
In-Reply-To: <CAJiuCceZa=WEiF8_LK+jDdiXOn1i8+z8Smr6YKCpo9_XftgueQ@mail.gmail.com>

On Wed, Jun 05, 2019 at 02:44:06PM +0200, Clément Péron wrote:
> Hi Maxime,
>
> On Wed, 5 Jun 2019 at 11:51, Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> >
> > On Tue, Jun 04, 2019 at 06:29:50PM +0200, Clément Péron wrote:
> > > We are using RXINT bits definition when looking at RXSTA register.
> > >
> > > These bits are equal but it's not really proper.
> > >
> > > Introduce the RXSTA bits and use them to have coherency.
> > >
> > > Signed-off-by: Clément Péron <peron.clem@gmail.com>
> > > ---
> > >  drivers/media/rc/sunxi-cir.c | 18 ++++++++++++------
> > >  1 file changed, 12 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
> > > index 0504ebfc831f..572bd2257d35 100644
> > > --- a/drivers/media/rc/sunxi-cir.c
> > > +++ b/drivers/media/rc/sunxi-cir.c
> > > @@ -48,11 +48,11 @@
> > >
> > >  /* Rx Interrupt Enable */
> > >  #define SUNXI_IR_RXINT_REG    0x2C
> > > -/* Rx FIFO Overflow */
> > > +/* Rx FIFO Overflow Interrupt Enable */
> > >  #define REG_RXINT_ROI_EN             BIT(0)
> > > -/* Rx Packet End */
> > > +/* Rx Packet End Interrupt Enable */
> > >  #define REG_RXINT_RPEI_EN            BIT(1)
> > > -/* Rx FIFO Data Available */
> > > +/* Rx FIFO Data Available Interrupt Enable */
> > >  #define REG_RXINT_RAI_EN             BIT(4)
> > >
> > >  /* Rx FIFO available byte level */
> > > @@ -60,6 +60,12 @@
> > >
> > >  /* Rx Interrupt Status */
> > >  #define SUNXI_IR_RXSTA_REG    0x30
> > > +/* Rx FIFO Overflow */
> > > +#define REG_RXSTA_ROI                        BIT(0)
> > > +/* Rx Packet End */
> > > +#define REG_RXSTA_RPE                        BIT(1)
> > > +/* Rx FIFO Data Available */
> > > +#define REG_RXSTA_RA                 BIT(4)
> >
> > I'm fine with it on principle, but if the consistency needs to be
> > maintained then we could just reuse the above defines
>
> There is no comment why we can reuse them, they can also be some wrong
> case for example the RXINT_DRQ_EN bit is not present in RXSTA and same
> for STAT bit present in RXSTA and not present in RXINT.
>
> I have discover and read this code a month ago and this logic is
> really not obvious nor explain.
>
> Maybe this hack could be done when we will introduce a quirks, but for
> the moment I really think that it's more proper and readable to
> introduce them properly.

I don't think we understood each other :)

I was talking about having something like

#define REG_RXSTA_ROI  REG_RXINT_ROI_EN

Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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  reply	other threads:[~2019-06-05 20:00 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-04 16:29 [PATCH v4 00/13] Allwinner A64/H6 IR support Clément Péron
2019-06-04 16:29 ` [PATCH v4 01/13] dt-bindings: media: sunxi-ir: Add A31 compatible Clément Péron
2019-06-05  9:49   ` Maxime Ripard
2019-06-04 16:29 ` [PATCH v4 02/13] media: rc: Introduce sunxi_ir_quirks Clément Péron
2019-06-05  9:49   ` Maxime Ripard
2019-06-04 16:29 ` [PATCH v4 03/13] media: rc: sunxi: Add A31 compatible Clément Péron
2019-06-05  9:49   ` Maxime Ripard
2019-06-04 16:29 ` [PATCH v4 04/13] media: rc: sunxi: Add RXSTA bits definition Clément Péron
2019-06-05  9:51   ` Maxime Ripard
2019-06-05 12:44     ` Clément Péron
2019-06-05 20:00       ` Maxime Ripard [this message]
2019-06-05 20:34         ` Clément Péron
2019-06-04 16:29 ` [PATCH v4 05/13] ARM: dts: sunxi: Prefer A31 bindings for IR Clément Péron
2019-06-04 16:29 ` [PATCH v4 06/13] " Clément Péron
2019-06-04 16:29 ` [PATCH v4 07/13] dt-bindings: media: sunxi-ir: Add A64 compatible Clément Péron
2019-06-04 16:29 ` [PATCH v4 08/13] arm64: dts: allwinner: a64: Add IR node Clément Péron
2019-06-04 16:29 ` [PATCH v4 09/13] arm64: dts: allwinner: a64: Enable IR on Orange Pi Win Clément Péron
2019-06-04 16:29 ` [PATCH v4 10/13] dt-bindings: media: sunxi-ir: Add H6 compatible Clément Péron
2019-06-04 16:29 ` [PATCH v4 11/13] arm64: dts: allwinner: h6: Add IR receiver node Clément Péron
2019-06-04 16:29 ` [PATCH v4 12/13] arm64: dts: allwinner: h6: Enable IR on H6 boards Clément Péron
2019-06-04 16:29 ` [PATCH v4 13/13] arm64: defconfig: Enable IR SUNXI option Clément Péron

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