* [PATCH 01/22] ARM: dts: r7s9210: Add RSPI
2019-06-21 9:13 [GIT PULL] Renesas ARM Based SoC DT Updates for v5.3 Simon Horman
@ 2019-06-21 9:13 ` Simon Horman
2019-06-21 9:13 ` [PATCH 02/22] ARM: dts: r7s9210: Add Ethernet support Simon Horman
` (21 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Simon Horman @ 2019-06-21 9:13 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Simon Horman, Chris Brandt, Magnus Damm, linux-arm-kernel
From: Chris Brandt <chris.brandt@renesas.com>
Add RSPI support for RZ/A2 SoC.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r7s9210.dtsi | 45 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/arch/arm/boot/dts/r7s9210.dtsi b/arch/arm/boot/dts/r7s9210.dtsi
index 22baa96f5974..8423004bb4b7 100644
--- a/arch/arm/boot/dts/r7s9210.dtsi
+++ b/arch/arm/boot/dts/r7s9210.dtsi
@@ -146,6 +146,51 @@
status = "disabled";
};
+ spi0: spi@e800c800 {
+ compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz";
+ reg = <0xe800c800 0x24>;
+ interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error", "rx", "tx";
+ clocks = <&cpg CPG_MOD 97>;
+ power-domains = <&cpg>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi1: spi@e800d000 {
+ compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz";
+ reg = <0xe800d000 0x24>;
+ interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error", "rx", "tx";
+ clocks = <&cpg CPG_MOD 96>;
+ power-domains = <&cpg>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi2: spi@e800d800 {
+ compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz";
+ reg = <0xe800d800 0x24>;
+ interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error", "rx", "tx";
+ clocks = <&cpg CPG_MOD 95>;
+ power-domains = <&cpg>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
ostm0: timer@e803b000 {
compatible = "renesas,r7s9210-ostm", "renesas,ostm";
reg = <0xe803b000 0x30>;
--
2.11.0
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^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 02/22] ARM: dts: r7s9210: Add Ethernet support
2019-06-21 9:13 [GIT PULL] Renesas ARM Based SoC DT Updates for v5.3 Simon Horman
2019-06-21 9:13 ` [PATCH 01/22] ARM: dts: r7s9210: Add RSPI Simon Horman
@ 2019-06-21 9:13 ` Simon Horman
2019-06-21 9:13 ` [PATCH 03/22] ARM: dts: r7s9210: Add RIIC support Simon Horman
` (20 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Simon Horman @ 2019-06-21 9:13 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Simon Horman, Chris Brandt, Magnus Damm, linux-arm-kernel
From: Chris Brandt <chris.brandt@renesas.com>
Add Ethernet support for the RZ/A2 SoC.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r7s9210.dtsi | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm/boot/dts/r7s9210.dtsi b/arch/arm/boot/dts/r7s9210.dtsi
index 8423004bb4b7..8e9738467bfa 100644
--- a/arch/arm/boot/dts/r7s9210.dtsi
+++ b/arch/arm/boot/dts/r7s9210.dtsi
@@ -191,6 +191,31 @@
status = "disabled";
};
+ ether0: ethernet@e8204000 {
+ compatible = "renesas,ether-r7s9210";
+ reg = <0xe8204000 0x200>;
+ interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 65>;
+ power-domains = <&cpg>;
+
+ phy-mode = "rmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ ether1: ethernet@e8204200 {
+ compatible = "renesas,ether-r7s9210";
+ reg = <0xe8204200 0x200>;
+ interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 64>;
+ power-domains = <&cpg>;
+ phy-mode = "rmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
ostm0: timer@e803b000 {
compatible = "renesas,r7s9210-ostm", "renesas,ostm";
reg = <0xe803b000 0x30>;
--
2.11.0
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^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 03/22] ARM: dts: r7s9210: Add RIIC support
2019-06-21 9:13 [GIT PULL] Renesas ARM Based SoC DT Updates for v5.3 Simon Horman
2019-06-21 9:13 ` [PATCH 01/22] ARM: dts: r7s9210: Add RSPI Simon Horman
2019-06-21 9:13 ` [PATCH 02/22] ARM: dts: r7s9210: Add Ethernet support Simon Horman
@ 2019-06-21 9:13 ` Simon Horman
2019-06-21 9:13 ` [PATCH 04/22] ARM: dts: r7s9210: Add SDHI support Simon Horman
` (19 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Simon Horman @ 2019-06-21 9:13 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Simon Horman, Chris Brandt, Magnus Damm, linux-arm-kernel
From: Chris Brandt <chris.brandt@renesas.com>
Add I2C support for the R7S9210 (RZ/A2) SoC.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r7s9210.dtsi | 76 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 76 insertions(+)
diff --git a/arch/arm/boot/dts/r7s9210.dtsi b/arch/arm/boot/dts/r7s9210.dtsi
index 8e9738467bfa..1cd982c9920f 100644
--- a/arch/arm/boot/dts/r7s9210.dtsi
+++ b/arch/arm/boot/dts/r7s9210.dtsi
@@ -216,6 +216,82 @@
status = "disabled";
};
+ i2c0: i2c@e803a000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,riic-r7s9210", "renesas,riic-rz";
+ reg = <0xe803a000 0x44>;
+ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 233 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 87>;
+ power-domains = <&cpg>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@e803a400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,riic-r7s9210", "renesas,riic-rz";
+ reg = <0xe803a400 0x44>;
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 86>;
+ power-domains = <&cpg>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@e803a800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,riic-r7s9210", "renesas,riic-rz";
+ reg = <0xe803a800 0x44>;
+ interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 85>;
+ power-domains = <&cpg>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@e803ac00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,riic-r7s9210", "renesas,riic-rz";
+ reg = <0xe803ac00 0x44>;
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 257 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 258 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 84>;
+ power-domains = <&cpg>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
ostm0: timer@e803b000 {
compatible = "renesas,r7s9210-ostm", "renesas,ostm";
reg = <0xe803b000 0x30>;
--
2.11.0
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^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 04/22] ARM: dts: r7s9210: Add SDHI support
2019-06-21 9:13 [GIT PULL] Renesas ARM Based SoC DT Updates for v5.3 Simon Horman
` (2 preceding siblings ...)
2019-06-21 9:13 ` [PATCH 03/22] ARM: dts: r7s9210: Add RIIC support Simon Horman
@ 2019-06-21 9:13 ` Simon Horman
2019-06-21 9:13 ` [PATCH 05/22] ARM: dts: rza2mevb: Add Ethernet support Simon Horman
` (18 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Simon Horman @ 2019-06-21 9:13 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Simon Horman, Chris Brandt, Magnus Damm, linux-arm-kernel
From: Chris Brandt <chris.brandt@renesas.com>
Add SDHI support for the R7S9210 (RZ/A2) SoC.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r7s9210.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/r7s9210.dtsi b/arch/arm/boot/dts/r7s9210.dtsi
index 1cd982c9920f..2eaa5eeba509 100644
--- a/arch/arm/boot/dts/r7s9210.dtsi
+++ b/arch/arm/boot/dts/r7s9210.dtsi
@@ -322,6 +322,30 @@
status = "disabled";
};
+ sdhi0: sd@e8228000 {
+ compatible = "renesas,sdhi-r7s9210";
+ reg = <0xe8228000 0x8c0>;
+ interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 103>, <&cpg CPG_MOD 102>;
+ clock-names = "core", "cd";
+ power-domains = <&cpg>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ status = "disabled";
+ };
+
+ sdhi1: sd@e822a000 {
+ compatible = "renesas,sdhi-r7s9210";
+ reg = <0xe822a000 0x8c0>;
+ interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 101>, <&cpg CPG_MOD 100>;
+ clock-names = "core", "cd";
+ power-domains = <&cpg>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ status = "disabled";
+ };
+
gic: interrupt-controller@e8221000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.11.0
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^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 05/22] ARM: dts: rza2mevb: Add Ethernet support
2019-06-21 9:13 [GIT PULL] Renesas ARM Based SoC DT Updates for v5.3 Simon Horman
` (3 preceding siblings ...)
2019-06-21 9:13 ` [PATCH 04/22] ARM: dts: r7s9210: Add SDHI support Simon Horman
@ 2019-06-21 9:13 ` Simon Horman
2019-06-21 9:13 ` [PATCH 06/22] ARM: dts: rza2mevb: Add SDHI support Simon Horman
` (17 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Simon Horman @ 2019-06-21 9:13 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Simon Horman, Chris Brandt, Magnus Damm, linux-arm-kernel
From: Chris Brandt <chris.brandt@renesas.com>
The RZ/A2M EVB sub board has 2 Ethernet jacks on it.
Set switch SW6_4 to ON to use Ethernet Ch-0
Set switch SW6_5 to ON to use Ethernet Ch-1
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r7s9210-rza2mevb.dts | 50 ++++++++++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/arch/arm/boot/dts/r7s9210-rza2mevb.dts b/arch/arm/boot/dts/r7s9210-rza2mevb.dts
index 991e09de1219..1544f3bab3f8 100644
--- a/arch/arm/boot/dts/r7s9210-rza2mevb.dts
+++ b/arch/arm/boot/dts/r7s9210-rza2mevb.dts
@@ -62,6 +62,34 @@
pinmux = <RZA2_PINMUX(PORT9, 0, 4)>, /* TxD4 */
<RZA2_PINMUX(PORT9, 1, 4)>; /* RxD4 */
};
+
+ eth0_pins: eth0 {
+ pinmux = <RZA2_PINMUX(PORTE, 0, 7)>, /* REF50CK0 */
+ <RZA2_PINMUX(PORT6, 1, 7)>, /* RMMI0_TXDEN */
+ <RZA2_PINMUX(PORT6, 2, 7)>, /* RMII0_TXD0 */
+ <RZA2_PINMUX(PORT6, 3, 7)>, /* RMII0_TXD1 */
+ <RZA2_PINMUX(PORTE, 4, 7)>, /* RMII0_CRSDV */
+ <RZA2_PINMUX(PORTE, 1, 7)>, /* RMII0_RXD0 */
+ <RZA2_PINMUX(PORTE, 2, 7)>, /* RMII0_RXD1 */
+ <RZA2_PINMUX(PORTE, 3, 7)>, /* RMII0_RXER */
+ <RZA2_PINMUX(PORTE, 5, 1)>, /* ET0_MDC */
+ <RZA2_PINMUX(PORTE, 6, 1)>, /* ET0_MDIO */
+ <RZA2_PINMUX(PORTL, 0, 5)>; /* IRQ4 */
+ };
+
+ eth1_pins: eth1 {
+ pinmux = <RZA2_PINMUX(PORTK, 3, 7)>, /* REF50CK1 */
+ <RZA2_PINMUX(PORTK, 0, 7)>, /* RMMI1_TXDEN */
+ <RZA2_PINMUX(PORTK, 1, 7)>, /* RMII1_TXD0 */
+ <RZA2_PINMUX(PORTK, 2, 7)>, /* RMII1_TXD1 */
+ <RZA2_PINMUX(PORT3, 2, 7)>, /* RMII1_CRSDV */
+ <RZA2_PINMUX(PORTK, 4, 7)>, /* RMII1_RXD0 */
+ <RZA2_PINMUX(PORT3, 5, 7)>, /* RMII1_RXD1 */
+ <RZA2_PINMUX(PORT3, 1, 7)>, /* RMII1_RXER */
+ <RZA2_PINMUX(PORT3, 3, 1)>, /* ET1_MDC */
+ <RZA2_PINMUX(PORT3, 4, 1)>, /* ET1_MDIO */
+ <RZA2_PINMUX(PORTL, 1, 5)>; /* IRQ5 */
+ };
};
/* High resolution System tick timers */
@@ -80,3 +108,25 @@
status = "okay";
};
+
+ðer0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <ð0_pins>;
+ status = "okay";
+ renesas,no-ether-link;
+ phy-handle = <&phy0>;
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+ðer1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <ð1_pins>;
+ status = "okay";
+ renesas,no-ether-link;
+ phy-handle = <&phy1>;
+ phy1: ethernet-phy@1 {
+ reg = <0>;
+ };
+};
--
2.11.0
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^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 06/22] ARM: dts: rza2mevb: Add SDHI support
2019-06-21 9:13 [GIT PULL] Renesas ARM Based SoC DT Updates for v5.3 Simon Horman
` (4 preceding siblings ...)
2019-06-21 9:13 ` [PATCH 05/22] ARM: dts: rza2mevb: Add Ethernet support Simon Horman
@ 2019-06-21 9:13 ` Simon Horman
2019-06-21 9:13 ` [PATCH 07/22] ARM: dts: rza2mevb: add ethernet aliases Simon Horman
` (16 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Simon Horman @ 2019-06-21 9:13 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Simon Horman, Chris Brandt, Magnus Damm, linux-arm-kernel
From: Chris Brandt <chris.brandt@renesas.com>
The RZ/A2M EVB supports 2 SD card slots. A micro SD slot on the CPU
board, and a full SD card slot on the sub board.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r7s9210-rza2mevb.dts | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/r7s9210-rza2mevb.dts b/arch/arm/boot/dts/r7s9210-rza2mevb.dts
index 1544f3bab3f8..a328426a0409 100644
--- a/arch/arm/boot/dts/r7s9210-rza2mevb.dts
+++ b/arch/arm/boot/dts/r7s9210-rza2mevb.dts
@@ -90,6 +90,16 @@
<RZA2_PINMUX(PORT3, 4, 1)>, /* ET1_MDIO */
<RZA2_PINMUX(PORTL, 1, 5)>; /* IRQ5 */
};
+
+ sdhi0_pins: sdhi0 {
+ pinmux = <RZA2_PINMUX(PORT5, 0, 3)>, /* SD0_CD */
+ <RZA2_PINMUX(PORT5, 1, 3)>; /* SD0_WP */
+ };
+
+ sdhi1_pins: sdhi1 {
+ pinmux = <RZA2_PINMUX(PORT5, 4, 3)>, /* SD1_CD */
+ <RZA2_PINMUX(PORT5, 5, 3)>; /* SD1_WP */
+ };
};
/* High resolution System tick timers */
@@ -130,3 +140,17 @@
reg = <0>;
};
};
+
+&sdhi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhi0_pins>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&sdhi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhi1_pins>;
+ bus-width = <4>;
+ status = "okay";
+};
--
2.11.0
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^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 07/22] ARM: dts: rza2mevb: add ethernet aliases
2019-06-21 9:13 [GIT PULL] Renesas ARM Based SoC DT Updates for v5.3 Simon Horman
` (5 preceding siblings ...)
2019-06-21 9:13 ` [PATCH 06/22] ARM: dts: rza2mevb: Add SDHI support Simon Horman
@ 2019-06-21 9:13 ` Simon Horman
2019-06-21 9:13 ` [PATCH 08/22] ARM: dts: r7s9210: Add USB clock Simon Horman
` (15 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Simon Horman @ 2019-06-21 9:13 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Simon Horman, Chris Brandt, Magnus Damm, linux-arm-kernel
From: Chris Brandt <chris.brandt@renesas.com>
Add ethernet aliases so u-boot can find the device nodes.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r7s9210-rza2mevb.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/r7s9210-rza2mevb.dts b/arch/arm/boot/dts/r7s9210-rza2mevb.dts
index a328426a0409..e720a22eaf58 100644
--- a/arch/arm/boot/dts/r7s9210-rza2mevb.dts
+++ b/arch/arm/boot/dts/r7s9210-rza2mevb.dts
@@ -17,6 +17,8 @@
aliases {
serial0 = &scif4;
+ ethernet0 = ðer0;
+ ethernet1 = ðer1;
};
chosen {
--
2.11.0
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^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 08/22] ARM: dts: r7s9210: Add USB clock
2019-06-21 9:13 [GIT PULL] Renesas ARM Based SoC DT Updates for v5.3 Simon Horman
` (6 preceding siblings ...)
2019-06-21 9:13 ` [PATCH 07/22] ARM: dts: rza2mevb: add ethernet aliases Simon Horman
@ 2019-06-21 9:13 ` Simon Horman
2019-06-21 9:13 ` [PATCH 09/22] ARM: dts: rza2mevb: Add 48MHz " Simon Horman
` (14 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Simon Horman @ 2019-06-21 9:13 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Simon Horman, Chris Brandt, Magnus Damm, linux-arm-kernel
From: Chris Brandt <chris.brandt@renesas.com>
Add USB clock node. If present, this clock input must be 48MHz.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r7s9210.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/r7s9210.dtsi b/arch/arm/boot/dts/r7s9210.dtsi
index 2eaa5eeba509..73041f04fef5 100644
--- a/arch/arm/boot/dts/r7s9210.dtsi
+++ b/arch/arm/boot/dts/r7s9210.dtsi
@@ -30,6 +30,13 @@
clock-frequency = <0>;
};
+ usb_x1_clk: usb_x1 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ /* If clk present, value (48000000) must be set by board */
+ clock-frequency = <0>;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
--
2.11.0
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^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 09/22] ARM: dts: rza2mevb: Add 48MHz USB clock
2019-06-21 9:13 [GIT PULL] Renesas ARM Based SoC DT Updates for v5.3 Simon Horman
` (7 preceding siblings ...)
2019-06-21 9:13 ` [PATCH 08/22] ARM: dts: r7s9210: Add USB clock Simon Horman
@ 2019-06-21 9:13 ` Simon Horman
2019-06-21 9:13 ` [PATCH 10/22] ARM: dts: r8a779x: Configure PMIC IRQ pinmux Simon Horman
` (13 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Simon Horman @ 2019-06-21 9:13 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Simon Horman, Chris Brandt, Magnus Damm, linux-arm-kernel
From: Chris Brandt <chris.brandt@renesas.com>
The RZ/A2M EVB has a 48MHz clock attached to USB_X1.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r7s9210-rza2mevb.dts | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/r7s9210-rza2mevb.dts b/arch/arm/boot/dts/r7s9210-rza2mevb.dts
index e720a22eaf58..fa44e35e0fda 100644
--- a/arch/arm/boot/dts/r7s9210-rza2mevb.dts
+++ b/arch/arm/boot/dts/r7s9210-rza2mevb.dts
@@ -58,6 +58,11 @@
clock-frequency = <32768>;
};
+/* USB_X1 */
+&usb_x1_clk {
+ clock-frequency = <48000000>;
+};
+
&pinctrl {
/* Serial Console */
scif4_pins: serial4 {
--
2.11.0
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^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 10/22] ARM: dts: r8a779x: Configure PMIC IRQ pinmux
2019-06-21 9:13 [GIT PULL] Renesas ARM Based SoC DT Updates for v5.3 Simon Horman
` (8 preceding siblings ...)
2019-06-21 9:13 ` [PATCH 09/22] ARM: dts: rza2mevb: Add 48MHz " Simon Horman
@ 2019-06-21 9:13 ` Simon Horman
2019-06-21 9:13 ` [PATCH 11/22] ARM: dts: r7s72100: Add IRQC device node Simon Horman
` (12 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Simon Horman @ 2019-06-21 9:13 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Simon Horman, Magnus Damm, linux-arm-kernel, Marek Vasut
From: Marek Vasut <marek.vasut+renesas@gmail.com>
The PMIC IRQ line pin multiplexing configuration is missing from the DTs.
Since the line is configured correctly by default, the system works fine.
However, add the IRQ line pin multiplexing configuration for completeness.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7790-lager.dts | 7 +++++++
arch/arm/boot/dts/r8a7790-stout.dts | 7 ++++++-
arch/arm/boot/dts/r8a7791-koelsch.dts | 7 +++++++
arch/arm/boot/dts/r8a7791-porter.dts | 7 +++++++
arch/arm/boot/dts/r8a7792-blanche.dts | 7 +++++++
arch/arm/boot/dts/r8a7793-gose.dts | 7 +++++++
6 files changed, 41 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 7b9508e83d46..d637b9727808 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -423,6 +423,8 @@
*/
i2cpwr: i2c-13 {
compatible = "i2c-demux-pinctrl";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_irq_pins>;
i2c-parent = <&iic3>, <&i2c3>;
i2c-bus-name = "i2c-pwr";
#address-cells = <1>;
@@ -615,6 +617,11 @@
function = "iic3";
};
+ pmic_irq_pins: pmicirq {
+ groups = "intc_irq2";
+ function = "intc";
+ };
+
hsusb_pins: hsusb {
groups = "usb0_ovc_vbus";
function = "usb0";
diff --git a/arch/arm/boot/dts/r8a7790-stout.dts b/arch/arm/boot/dts/r8a7790-stout.dts
index 7a7d3b84d1a6..ad68e6034b43 100644
--- a/arch/arm/boot/dts/r8a7790-stout.dts
+++ b/arch/arm/boot/dts/r8a7790-stout.dts
@@ -179,6 +179,11 @@
function = "iic3";
};
+ pmic_irq_pins: pmicirq {
+ groups = "intc_irq2";
+ function = "intc";
+ };
+
usb0_pins: usb0 {
groups = "usb0";
function = "usb0";
@@ -317,7 +322,7 @@
&iic3 {
pinctrl-names = "default";
- pinctrl-0 = <&iic3_pins>;
+ pinctrl-0 = <&iic3_pins &pmic_irq_pins>;
status = "okay";
pmic@58 {
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index e6580aa0cea3..a116bfc11f0b 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -540,6 +540,11 @@
function = "intc";
};
+ pmic_irq_pins: pmicirq {
+ groups = "intc_irq2";
+ function = "intc";
+ };
+
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
@@ -776,6 +781,8 @@
};
&i2c6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_irq_pins>;
status = "okay";
clock-frequency = <100000>;
diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts
index fefdf8238bbe..e08d257f5d0c 100644
--- a/arch/arm/boot/dts/r8a7791-porter.dts
+++ b/arch/arm/boot/dts/r8a7791-porter.dts
@@ -228,6 +228,11 @@
function = "intc";
};
+ pmic_irq_pins: pmicirq {
+ groups = "intc_irq2";
+ function = "intc";
+ };
+
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
@@ -373,6 +378,8 @@
};
&i2c6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_irq_pins>;
status = "okay";
clock-frequency = <100000>;
diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts
index b6fa80c3b07e..b7af14de7c8e 100644
--- a/arch/arm/boot/dts/r8a7792-blanche.dts
+++ b/arch/arm/boot/dts/r8a7792-blanche.dts
@@ -234,6 +234,11 @@
groups = "du1_rgb666", "du1_sync", "du1_disp";
function = "du1";
};
+
+ pmic_irq_pins: pmicirq {
+ groups = "intc_irq2";
+ function = "intc";
+ };
};
&rwdt {
@@ -314,6 +319,8 @@
pmic@58 {
compatible = "dlg,da9063";
reg = <0x58>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_irq_pins>;
interrupt-parent = <&irqc>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts
index f51601af89a2..9984ebf06695 100644
--- a/arch/arm/boot/dts/r8a7793-gose.dts
+++ b/arch/arm/boot/dts/r8a7793-gose.dts
@@ -514,6 +514,11 @@
function = "intc";
};
+ pmic_irq_pins: pmicirq {
+ groups = "intc_irq2";
+ function = "intc";
+ };
+
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
@@ -711,6 +716,8 @@
};
&i2c6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_irq_pins>;
status = "okay";
clock-frequency = <100000>;
--
2.11.0
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^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 11/22] ARM: dts: r7s72100: Add IRQC device node
2019-06-21 9:13 [GIT PULL] Renesas ARM Based SoC DT Updates for v5.3 Simon Horman
` (9 preceding siblings ...)
2019-06-21 9:13 ` [PATCH 10/22] ARM: dts: r8a779x: Configure PMIC IRQ pinmux Simon Horman
@ 2019-06-21 9:13 ` Simon Horman
2019-06-21 9:13 ` [PATCH 12/22] ARM: dts: rskrza1: Add input switches Simon Horman
` (11 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Simon Horman @ 2019-06-21 9:13 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Simon Horman, Magnus Damm, Geert Uytterhoeven, linux-arm-kernel
From: Geert Uytterhoeven <geert+renesas@glider.be>
Enable support for the IRQC on RZ/A1H, which is a small front-end to the
GIC. This allows to use up to 8 external interrupts with configurable
sense select.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r7s72100.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index 2211f88ede2a..d03dcd919d6f 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -670,6 +670,25 @@
status = "disabled";
};
+ irqc: interrupt-controller@fcfef800 {
+ compatible = "renesas,r7s72100-irqc",
+ "renesas,rza1-irqc";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0xfcfef800 0x6>;
+ interrupt-map =
+ <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <7 0>;
+ };
+
mtu2: timer@fcff0000 {
compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
reg = <0xfcff0000 0x400>;
--
2.11.0
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^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 12/22] ARM: dts: rskrza1: Add input switches
2019-06-21 9:13 [GIT PULL] Renesas ARM Based SoC DT Updates for v5.3 Simon Horman
` (10 preceding siblings ...)
2019-06-21 9:13 ` [PATCH 11/22] ARM: dts: r7s72100: Add IRQC device node Simon Horman
@ 2019-06-21 9:13 ` Simon Horman
2019-06-21 9:13 ` [PATCH 13/22] ARM: dts: r7s9210: Add USB Host support Simon Horman
` (10 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Simon Horman @ 2019-06-21 9:13 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Simon Horman, Magnus Damm, Geert Uytterhoeven, linux-arm-kernel
From: Geert Uytterhoeven <geert+renesas@glider.be>
Add support for input switches SW1-3 on the Renesas RZ/A1 RSK+RZA1
development board.
Note that this uses the IRQ interrupts, as the RZ/A1 GPIO controller
does not include interrupt support.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r7s72100-rskrza1.dts | 38 ++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts b/arch/arm/boot/dts/r7s72100-rskrza1.dts
index ff24301dc1be..99acfe4fe11a 100644
--- a/arch/arm/boot/dts/r7s72100-rskrza1.dts
+++ b/arch/arm/boot/dts/r7s72100-rskrza1.dts
@@ -8,6 +8,7 @@
/dts-v1/;
#include "r7s72100.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
/ {
@@ -28,6 +29,37 @@
reg = <0x08000000 0x02000000>;
};
+ keyboard {
+ compatible = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&keyboard_pins>;
+
+ key-1 {
+ interrupt-parent = <&irqc>;
+ interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
+ linux,code = <KEY_1>;
+ label = "SW1";
+ wakeup-source;
+ };
+
+ key-2 {
+ interrupt-parent = <&irqc>;
+ interrupts = <2 IRQ_TYPE_EDGE_BOTH>;
+ linux,code = <KEY_2>;
+ label = "SW2";
+ wakeup-source;
+ };
+
+ key-3 {
+ interrupt-parent = <&irqc>;
+ interrupts = <5 IRQ_TYPE_EDGE_BOTH>;
+ linux,code = <KEY_3>;
+ label = "SW3";
+ wakeup-source;
+ };
+ };
+
lbsc {
#address-cells = <1>;
#size-cells = <1>;
@@ -101,6 +133,12 @@
<RZA1_PINMUX(1, 7, 1)>; /* RIIC3SDA */
};
+ keyboard_pins: keyboard {
+ pinmux = <RZA1_PINMUX(1, 9, 3)>, /* IRQ3 */
+ <RZA1_PINMUX(1, 8, 3)>, /* IRQ2 */
+ <RZA1_PINMUX(1, 11, 3)>; /* IRQ5 */
+ };
+
/* Serial Console */
scif2_pins: serial2 {
pinmux = <RZA1_PINMUX(3, 0, 6)>, /* TxD2 */
--
2.11.0
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^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 13/22] ARM: dts: r7s9210: Add USB Host support
2019-06-21 9:13 [GIT PULL] Renesas ARM Based SoC DT Updates for v5.3 Simon Horman
` (11 preceding siblings ...)
2019-06-21 9:13 ` [PATCH 12/22] ARM: dts: rskrza1: Add input switches Simon Horman
@ 2019-06-21 9:13 ` Simon Horman
2019-06-21 9:13 ` [PATCH 14/22] ARM: dts: r7s9210: Add USB Device support Simon Horman
` (9 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Simon Horman @ 2019-06-21 9:13 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Simon Horman, Chris Brandt, Magnus Damm, linux-arm-kernel
From: Chris Brandt <chris.brandt@renesas.com>
Add EHCI and OHCI host support for RZ/A2.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r7s9210.dtsi | 66 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 66 insertions(+)
diff --git a/arch/arm/boot/dts/r7s9210.dtsi b/arch/arm/boot/dts/r7s9210.dtsi
index 73041f04fef5..066e6fed11aa 100644
--- a/arch/arm/boot/dts/r7s9210.dtsi
+++ b/arch/arm/boot/dts/r7s9210.dtsi
@@ -329,6 +329,72 @@
status = "disabled";
};
+ ohci0: usb@e8218000 {
+ compatible = "generic-ohci";
+ reg = <0xe8218000 0x100>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 61>;
+ phys = <&usb2_phy0>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ehci0: usb@e8218100 {
+ compatible = "generic-ehci";
+ reg = <0xe8218100 0x100>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 61>;
+ phys = <&usb2_phy0>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ usb2_phy0: usb-phy@e8218200 {
+ compatible = "renesas,usb2-phy-r7s9210", "renesas,rcar-gen3-usb2-phy";
+ reg = <0xe8218200 0x700>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 61>, <&usb_x1_clk>;
+ clock-names = "fck", "usb_x1";
+ power-domains = <&cpg>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ ohci1: usb@e821a000 {
+ compatible = "generic-ohci";
+ reg = <0xe821a000 0x100>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 60>;
+ phys = <&usb2_phy1>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ehci1: usb@e821a100 {
+ compatible = "generic-ehci";
+ reg = <0xe821a100 0x100>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 60>;
+ phys = <&usb2_phy1>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ usb2_phy1: usb-phy@e821a200 {
+ compatible = "renesas,usb2-phy-r7s9210", "renesas,rcar-gen3-usb2-phy";
+ reg = <0xe821a200 0x700>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 60>, <&usb_x1_clk>;
+ clock-names = "fck", "usb_x1";
+ power-domains = <&cpg>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
sdhi0: sd@e8228000 {
compatible = "renesas,sdhi-r7s9210";
reg = <0xe8228000 0x8c0>;
--
2.11.0
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^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 14/22] ARM: dts: r7s9210: Add USB Device support
2019-06-21 9:13 [GIT PULL] Renesas ARM Based SoC DT Updates for v5.3 Simon Horman
` (12 preceding siblings ...)
2019-06-21 9:13 ` [PATCH 13/22] ARM: dts: r7s9210: Add USB Host support Simon Horman
@ 2019-06-21 9:13 ` Simon Horman
2019-06-21 9:13 ` [PATCH 15/22] ARM: dts: rza2mevb: Add USB Host support Simon Horman
` (8 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Simon Horman @ 2019-06-21 9:13 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Simon Horman, Chris Brandt, Magnus Damm, linux-arm-kernel
From: Chris Brandt <chris.brandt@renesas.com>
Add USB Device support for RZ/A2.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r7s9210.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/r7s9210.dtsi b/arch/arm/boot/dts/r7s9210.dtsi
index 066e6fed11aa..3d0bbc1f4543 100644
--- a/arch/arm/boot/dts/r7s9210.dtsi
+++ b/arch/arm/boot/dts/r7s9210.dtsi
@@ -362,6 +362,18 @@
status = "disabled";
};
+ usbhs0: usb@e8219000 {
+ compatible = "renesas,usbhs-r7s9210", "renesas,rza2-usbhs";
+ reg = <0xe8219000 0x724>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 61>;
+ renesas,buswait = <7>;
+ phys = <&usb2_phy0>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
ohci1: usb@e821a000 {
compatible = "generic-ohci";
reg = <0xe821a000 0x100>;
@@ -395,6 +407,18 @@
status = "disabled";
};
+ usbhs1: usb@e821b000 {
+ compatible = "renesas,usbhs-r7s9210", "renesas,rza2-usbhs";
+ reg = <0xe821b000 0x724>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 60>;
+ renesas,buswait = <7>;
+ phys = <&usb2_phy1>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
sdhi0: sd@e8228000 {
compatible = "renesas,sdhi-r7s9210";
reg = <0xe8228000 0x8c0>;
--
2.11.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 15/22] ARM: dts: rza2mevb: Add USB Host support
2019-06-21 9:13 [GIT PULL] Renesas ARM Based SoC DT Updates for v5.3 Simon Horman
` (13 preceding siblings ...)
2019-06-21 9:13 ` [PATCH 14/22] ARM: dts: r7s9210: Add USB Device support Simon Horman
@ 2019-06-21 9:13 ` Simon Horman
2019-06-21 9:13 ` [PATCH 16/22] ARM: dts: renesas: Use ip=on for bootargs Simon Horman
` (7 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Simon Horman @ 2019-06-21 9:13 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Simon Horman, Chris Brandt, Magnus Damm, linux-arm-kernel
From: Chris Brandt <chris.brandt@renesas.com>
Enable USB Host support for both the Type-C connector on the CPU board
and the Type-A plug on the sub board.
Both boards are also capable of USB Device operation as well after the
appropriate Device Tree modifications.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r7s9210-rza2mevb.dts | 36 ++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/r7s9210-rza2mevb.dts b/arch/arm/boot/dts/r7s9210-rza2mevb.dts
index fa44e35e0fda..e140168da573 100644
--- a/arch/arm/boot/dts/r7s9210-rza2mevb.dts
+++ b/arch/arm/boot/dts/r7s9210-rza2mevb.dts
@@ -107,6 +107,18 @@
pinmux = <RZA2_PINMUX(PORT5, 4, 3)>, /* SD1_CD */
<RZA2_PINMUX(PORT5, 5, 3)>; /* SD1_WP */
};
+
+ usb0_pins: usb0 {
+ pinmux = <RZA2_PINMUX(PORT5, 2, 3)>, /* VBUSIN0 */
+ <RZA2_PINMUX(PORTC, 6, 1)>, /* VBUSEN0 */
+ <RZA2_PINMUX(PORTC, 7, 1)>; /* OVRCUR0 */
+ };
+
+ usb1_pins: usb1 {
+ pinmux = <RZA2_PINMUX(PORTC, 0, 1)>, /* VBUSIN1 */
+ <RZA2_PINMUX(PORTC, 5, 1)>, /* VBUSEN1 */
+ <RZA2_PINMUX(PORT7, 5, 5)>; /* OVRCUR1 */
+ };
};
/* High resolution System tick timers */
@@ -161,3 +173,27 @@
bus-width = <4>;
status = "okay";
};
+
+/* USB-0 as Host */
+&usb2_phy0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_pins>;
+ dr_mode = "host"; /* Requires JP3 to be fitted */
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+/* USB-1 as Host */
+&usb2_phy1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb1_pins>;
+ dr_mode = "host";
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
--
2.11.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 16/22] ARM: dts: renesas: Use ip=on for bootargs
2019-06-21 9:13 [GIT PULL] Renesas ARM Based SoC DT Updates for v5.3 Simon Horman
` (14 preceding siblings ...)
2019-06-21 9:13 ` [PATCH 15/22] ARM: dts: rza2mevb: Add USB Host support Simon Horman
@ 2019-06-21 9:13 ` Simon Horman
2019-06-21 9:13 ` [PATCH 17/22] ARM: dts: rza2mevb: sort nodes of rza2mevb board Simon Horman
` (6 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Simon Horman @ 2019-06-21 9:13 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Magnus Damm, Magnus Damm, linux-arm-kernel, Simon Horman
From: Magnus Damm <damm+renesas@opensource.se>
Convert bootargs from ip=dhcp to ip=on
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/emev2-kzm9d.dts | 2 +-
arch/arm/boot/dts/r7s72100-genmai.dts | 2 +-
arch/arm/boot/dts/r8a73a4-ape6evm.dts | 2 +-
arch/arm/boot/dts/r8a7740-armadillo800eva.dts | 2 +-
arch/arm/boot/dts/r8a7743-sk-rzg1m.dts | 2 +-
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 2 +-
arch/arm/boot/dts/r8a7745-sk-rzg1e.dts | 2 +-
arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 2 +-
arch/arm/boot/dts/r8a7778-bockw.dts | 2 +-
arch/arm/boot/dts/r8a7779-marzen.dts | 2 +-
arch/arm/boot/dts/r8a7790-lager.dts | 2 +-
arch/arm/boot/dts/r8a7790-stout.dts | 2 +-
arch/arm/boot/dts/r8a7791-koelsch.dts | 2 +-
arch/arm/boot/dts/r8a7791-porter.dts | 2 +-
arch/arm/boot/dts/r8a7792-blanche.dts | 2 +-
arch/arm/boot/dts/r8a7792-wheat.dts | 2 +-
arch/arm/boot/dts/r8a7793-gose.dts | 2 +-
arch/arm/boot/dts/r8a7794-alt.dts | 2 +-
arch/arm/boot/dts/r8a7794-silk.dts | 2 +-
arch/arm/boot/dts/sh73a0-kzm9g.dts | 2 +-
20 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts
index abfff54d6de5..0a27f034dd6b 100644
--- a/arch/arm/boot/dts/emev2-kzm9d.dts
+++ b/arch/arm/boot/dts/emev2-kzm9d.dts
@@ -25,7 +25,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial1:115200n8";
};
diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts
index 474baa0c7cfc..07d611d2b7b5 100644
--- a/arch/arm/boot/dts/r7s72100-genmai.dts
+++ b/arch/arm/boot/dts/r7s72100-genmai.dts
@@ -20,7 +20,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
index f70f4a3e5c43..a5351ddbf506 100644
--- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
@@ -19,7 +19,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
index 32757caa2584..758360a2edc3 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
@@ -21,7 +21,7 @@
};
chosen {
- bootargs = "earlyprintk ignore_loglevel root=/dev/nfs ip=dhcp rw";
+ bootargs = "earlyprintk ignore_loglevel root=/dev/nfs ip=on rw";
stdout-path = "serial0:115200n8";
};
diff --git a/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts b/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
index ca0e0fc9b246..807e7d0d6b62 100644
--- a/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
+++ b/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
@@ -17,7 +17,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
index 1db220cfc1a1..ce6603b0994b 100644
--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
@@ -42,7 +42,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial3:115200n8";
};
diff --git a/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts b/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts
index 655b10bb42d5..db72a801abe5 100644
--- a/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts
+++ b/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts
@@ -17,7 +17,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
index 2840eb0d6fd4..af78e77a4778 100644
--- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
+++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
@@ -18,7 +18,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial1:115200n8";
};
diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts
index 0b49956069fc..6c7b07c4b9d3 100644
--- a/arch/arm/boot/dts/r8a7778-bockw.dts
+++ b/arch/arm/boot/dts/r8a7778-bockw.dts
@@ -25,7 +25,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index d4bee1ec9044..c755f0b8fd0d 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -21,7 +21,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index d637b9727808..83cc619861b2 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -56,7 +56,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
diff --git a/arch/arm/boot/dts/r8a7790-stout.dts b/arch/arm/boot/dts/r8a7790-stout.dts
index ad68e6034b43..a315ba749aa4 100644
--- a/arch/arm/boot/dts/r8a7790-stout.dts
+++ b/arch/arm/boot/dts/r8a7790-stout.dts
@@ -19,7 +19,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index a116bfc11f0b..af6bd8fcd5a4 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -56,7 +56,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts
index e08d257f5d0c..d6cf16aac14d 100644
--- a/arch/arm/boot/dts/r8a7791-porter.dts
+++ b/arch/arm/boot/dts/r8a7791-porter.dts
@@ -31,7 +31,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts
index b7af14de7c8e..248eb717eb35 100644
--- a/arch/arm/boot/dts/r8a7792-blanche.dts
+++ b/arch/arm/boot/dts/r8a7792-blanche.dts
@@ -21,7 +21,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
diff --git a/arch/arm/boot/dts/r8a7792-wheat.dts b/arch/arm/boot/dts/r8a7792-wheat.dts
index f46f4567b3d4..bd2a63bdab3d 100644
--- a/arch/arm/boot/dts/r8a7792-wheat.dts
+++ b/arch/arm/boot/dts/r8a7792-wheat.dts
@@ -20,7 +20,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts
index 9984ebf06695..42f3313e6988 100644
--- a/arch/arm/boot/dts/r8a7793-gose.dts
+++ b/arch/arm/boot/dts/r8a7793-gose.dts
@@ -52,7 +52,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index 0ab3d8d57f6d..1d22fcdc5d22 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -22,7 +22,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts
index 60e91ebfa65d..b3177aea45d1 100644
--- a/arch/arm/boot/dts/r8a7794-silk.dts
+++ b/arch/arm/boot/dts/r8a7794-silk.dts
@@ -34,7 +34,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/sh73a0-kzm9g.dts
index daac0c6078c5..1916f31a30ff 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g.dts
@@ -36,7 +36,7 @@
};
chosen {
- bootargs = "root=/dev/nfs ip=dhcp ignore_loglevel rw";
+ bootargs = "root=/dev/nfs ip=on ignore_loglevel rw";
stdout-path = "serial0:115200n8";
};
--
2.11.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 17/22] ARM: dts: rza2mevb: sort nodes of rza2mevb board
2019-06-21 9:13 [GIT PULL] Renesas ARM Based SoC DT Updates for v5.3 Simon Horman
` (15 preceding siblings ...)
2019-06-21 9:13 ` [PATCH 16/22] ARM: dts: renesas: Use ip=on for bootargs Simon Horman
@ 2019-06-21 9:13 ` Simon Horman
2019-06-21 9:13 ` [PATCH 18/22] ARM: dts: r7s9210: Add IRQC device node Simon Horman
` (5 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Simon Horman @ 2019-06-21 9:13 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Yoshihiro Kaneko, Magnus Damm, linux-arm-kernel, Simon Horman
From: Yoshihiro Kaneko <ykaneko0929@gmail.com>
This patch sorts the nodes of arch/arm/boot/dts/r7s9210-rza2mevb.dts.
* Sort subnodes of root ("/") node alphabetically
* Sort following top-level nodes alphabetically
* Sort subnodes of pinctrl alphabetically
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
[simon: rebase and sort new ehci nodes]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r7s9210-rza2mevb.dts | 104 ++++++++++++++++-----------------
1 file changed, 52 insertions(+), 52 deletions(-)
diff --git a/arch/arm/boot/dts/r7s9210-rza2mevb.dts b/arch/arm/boot/dts/r7s9210-rza2mevb.dts
index e140168da573..49c40065741b 100644
--- a/arch/arm/boot/dts/r7s9210-rza2mevb.dts
+++ b/arch/arm/boot/dts/r7s9210-rza2mevb.dts
@@ -26,11 +26,6 @@
stdout-path = "serial0:115200n8";
};
- memory@40000000 {
- device_type = "memory";
- reg = <0x40000000 0x00800000>; /* HyperRAM */
- };
-
lbsc {
#address-cells = <1>;
#size-cells = <1>;
@@ -46,6 +41,41 @@
gpios = <&pinctrl RZA2_PIN(PORTC, 1) GPIO_ACTIVE_HIGH>;
};
};
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0x00800000>; /* HyperRAM */
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+ðer0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <ð0_pins>;
+ status = "okay";
+ renesas,no-ether-link;
+ phy-handle = <&phy0>;
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+ðer1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <ð1_pins>;
+ status = "okay";
+ renesas,no-ether-link;
+ phy-handle = <&phy1>;
+ phy1: ethernet-phy@1 {
+ reg = <0>;
+ };
};
/* EXTAL */
@@ -53,23 +83,16 @@
clock-frequency = <24000000>; /* 24MHz */
};
-/* RTC_X1 */
-&rtc_x1_clk {
- clock-frequency = <32768>;
+/* High resolution System tick timers */
+&ostm0 {
+ status = "okay";
};
-/* USB_X1 */
-&usb_x1_clk {
- clock-frequency = <48000000>;
+&ostm1 {
+ status = "okay";
};
&pinctrl {
- /* Serial Console */
- scif4_pins: serial4 {
- pinmux = <RZA2_PINMUX(PORT9, 0, 4)>, /* TxD4 */
- <RZA2_PINMUX(PORT9, 1, 4)>; /* RxD4 */
- };
-
eth0_pins: eth0 {
pinmux = <RZA2_PINMUX(PORTE, 0, 7)>, /* REF50CK0 */
<RZA2_PINMUX(PORT6, 1, 7)>, /* RMMI0_TXDEN */
@@ -98,6 +121,12 @@
<RZA2_PINMUX(PORTL, 1, 5)>; /* IRQ5 */
};
+ /* Serial Console */
+ scif4_pins: serial4 {
+ pinmux = <RZA2_PINMUX(PORT9, 0, 4)>, /* TxD4 */
+ <RZA2_PINMUX(PORT9, 1, 4)>; /* RxD4 */
+ };
+
sdhi0_pins: sdhi0 {
pinmux = <RZA2_PINMUX(PORT5, 0, 3)>, /* SD0_CD */
<RZA2_PINMUX(PORT5, 1, 3)>; /* SD0_WP */
@@ -121,13 +150,9 @@
};
};
-/* High resolution System tick timers */
-&ostm0 {
- status = "okay";
-};
-
-&ostm1 {
- status = "okay";
+/* RTC_X1 */
+&rtc_x1_clk {
+ clock-frequency = <32768>;
};
/* Serial Console */
@@ -138,28 +163,6 @@
status = "okay";
};
-ðer0 {
- pinctrl-names = "default";
- pinctrl-0 = <ð0_pins>;
- status = "okay";
- renesas,no-ether-link;
- phy-handle = <&phy0>;
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
-};
-
-ðer1 {
- pinctrl-names = "default";
- pinctrl-0 = <ð1_pins>;
- status = "okay";
- renesas,no-ether-link;
- phy-handle = <&phy1>;
- phy1: ethernet-phy@1 {
- reg = <0>;
- };
-};
-
&sdhi0 {
pinctrl-names = "default";
pinctrl-0 = <&sdhi0_pins>;
@@ -182,10 +185,6 @@
status = "okay";
};
-&ehci0 {
- status = "okay";
-};
-
/* USB-1 as Host */
&usb2_phy1 {
pinctrl-names = "default";
@@ -194,6 +193,7 @@
status = "okay";
};
-&ehci1 {
- status = "okay";
+/* USB_X1 */
+&usb_x1_clk {
+ clock-frequency = <48000000>;
};
--
2.11.0
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^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 18/22] ARM: dts: r7s9210: Add IRQC device node
2019-06-21 9:13 [GIT PULL] Renesas ARM Based SoC DT Updates for v5.3 Simon Horman
` (16 preceding siblings ...)
2019-06-21 9:13 ` [PATCH 17/22] ARM: dts: rza2mevb: sort nodes of rza2mevb board Simon Horman
@ 2019-06-21 9:13 ` Simon Horman
2019-06-21 9:13 ` [PATCH 19/22] ARM: dts: rza2mevb: Add input switch Simon Horman
` (4 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Simon Horman @ 2019-06-21 9:13 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Simon Horman, Chris Brandt, Magnus Damm, linux-arm-kernel
From: Chris Brandt <chris.brandt@renesas.com>
Enable support for the IRQC on RZ/A2M, which is a small front-end to the
GIC. This allows to use up to 8 external interrupts with configurable
sense select.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r7s9210.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/r7s9210.dtsi b/arch/arm/boot/dts/r7s9210.dtsi
index 3d0bbc1f4543..72b79770e336 100644
--- a/arch/arm/boot/dts/r7s9210.dtsi
+++ b/arch/arm/boot/dts/r7s9210.dtsi
@@ -473,6 +473,25 @@
reg = <0xfcfe8004 4>;
};
+ irqc: interrupt-controller@fcfef800 {
+ compatible = "renesas,r7s9210-irqc",
+ "renesas,rza1-irqc";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0xfcfef800 0x6>;
+ interrupt-map =
+ <0 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <7 0>;
+ };
+
pinctrl: pin-controller@fcffe000 {
compatible = "renesas,r7s9210-pinctrl";
reg = <0xfcffe000 0x1000>;
--
2.11.0
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^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 19/22] ARM: dts: rza2mevb: Add input switch
2019-06-21 9:13 [GIT PULL] Renesas ARM Based SoC DT Updates for v5.3 Simon Horman
` (17 preceding siblings ...)
2019-06-21 9:13 ` [PATCH 18/22] ARM: dts: r7s9210: Add IRQC device node Simon Horman
@ 2019-06-21 9:13 ` Simon Horman
2019-06-21 9:13 ` [PATCH 20/22] ARM: dts: iwg20d-q7-common: Fix SDHI1 VccQ regularor Simon Horman
` (3 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Simon Horman @ 2019-06-21 9:13 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Simon Horman, Chris Brandt, Magnus Damm, linux-arm-kernel
From: Chris Brandt <chris.brandt@renesas.com>
Add support for input switch SW3 on the Renesas RZ/A2M EVB
development board.
Note that this uses the IRQ interrupt, as the RZ/A2 GPIO controller
does not include interrupt support
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r7s9210-rza2mevb.dts | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/r7s9210-rza2mevb.dts b/arch/arm/boot/dts/r7s9210-rza2mevb.dts
index 49c40065741b..d062d02865e7 100644
--- a/arch/arm/boot/dts/r7s9210-rza2mevb.dts
+++ b/arch/arm/boot/dts/r7s9210-rza2mevb.dts
@@ -9,6 +9,7 @@
/dts-v1/;
#include "r7s9210.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/r7s9210-pinctrl.h>
/ {
@@ -26,6 +27,21 @@
stdout-path = "serial0:115200n8";
};
+ keyboard {
+ compatible = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&keyboard_pins>;
+
+ key-3 {
+ interrupt-parent = <&irqc>;
+ interrupts = <0 IRQ_TYPE_EDGE_BOTH>;
+ linux,code = <KEY_3>;
+ label = "SW3";
+ wakeup-source;
+ };
+ };
+
lbsc {
#address-cells = <1>;
#size-cells = <1>;
@@ -121,6 +137,10 @@
<RZA2_PINMUX(PORTL, 1, 5)>; /* IRQ5 */
};
+ keyboard_pins: keyboard {
+ pinmux = <RZA2_PINMUX(PORTJ, 1, 6)>; /* IRQ0 */
+ };
+
/* Serial Console */
scif4_pins: serial4 {
pinmux = <RZA2_PINMUX(PORT9, 0, 4)>, /* TxD4 */
--
2.11.0
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^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 20/22] ARM: dts: iwg20d-q7-common: Fix SDHI1 VccQ regularor
2019-06-21 9:13 [GIT PULL] Renesas ARM Based SoC DT Updates for v5.3 Simon Horman
` (18 preceding siblings ...)
2019-06-21 9:13 ` [PATCH 19/22] ARM: dts: rza2mevb: Add input switch Simon Horman
@ 2019-06-21 9:13 ` Simon Horman
2019-06-21 9:13 ` [PATCH 21/22] ARM: dts: iwg23s-sbc: Fix SDHI2 VccQ regulator Simon Horman
` (2 subsequent siblings)
22 siblings, 0 replies; 24+ messages in thread
From: Simon Horman @ 2019-06-21 9:13 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Fabrizio Castro, Simon Horman, Magnus Damm, linux-arm-kernel
From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
SDR50 isn't working anymore because the GPIO regulator
driver is using descriptors since
commit d6cd33ad7102 ("regulator: gpio: Convert to use descriptors")
which in turn causes the system to use the polarity of the
GPIOs (as specified in the DT) for selecting the states,
but the polarity specified in the DT is wrong.
This patch fixes the regulator DT definition, and that fixes
SDR50.
Fixes: 029efb3a03c5 ("ARM: dts: iwg20d-q7: Add SDHI1 support")
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/iwg20d-q7-common.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
index e2b1ab9b56e5..ae75a1db3d9a 100644
--- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
@@ -87,7 +87,7 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
- gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
--
2.11.0
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^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 21/22] ARM: dts: iwg23s-sbc: Fix SDHI2 VccQ regulator
2019-06-21 9:13 [GIT PULL] Renesas ARM Based SoC DT Updates for v5.3 Simon Horman
` (19 preceding siblings ...)
2019-06-21 9:13 ` [PATCH 20/22] ARM: dts: iwg20d-q7-common: Fix SDHI1 VccQ regularor Simon Horman
@ 2019-06-21 9:13 ` Simon Horman
2019-06-21 9:13 ` [PATCH 22/22] ARM: dts: r8a7792: Add CMT0 and CMT1 to r8a7792 Simon Horman
2019-06-25 11:45 ` [GIT PULL] Renesas ARM Based SoC DT Updates for v5.3 Olof Johansson
22 siblings, 0 replies; 24+ messages in thread
From: Simon Horman @ 2019-06-21 9:13 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Fabrizio Castro, Simon Horman, Magnus Damm, linux-arm-kernel
From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
SDR50 isn't working anymore because the GPIO regulator
driver is using descriptors since
commit d6cd33ad7102 ("regulator: gpio: Convert to use descriptors")
which in turn causes the system to use the polarity of the
GPIOs (as specified in the DT) for selecting the states,
but the polarity specified in the DT is wrong.
This patch fixes the regulator DT definition, and that fixes
SDR50.
Fixes: 9eb36b945b5c ("ARM: dts: iwg23s-sbc: Add uSD and eMMC support")
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
index af78e77a4778..450efe923008 100644
--- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
+++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
@@ -63,7 +63,7 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
- gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
--
2.11.0
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^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 22/22] ARM: dts: r8a7792: Add CMT0 and CMT1 to r8a7792
2019-06-21 9:13 [GIT PULL] Renesas ARM Based SoC DT Updates for v5.3 Simon Horman
` (20 preceding siblings ...)
2019-06-21 9:13 ` [PATCH 21/22] ARM: dts: iwg23s-sbc: Fix SDHI2 VccQ regulator Simon Horman
@ 2019-06-21 9:13 ` Simon Horman
2019-06-25 11:45 ` [GIT PULL] Renesas ARM Based SoC DT Updates for v5.3 Olof Johansson
22 siblings, 0 replies; 24+ messages in thread
From: Simon Horman @ 2019-06-21 9:13 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Magnus Damm, Magnus Damm, linux-arm-kernel, Simon Horman
From: Magnus Damm <damm+renesas@opensource.se>
Add CMT0 and CMT1 to the R-Car Gen2 V2H (r8a7792) SoC.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7792.dtsi | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index 38fb43d11b27..c4ea2d676030 100644
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -875,6 +875,40 @@
compatible = "renesas,prr";
reg = <0 0xff000044 0 4>;
};
+
+ cmt0: timer@ffca0000 {
+ compatible = "renesas,r8a7792-cmt0",
+ "renesas,rcar-gen2-cmt0";
+ reg = <0 0xffca0000 0 0x1004>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 124>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 124>;
+
+ status = "disabled";
+ };
+
+ cmt1: timer@e6130000 {
+ compatible = "renesas,r8a7792-cmt1",
+ "renesas,rcar-gen2-cmt1";
+ reg = <0 0xe6130000 0 0x1004>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 329>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 329>;
+
+ status = "disabled";
+ };
};
timer {
--
2.11.0
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^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [GIT PULL] Renesas ARM Based SoC DT Updates for v5.3
2019-06-21 9:13 [GIT PULL] Renesas ARM Based SoC DT Updates for v5.3 Simon Horman
` (21 preceding siblings ...)
2019-06-21 9:13 ` [PATCH 22/22] ARM: dts: r8a7792: Add CMT0 and CMT1 to r8a7792 Simon Horman
@ 2019-06-25 11:45 ` Olof Johansson
22 siblings, 0 replies; 24+ messages in thread
From: Olof Johansson @ 2019-06-25 11:45 UTC (permalink / raw)
To: Simon Horman
Cc: Arnd Bergmann, Kevin Hilman, Magnus Damm, linux-renesas-soc, arm,
linux-arm-kernel
On Fri, Jun 21, 2019 at 11:13:44AM +0200, Simon Horman wrote:
> Hi Olof, Hi Kevin, Hi Arnd,
>
> Please consider these Renesas ARM based SoC DT updates for v5.3.
>
>
> The following changes since commit a188339ca5a396acc588e5851ed7e19f66b0ebd9:
>
> Linux 5.2-rc1 (2019-05-19 15:47:09 -0700)
>
> are available in the git repository at:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-arm-dt-for-v5.3
>
> for you to fetch changes up to 9dd6f7c484fd2aaa468dfdf5087425ea9e4c7bf8:
>
> ARM: dts: r8a7792: Add CMT0 and CMT1 to r8a7792 (2019-06-21 09:45:37 +0200)
>
> ----------------------------------------------------------------
> Renesas ARM Based SoC DT Updates for v5.3
>
> * Renesas SoC based boards
> - Use ip=on for bootargs
>
> * Renesas R-Car Gen 2 SOC based boards
> - Configure PMIC IRQ pinmux
>
> * R-Car V2H (r8a7792) SoC
> - Describe CMT devices in DT
>
> * RZ/G1C (r8a77470) based iWave SBC (iwg23s-sbc) and
> RZ/G1N (r8a7744) based boards:
> - Correct SDHI2 VccQ regulator to fix SDR50 mode
>
> * RZ/A2M (r7s9210) based rza2mevb EVB
> RZ/A1H (r7s72100) based rskrza1 board
> - Describe input switch in DT
>
> * RZ/A2M (r7s9210) based rza2mevb EVB
> - Sort nodes to ease future maintenance
> - Add USB host, Ethernet and SDHI support
>
> * RZ/A2M (r7s9210) and RZ/A1H (r7s72100) SoCs
> - Describe IRQC device in DT
Merged, thanks!
-Olof
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^ permalink raw reply [flat|nested] 24+ messages in thread