[PATCH 1/2] perf/imx_ddr: add enhanced AXI ID filter support

From: Joakim Zhang <qiangqing.zhang@nxp.com>
To: "will@kernel.org" <will@kernel.org>,
	"mark.rutland@arm.com" <mark.rutland@arm.com>,
	"robin.murphy@arm.com" <robin.murphy@arm.com>,
	Frank Li <frank.li@nxp.com>
Cc: dl-linux-imx <linux-imx@nxp.com>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	Joakim Zhang <qiangqing.zhang@nxp.com>
Subject: [PATCH 1/2] perf/imx_ddr: add enhanced AXI ID filter support
Date: Fri, 6 Sep 2019 08:26:55 +0000	[thread overview]
Message-ID: <20190906082356.25485-1-qiangqing.zhang@nxp.com> (raw)

With DDR_CAP_AXI_ID_FILTER quirk, indicating HW supports AXI ID filter
which only can get bursts of reading/writing DDR, i.e. DDR read/write
request.

This patch add DDR_CAP_AXI_ID_ENHANCED_FILTER quirk, indicating HW
supports AXI ID filter which can get bytes of reading/writing DDR. This
feature is more meaningful due to we always care more about bandwidth.

Need select both above two qiurks together when HW support enhanced AXI
ID filter.

Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
---
 drivers/perf/fsl_imx8_ddr_perf.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c
index ce7345745b42..5f70dbfa9607 100644
--- a/drivers/perf/fsl_imx8_ddr_perf.c
+++ b/drivers/perf/fsl_imx8_ddr_perf.c
@@ -45,7 +45,8 @@
 static DEFINE_IDA(ddr_ida);
 
 /* DDR Perf hardware feature */
-#define DDR_CAP_AXI_ID_FILTER          0x1     /* support AXI ID filter */
+#define DDR_CAP_AXI_ID_FILTER			BIT(1)     /* support AXI ID filter */
+#define DDR_CAP_AXI_ID_FILTER_ENHANCED		BIT(2)     /* support enhanced AXI ID filter */
 
 struct fsl_ddr_devtype_data {
 	unsigned int quirks;    /* quirks needed for different DDR Perf core */
@@ -209,7 +210,15 @@ static void ddr_perf_free_counter(struct ddr_pmu *pmu, int counter)
 
 static u32 ddr_perf_read_counter(struct ddr_pmu *pmu, int counter)
 {
-	return readl_relaxed(pmu->base + COUNTER_READ + counter * 4);
+	if ((pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER) &&
+	    (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED)) {
+		if ((pmu->events[counter]->attr.config == 0x41) ||
+		    (pmu->events[counter]->attr.config == 0x42))
+			return readl_relaxed(pmu->base + COUNTER_DPCR1 + counter * 4);
+		else
+			return readl_relaxed(pmu->base + COUNTER_READ + counter * 4);
+	} else
+		return readl_relaxed(pmu->base + COUNTER_READ + counter * 4);
 }
 
 static bool ddr_perf_is_filtered(struct perf_event *event)
-- 
2.17.1


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