From: Sebastian Andrzej Siewior <sebastian@breakpoint.cc>
To: Waiman Long <longman@redhat.com>
Cc: Arnd Bergmann <arnd@arndb.de>,
Peter Zijlstra <peterz@infradead.org>,
Russell King <linux@armlinux.org.uk>,
Ingo Molnar <mingo@redhat.com>, Will Deacon <will@kernel.org>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [RFC PATCH 0/6 v2] Queued spinlocks/RW-locks for ARM
Date: Wed, 16 Oct 2019 23:35:27 +0200 [thread overview]
Message-ID: <20191016213527.fnxuxvhr6mgeeoqq@flow> (raw)
In-Reply-To: <a14cbac0-3eab-c136-ad2d-9b4d8b95a098@redhat.com>
On 2019-10-16 13:45:13 [-0400], Waiman Long wrote:
> My own testing on qspinlocks in the past, at least on x86-64, is that it
> is comparable to ticket lock with one or 2 contending tasks if not
> better. When there are 3 contending tasks, qspinlock will then be a bit
> slower than ticket lock because the overhead of using the MCS node for
> queuing is showing up. Starting with 4 and more contending tasks,
> qspinlock starts to show its strength and performing better and better
> with more contending tasks.
>
> So if the target is 4 cores or less, there isn't too much to gain from
> using qspinlock. Lock function inlining probably has a bigger
> performance benefit here than switching to qspinlock. Just food for thought.
from my initial numbers:
|IMX6q
|~~~~~
|HZ_100 | PREEMPT_NONE | PREEMPT_VOLUNTARY | PREEMPT
|Ticket | 52.103 | 52.284 | 60.5681
|Q-locks | 54.1804 | 53.267 | 56.1914
|Q-locksI| 52.2985 | 49.398 | 56.7441
|
|AM572x
|~~~~~~
|HZ_100 | PREEMPT_NONE | PREEMPT_VOLUNTARY | PREEMPT
|Ticket | 42.3819 | 42.4821 | 43.2671
|Q-locks | 40.9141 | 40.0269 | 42.65
|Q-locksI| 40.0763 | 39.9101 | 40.7811
AM572x (Cortex-A15) has two CPUs, IMX6q (Cortex-A9) has four. Here on
AM572x q-locks gain ~3.5% (PREEMPT_NONE) without inlining. IMX6q
performs worse in the same category. However it performs better on
HZ_250 which I wouldn't expect.
> Cheers,
> Longman
Sebastian
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next prev parent reply other threads:[~2019-10-16 21:35 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-13 22:13 [RFC PATCH 0/6 v2] Queued spinlocks/RW-locks for ARM Sebastian Andrzej Siewior
2019-10-13 22:13 ` [PATCH 1/6] sh: Move cmpxchg-xchg.h to asm-generic Sebastian Andrzej Siewior
2019-10-14 7:25 ` Arnd Bergmann
2019-10-15 22:31 ` [PATCH 1/6 v2] " Sebastian Andrzej Siewior
2019-10-13 22:13 ` [PATCH 2/6] ARM: cmpxchg: Define first cmpxchg() followed by xchg() Sebastian Andrzej Siewior
2019-10-13 22:13 ` [PATCH 3/6] ARM: Add xchg_{8|16}() on generic cmpxchg() on CPU_V6 Sebastian Andrzej Siewior
2019-10-13 22:13 ` [PATCH 4/6] ARM: Use qrwlock implementation Sebastian Andrzej Siewior
2019-10-13 22:13 ` [PATCH 5/6] ARM: Use qspinlock implementation Sebastian Andrzej Siewior
2019-10-13 22:13 ` [PATCH 6/6] ARM: Inline locking functions for !PREEMPTION Sebastian Andrzej Siewior
2019-10-14 7:43 ` Arnd Bergmann
2019-10-14 10:01 ` Arnd Bergmann
2019-10-15 22:30 ` Sebastian Andrzej Siewior
2019-10-15 22:37 ` Waiman Long
2019-10-15 22:47 ` Arnd Bergmann
2019-10-15 22:04 ` Sebastian Andrzej Siewior
2019-10-14 9:00 ` [RFC PATCH 0/6 v2] Queued spinlocks/RW-locks for ARM Arnd Bergmann
2019-10-16 15:57 ` Will Deacon
2019-10-16 17:45 ` Waiman Long
2019-10-16 18:33 ` Arnd Bergmann
2019-10-16 21:35 ` Sebastian Andrzej Siewior [this message]
2019-10-16 22:09 ` Sebastian Andrzej Siewior
2019-10-17 15:36 ` Waiman Long
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