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From: Will Deacon <will@kernel.org>
To: Mark Brown <broonie@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 2/3] arm64: insn: Add constants for PAC and BTI instruction decode
Date: Thu, 30 Apr 2020 17:07:30 +0100	[thread overview]
Message-ID: <20200430160729.GB25258@willie-the-truck> (raw)
In-Reply-To: <20200428172433.48830-3-broonie@kernel.org>

On Tue, Apr 28, 2020 at 06:24:32PM +0100, Mark Brown wrote:
> Add constants for decoding the various PAC and BTI instructions defined
> in the HINT space. Since we are now decoding both the op2 and CRm fields
> rename the enum as well; this is compatible with what the existing users
> are doing.
> 
> Signed-off-by: Mark Brown <broonie@kernel.org>
> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
> ---
>  arch/arm64/include/asm/insn.h | 22 ++++++++++++++++++++--
>  arch/arm64/kernel/insn.c      |  2 +-
>  2 files changed, 21 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h
> index bb313dde58a4..e5a87f98a548 100644
> --- a/arch/arm64/include/asm/insn.h
> +++ b/arch/arm64/include/asm/insn.h
> @@ -39,13 +39,31 @@ enum aarch64_insn_encoding_class {
>  					 * system instructions */
>  };
>  
> -enum aarch64_insn_hint_op {
> +enum aarch64_insn_hint_cr_op {
>  	AARCH64_INSN_HINT_NOP	= 0x0 << 5,
>  	AARCH64_INSN_HINT_YIELD	= 0x1 << 5,
>  	AARCH64_INSN_HINT_WFE	= 0x2 << 5,
>  	AARCH64_INSN_HINT_WFI	= 0x3 << 5,
>  	AARCH64_INSN_HINT_SEV	= 0x4 << 5,
>  	AARCH64_INSN_HINT_SEVL	= 0x5 << 5,
> +
> +	AARCH64_INSN_HINT_PACIA_1716 = 0x08 << 5,
> +	AARCH64_INSN_HINT_PACIB_1716 = 0x0A << 5,
> +	AARCH64_INSN_HINT_AUTIA_1716 = 0x0B << 5,
> +	AARCH64_INSN_HINT_AUTIB_1716 = 0x0C << 5,

These still look wrong to me.

> +	AARCH64_INSN_HINT_PACIAZ     = 0x18 << 5,
> +	AARCH64_INSN_HINT_PACIASP    = 0x19 << 5,
> +	AARCH64_INSN_HINT_PACIBZ     = 0x1A << 5,
> +	AARCH64_INSN_HINT_PACIBSP    = 0x1B << 5,
> +	AARCH64_INSN_HINT_AUTIAZ     = 0x1C << 5,
> +	AARCH64_INSN_HINT_AUTIASP    = 0x1D << 5,

This one is typo'd in the Arm ARM as AUTHASP. Seems nobody can get this
stuff right!

> +	AARCH64_INSN_HINT_AUTIBZ     = 0x1E << 5,
> +	AARCH64_INSN_HINT_AUTIBSP    = 0x1F << 5,
> +
> +	AARCH64_INSN_HINT_BTI   = 0x20 << 5,
> +	AARCH64_INSN_HINT_BTIC  = 0x22 << 5,
> +	AARCH64_INSN_HINT_BTIJ  = 0x24 << 5,
> +	AARCH64_INSN_HINT_BTIJC = 0x2C << 5,

This looks wrong as well.

Will

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  reply	other threads:[~2020-04-30 16:07 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-28 17:24 [PATCH v2 0/3] arm64: Make NOP handling a whitelist Mark Brown
2020-04-28 17:24 ` [PATCH v2 1/3] arm64: insn: Don't assume unrecognized HINTs are NOPs Mark Brown
2020-04-30 16:08   ` Will Deacon
2020-04-28 17:24 ` [PATCH v2 2/3] arm64: insn: Add constants for PAC and BTI instruction decode Mark Brown
2020-04-30 16:07   ` Will Deacon [this message]
2020-04-30 16:45     ` Mark Brown
2020-04-28 17:24 ` [PATCH v2 3/3] arm64: insn: Report PAC and BTI instructions as NOPs Mark Brown
2020-04-30 16:09   ` Will Deacon
2020-04-30 17:16     ` Mark Brown
2020-04-30 17:20       ` Will Deacon
2020-04-30 17:36         ` Mark Brown

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