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From: Will Deacon <will@kernel.org>
To: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] arm64: perf: Expose some new events via sysfs
Date: Fri, 1 May 2020 18:12:37 +0100	[thread overview]
Message-ID: <20200501171237.GA19048@willie-the-truck> (raw)
In-Reply-To: <1587450713-18048-1-git-send-email-zhangshaokun@hisilicon.com>

On Tue, Apr 21, 2020 at 02:31:53PM +0800, Shaokun Zhang wrote:
> Some new PMU events can been detected by PMCEID1_EL0, but it can't
> be listed, Let's expose these through sysfs.
> 
> Cc: Will Deacon <will@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
> ---
>  arch/arm64/include/asm/perf_event.h | 19 +++++++++++++++++++
>  arch/arm64/kernel/perf_event.c      | 19 +++++++++++++++++++
>  2 files changed, 38 insertions(+)
> 
> diff --git a/arch/arm64/include/asm/perf_event.h b/arch/arm64/include/asm/perf_event.h
> index e7765b62c712..f1b93d7c4260 100644
> --- a/arch/arm64/include/asm/perf_event.h
> +++ b/arch/arm64/include/asm/perf_event.h
> @@ -72,12 +72,31 @@
>  #define ARMV8_PMUV3_PERFCTR_LL_CACHE_RD				0x36
>  #define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD			0x37
>  #define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD			0x38
> +#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD			0x39
> +#define ARMV8_PMUV3_PERFCTR_OP_RETIRED				0x3A
> +#define ARMV8_PMUV3_PERFCTR_OP_SPEC				0x3B
> +#define ARMV8_PMUV3_PERFCTR_STALL				0x3C
> +#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND			0x3D
> +#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND			0x3E
> +#define ARMV8_PMUV3_PERFCTR_STALL_SLOT				0x3F

Hmm, looks like the presence of this event implies the presence of the
PMMIR_EL1 register. Should we be exposing the "SLOTS" field from that in
sysfs? (obviously as a separate patch)

>  
>  /* Statistical profiling extension microarchitectural events */
>  #define	ARMV8_SPE_PERFCTR_SAMPLE_POP				0x4000
>  #define	ARMV8_SPE_PERFCTR_SAMPLE_FEED				0x4001
>  #define	ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE			0x4002
>  #define	ARMV8_SPE_PERFCTR_SAMPLE_COLLISION			0x4003
> +#define	ARMV8_SPE_PERFCTR_CNT_CYCLES				0x4004
> +#define	ARMV8_SPE_PERFCTR_STALL_BACKEND_MEM			0x4005
> +#define	ARMV8_SPE_PERFCTR_L1I_CACHE_LMISS			0x4006
> +#define	ARMV8_SPE_PERFCTR_L2D_CACHE_LMISS_RD			0x4009
> +#define	ARMV8_SPE_PERFCTR_L2I_CACHE_LMISS			0x400A
> +#define	ARMV8_SPE_PERFCTR_L3D_CACHE_LMISS_RD			0x400B
> +#define	ARMV8_SPE_PERFCTR_LDST_ALIGN_LAT			0x4020
> +#define	ARMV8_SPE_PERFCTR_LD_ALIGN_LAT				0x4021
> +#define	ARMV8_SPE_PERFCTR_ST_ALIGN_LAT				0x4022
> +#define	ARMV8_SPE_PERFCTR_MEM_ACCESS_CHECKED			0x4024
> +#define	ARMV8_SPE_PERFCTR_MEM_ACCESS_CHECKED_RD			0x4025
> +#define	ARMV8_SPE_PERFCTR_MEM_ACCESS_CHECKED_WR			0x4026

I think the naming is off here, as these don't seem to have anything to do
with SPE afaict.

Will

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  reply	other threads:[~2020-05-01 17:12 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-21  6:31 [PATCH] arm64: perf: Expose some new events via sysfs Shaokun Zhang
2020-05-01 17:12 ` Will Deacon [this message]
2020-05-04  1:31   ` Shaokun Zhang
2020-05-04  3:46   ` Shaokun Zhang
2020-05-04  7:06     ` Will Deacon
2020-05-05  2:21       ` Shaokun Zhang

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