From: Alexandru Elisei <alexandru.elisei@arm.com>
To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Cc: mark.rutland@arm.com, Julien Thierry <julien.thierry@arm.com>,
Peter Zijlstra <peterz@infradead.org>,
maz@kernel.org, Jiri Olsa <jolsa@redhat.com>,
Will Deacon <will.deacon@arm.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Ingo Molnar <mingo@redhat.com>,
catalin.marinas@arm.com, Namhyung Kim <namhyung@kernel.org>,
will@kernel.org, Julien Thierry <julien.thierry.kdev@gmail.com>
Subject: [PATCH v5 1/7] arm64: perf: Add missing ISB in armv8pmu_enable_event()
Date: Wed, 17 Jun 2020 12:38:45 +0100 [thread overview]
Message-ID: <20200617113851.607706-2-alexandru.elisei@arm.com> (raw)
In-Reply-To: <20200617113851.607706-1-alexandru.elisei@arm.com>
Writes to the PMXEVTYPER_EL0 register are not self-synchronising. In
armv8pmu_enable_event(), the PE can reorder configuring the event type
after we have enabled the counter and the interrupt. This can lead to an
interrupt being asserted because the of the previous event type that we
were counting, not the one that we've just enabled.
The same rationale applies to writes to the PMINTENSET_EL1 register. The PE
can reorder enabling the interrupt at any point in the future after we have
enabled the event.
Prevent both situations from happening by adding an ISB just before we
enable the event counter.
Cc: Julien Thierry <julien.thierry.kdev@gmail.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Fixes: 030896885ade ("arm64: Performance counters support")
Reported-by: Julien Thierry <julien.thierry@arm.com>
Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
---
arch/arm64/kernel/perf_event.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 4d7879484cec..ee180b2a5b39 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -605,6 +605,7 @@ static void armv8pmu_enable_event(struct perf_event *event)
* Enable interrupt for this counter
*/
armv8pmu_enable_event_irq(event);
+ isb();
/*
* Enable counter
--
2.27.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-06-17 11:41 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-17 11:38 [PATCH v5 0/7] arm_pmu: Use NMI for perf interrupt Alexandru Elisei
2020-06-17 11:38 ` Alexandru Elisei [this message]
2020-06-17 20:01 ` [PATCH v5 1/7] arm64: perf: Add missing ISB in armv8pmu_enable_event() Stephen Boyd
2020-06-18 10:50 ` Alexandru Elisei
2020-06-17 11:38 ` [PATCH v5 2/7] arm64: perf: Avoid PMXEV* indirection Alexandru Elisei
2020-06-17 20:11 ` Stephen Boyd
2020-06-18 10:51 ` Alexandru Elisei
2020-06-19 8:26 ` Stephen Boyd
2020-06-17 11:38 ` [PATCH v5 3/7] arm64: perf: Remove PMU locking Alexandru Elisei
2020-06-17 20:17 ` Stephen Boyd
2020-06-18 10:51 ` Alexandru Elisei
2020-06-19 8:29 ` Stephen Boyd
2020-07-03 13:45 ` Will Deacon
2020-06-17 11:38 ` [PATCH v5 4/7] arm64: perf: Defer irq_work to IPI_IRQ_WORK Alexandru Elisei
2020-06-17 11:38 ` [PATCH v5 5/7] arm64: kvm: pmu: Make overflow handler NMI safe Alexandru Elisei
2020-06-17 11:38 ` [PATCH v5 6/7] arm_pmu: Introduce pmu_irq_ops Alexandru Elisei
2020-06-17 20:23 ` Stephen Boyd
2020-06-18 10:51 ` Alexandru Elisei
2020-06-19 8:33 ` Stephen Boyd
2020-06-17 11:38 ` [PATCH v5 7/7] arm_pmu: arm64: Use NMIs for PMU Alexandru Elisei
2020-06-25 15:11 ` [PATCH v5 0/7] arm_pmu: Use NMI for perf interrupt Alexandru Elisei
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200617113851.607706-2-alexandru.elisei@arm.com \
--to=alexandru.elisei@arm.com \
--cc=acme@kernel.org \
--cc=alexander.shishkin@linux.intel.com \
--cc=catalin.marinas@arm.com \
--cc=jolsa@redhat.com \
--cc=julien.thierry.kdev@gmail.com \
--cc=julien.thierry@arm.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=maz@kernel.org \
--cc=mingo@redhat.com \
--cc=namhyung@kernel.org \
--cc=peterz@infradead.org \
--cc=will.deacon@arm.com \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox