* [v3, 1/4] dt-binding: reset-controller: ti: add reset-duration-us property
2020-08-17 2:48 [v3,0/6] introduce TI reset controller for MT8192 SoC Crystal Guo
@ 2020-08-17 2:48 ` Crystal Guo
2020-08-17 2:48 ` [v3, 2/4] dt-binding: reset-controller: ti: add 'mediatek, infra-reset' to compatible Crystal Guo
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Crystal Guo @ 2020-08-17 2:48 UTC (permalink / raw)
To: p.zabel, robh+dt, matthias.bgg
Cc: devicetree, yong.liang, stanley.chu, srv_heupstream, seiya.wang,
linux-kernel, afd, fan.chen, Crystal Guo, linux-mediatek,
yingjoe.chen, linux-arm-kernel
introduce 'reset' method to allow device do serialized assert and
deassert operations in a single step, which needs a minimum delay
to be waited between assert and deassert.
Signed-off-by: Crystal Guo <crystal.guo@mediatek.com>
---
Documentation/devicetree/bindings/reset/ti-syscon-reset.txt | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
index 86945502ccb5..ab041032339b 100644
--- a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
+++ b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
@@ -59,6 +59,11 @@ Required properties:
Please also refer to Documentation/devicetree/bindings/reset/reset.txt for
common reset controller usage by consumers.
+Optional properties:
+- reset-duration-us: When do serialized assert and deassert operations, minimum delay in microseconds
+is needed to be waited between an assert and a deassert to reset the device. This value can be 0, 0 means
+that such a delay is not needed.
+
Example:
--------
The following example demonstrates a syscon node, the reset controller node
--
2.18.0
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^ permalink raw reply related [flat|nested] 5+ messages in thread* [v3, 2/4] dt-binding: reset-controller: ti: add 'mediatek, infra-reset' to compatible
2020-08-17 2:48 [v3,0/6] introduce TI reset controller for MT8192 SoC Crystal Guo
2020-08-17 2:48 ` [v3, 1/4] dt-binding: reset-controller: ti: add reset-duration-us property Crystal Guo
@ 2020-08-17 2:48 ` Crystal Guo
2020-08-17 2:48 ` [v3,3/4] reset-controller: ti: introduce a new reset handler Crystal Guo
2020-08-17 2:48 ` [v4,4/4] arm64: dts: mt8192: add infracfg_rst node Crystal Guo
3 siblings, 0 replies; 5+ messages in thread
From: Crystal Guo @ 2020-08-17 2:48 UTC (permalink / raw)
To: p.zabel, robh+dt, matthias.bgg
Cc: devicetree, yong.liang, stanley.chu, srv_heupstream, seiya.wang,
linux-kernel, afd, fan.chen, Crystal Guo, linux-mediatek,
yingjoe.chen, linux-arm-kernel
The TI syscon reset controller provides a common reset management,
and is suitable for MTK SoCs. Add compatible 'mediatek,infra-reset',
which denotes to use ti reset-controller driver directly.
Signed-off-by: Crystal Guo <crystal.guo@mediatek.com>
---
Documentation/devicetree/bindings/reset/ti-syscon-reset.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
index ab041032339b..5a0e9365b51b 100644
--- a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
+++ b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
@@ -25,6 +25,7 @@ Required properties:
"ti,k2l-pscrst"
"ti,k2hk-pscrst"
"ti,syscon-reset"
+ "mediatek,infra-reset", "ti,syscon-reset"
- #reset-cells : Should be 1. Please see the reset consumer node below
for usage details
- ti,reset-bits : Contains the reset control register information
--
2.18.0
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* [v3,3/4] reset-controller: ti: introduce a new reset handler
2020-08-17 2:48 [v3,0/6] introduce TI reset controller for MT8192 SoC Crystal Guo
2020-08-17 2:48 ` [v3, 1/4] dt-binding: reset-controller: ti: add reset-duration-us property Crystal Guo
2020-08-17 2:48 ` [v3, 2/4] dt-binding: reset-controller: ti: add 'mediatek, infra-reset' to compatible Crystal Guo
@ 2020-08-17 2:48 ` Crystal Guo
2020-08-17 2:48 ` [v4,4/4] arm64: dts: mt8192: add infracfg_rst node Crystal Guo
3 siblings, 0 replies; 5+ messages in thread
From: Crystal Guo @ 2020-08-17 2:48 UTC (permalink / raw)
To: p.zabel, robh+dt, matthias.bgg
Cc: devicetree, yong.liang, stanley.chu, srv_heupstream, seiya.wang,
linux-kernel, afd, fan.chen, Crystal Guo, linux-mediatek,
yingjoe.chen, linux-arm-kernel
Introduce ti_syscon_reset() to integrate assert and deassert together.
If some modules need do serialized assert and deassert operations
to reset itself, reset_control_reset can be called for convenience.
Such as reset-qcom-aoss.c, it integrates assert and deassert together
by 'reset' method. MTK Socs also need this method to perform reset.
Signed-off-by: Crystal Guo <crystal.guo@mediatek.com>
---
drivers/reset/reset-ti-syscon.c | 26 ++++++++++++++++++++++++--
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/reset/reset-ti-syscon.c b/drivers/reset/reset-ti-syscon.c
index a2635c21db7f..08289342f9af 100644
--- a/drivers/reset/reset-ti-syscon.c
+++ b/drivers/reset/reset-ti-syscon.c
@@ -15,6 +15,7 @@
* GNU General Public License for more details.
*/
+#include <linux/delay.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
@@ -56,6 +57,7 @@ struct ti_syscon_reset_data {
struct regmap *regmap;
struct ti_syscon_reset_control *controls;
unsigned int nr_controls;
+ unsigned int reset_duration_us;
};
#define to_ti_syscon_reset_data(rcdev) \
@@ -89,7 +91,7 @@ static int ti_syscon_reset_assert(struct reset_controller_dev *rcdev,
mask = BIT(control->assert_bit);
value = (control->flags & ASSERT_SET) ? mask : 0x0;
- return regmap_update_bits(data->regmap, control->assert_offset, mask, value);
+ return regmap_write_bits(data->regmap, control->assert_offset, mask, value);
}
/**
@@ -120,7 +122,7 @@ static int ti_syscon_reset_deassert(struct reset_controller_dev *rcdev,
mask = BIT(control->deassert_bit);
value = (control->flags & DEASSERT_SET) ? mask : 0x0;
- return regmap_update_bits(data->regmap, control->deassert_offset, mask, value);
+ return regmap_write_bits(data->regmap, control->deassert_offset, mask, value);
}
/**
@@ -158,9 +160,26 @@ static int ti_syscon_reset_status(struct reset_controller_dev *rcdev,
!(control->flags & STATUS_SET);
}
+static int ti_syscon_reset(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct ti_syscon_reset_data *data = to_ti_syscon_reset_data(rcdev);
+ int ret;
+
+ ret = ti_syscon_reset_assert(rcdev, id);
+ if (ret)
+ return ret;
+
+ if (data->reset_duration_us)
+ usleep_range(data->reset_duration_us, data->reset_duration_us * 2);
+
+ return ti_syscon_reset_deassert(rcdev, id);
+}
+
static const struct reset_control_ops ti_syscon_reset_ops = {
.assert = ti_syscon_reset_assert,
.deassert = ti_syscon_reset_deassert,
+ .reset = ti_syscon_reset,
.status = ti_syscon_reset_status,
};
@@ -204,6 +223,9 @@ static int ti_syscon_reset_probe(struct platform_device *pdev)
controls[i].flags = be32_to_cpup(list++);
}
+ of_property_read_u32(pdev->dev.of_node, "reset-duration-us",
+ &data->reset_duration_us);
+
data->rcdev.ops = &ti_syscon_reset_ops;
data->rcdev.owner = THIS_MODULE;
data->rcdev.of_node = np;
--
2.18.0
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^ permalink raw reply related [flat|nested] 5+ messages in thread* [v4,4/4] arm64: dts: mt8192: add infracfg_rst node
2020-08-17 2:48 [v3,0/6] introduce TI reset controller for MT8192 SoC Crystal Guo
` (2 preceding siblings ...)
2020-08-17 2:48 ` [v3,3/4] reset-controller: ti: introduce a new reset handler Crystal Guo
@ 2020-08-17 2:48 ` Crystal Guo
3 siblings, 0 replies; 5+ messages in thread
From: Crystal Guo @ 2020-08-17 2:48 UTC (permalink / raw)
To: p.zabel, robh+dt, matthias.bgg
Cc: devicetree, yong.liang, stanley.chu, srv_heupstream, seiya.wang,
linux-kernel, afd, fan.chen, Crystal Guo, linux-mediatek,
yingjoe.chen, linux-arm-kernel
add infracfg_rst node which is for MT8192 platform
Signed-off-by: Crystal Guo <crystal.guo@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 931e1ca17220..a0cb9904706b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
#include <dt-bindings/power/mt8192-power.h>
+#include <dt-bindings/reset/ti-syscon.h>
/ {
compatible = "mediatek,mt8192";
@@ -219,9 +220,17 @@
};
infracfg: infracfg@10001000 {
- compatible = "mediatek,mt8192-infracfg", "syscon";
+ compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
+
+ infracfg_rst: reset-controller {
+ compatible = "mediatek,infra-reset", "ti,syscon-reset";
+ #reset-cells = <1>;
+ ti,reset-bits = <
+ 0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: pcie */
+ >;
+ };
};
pericfg: pericfg@10003000 {
--
2.18.0
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^ permalink raw reply related [flat|nested] 5+ messages in thread