From: Suman Anna <s-anna@ti.com>
To: Nishanth Menon <nm@ti.com>, Tero Kristo <t-kristo@ti.com>
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH 4/7] arm64: dts: ti: k3-j721e-main: Add C71x DSP node
Date: Wed, 19 Aug 2020 20:03:28 -0500 [thread overview]
Message-ID: <20200820010331.2911-5-s-anna@ti.com> (raw)
In-Reply-To: <20200820010331.2911-1-s-anna@ti.com>
The J721E SoCs have a single TMS320C71x DSP Subsystem in the MAIN
voltage domain containing the next-generation C711 CPU core. The
subsystem has 32 KB of L1D configurable SRAM/Cache and 512 KB of
L2 configurable SRAM/Cache. This subsystem has a CMMU but is not
used currently. The inter-processor communication between the main
A72 cores and the C711 processor is achieved through shared memory
and a Mailbox. Add the DT node for this DSP processor sub-system
in the common k3-j721e-main.dtsi file.
The following firmware name is used by default for the C71x core,
and can be overridden in a board dts file if desired:
C71x_0 DSP: j7-c71_0-fw
Signed-off-by: Suman Anna <s-anna@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 46cde2677e17..4ba5d356655a 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -1352,4 +1352,16 @@ c66_1: dsp@4d81800000 {
resets = <&k3_reset 143 1>;
firmware-name = "j7-c66_1-fw";
};
+
+ c71_0: dsp@64800000 {
+ compatible = "ti,j721e-c71-dsp";
+ reg = <0x00 0x64800000 0x00 0x00080000>,
+ <0x00 0x64e00000 0x00 0x0000c000>;
+ reg-names = "l2sram", "l1dram";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <15>;
+ ti,sci-proc-ids = <0x30 0xff>;
+ resets = <&k3_reset 15 1>;
+ firmware-name = "j7-c71_0-fw";
+ };
};
--
2.28.0
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next prev parent reply other threads:[~2020-08-20 1:05 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-20 1:03 [PATCH 0/7] Add C66x & C71x DSP nodes on J721E SoCs Suman Anna
2020-08-20 1:03 ` [PATCH 1/7] arm64: dts: ti: k3-j721e-main: Add C66x DSP nodes Suman Anna
2020-08-20 1:03 ` [PATCH 2/7] arm64: dts: ti: k3-j721e-common-proc-board: Add mailboxes to C66x DSPs Suman Anna
2020-08-20 11:42 ` Nishanth Menon
2020-08-20 13:25 ` Suman Anna
2020-08-20 19:03 ` Nishanth Menon
2020-08-24 22:00 ` Suman Anna
2020-08-25 10:42 ` Nishanth Menon
2020-08-25 17:25 ` Suman Anna
2020-08-20 1:03 ` [PATCH 3/7] arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for C66 DSPs Suman Anna
2020-08-20 1:03 ` Suman Anna [this message]
2020-08-20 1:03 ` [PATCH 5/7] arm64: dts: ti: k3-j721e-common-proc-board: Add mailboxes to C71x DSP Suman Anna
2020-08-20 1:03 ` [PATCH 6/7] arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for " Suman Anna
2020-08-20 1:03 ` [PATCH 7/7] arm64: dts: ti: k3-j721e-som-p0: Reserve memory for IPC between RTOS cores Suman Anna
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