From: Mark Rutland <mark.rutland@arm.com>
To: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2] arm64: dbm: Invalidate local TLB when setting TCR_EL1.HD
Date: Thu, 1 Oct 2020 12:22:05 +0100 [thread overview]
Message-ID: <20201001112205.GA86680@C02TD0UTHF1T.local> (raw)
In-Reply-To: <20201001110405.18617-1-will@kernel.org>
On Thu, Oct 01, 2020 at 12:04:05PM +0100, Will Deacon wrote:
> TCR_EL1.HD is permitted to be cached in a TLB, so invalidate the local
> TLB after setting the bit when detected support for the feature. Although
> this isn't strictly necessary, since we can happily operate with the bit
> effectively clear, the current code uses an ISB in a half-hearted attempt
> to make the change effective, so let's just fix that up.
>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Signed-off-by: Will Deacon <will@kernel.org>
Reviewed-by: Mark Rutland <mark.rutladn@arm.com>
Mark.
> ---
>
> v1 -> v2: Retain isb() prior to TLB invalidation.
>
> arch/arm64/kernel/cpufeature.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 6424584be01e..a474a4f39c95 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -1443,6 +1443,7 @@ static inline void __cpu_enable_hw_dbm(void)
>
> write_sysreg(tcr, tcr_el1);
> isb();
> + local_flush_tlb_all();
> }
>
> static bool cpu_has_broken_dbm(void)
> --
> 2.28.0.709.gb0816b6eb0-goog
>
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prev parent reply other threads:[~2020-10-01 11:23 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-01 11:04 [PATCH v2] arm64: dbm: Invalidate local TLB when setting TCR_EL1.HD Will Deacon
2020-10-01 11:12 ` Catalin Marinas
2020-10-01 11:22 ` Mark Rutland [this message]
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