From: Will Deacon <will@kernel.org>
To: Arnd Bergmann <arnd@arndb.de>
Cc: Marc Zyngier <maz@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Yassine Oudjana <y.oudjana@protonmail.com>,
Ard Biesheuvel <ardb@kernel.org>,
Android Kernel Team <kernel-team@android.com>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
Mark Rutland <mark.rutland@arm.com>,
Vincent Whitchurch <vincent.whitchurch@axis.com>,
linux-arm-msm <linux-arm-msm@vger.kernel.org>
Subject: Re: [PATCH] arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES)
Date: Tue, 6 Jul 2021 17:20:08 +0100 [thread overview]
Message-ID: <20210706162007.GA20541@willie-the-truck> (raw)
In-Reply-To: <CAK8P3a2xWTvj6HjsC6gH44Ad13adKjK0wR7UxFFQ1i=XYixvQA@mail.gmail.com>
On Tue, Jul 06, 2021 at 04:30:34PM +0200, Arnd Bergmann wrote:
> On Tue, Jul 6, 2021 at 3:44 PM Marc Zyngier <maz@kernel.org> wrote:
> >
> > On 2021-07-06 14:33, Will Deacon wrote:
> > > On Tue, Jul 06, 2021 at 02:29:07PM +0100, Robin Murphy wrote:
> > >
> > > I can't find much information about the original Kryo core at all...
> >
> > I have similar issues with my QDF2400. The UART, RTC and DMA controllers
> > are all screaming at me. I'm confident that the UART doesn't do any
> > DMA (it is handled by the SBSA driver), but the DMA controllers are
> > probably doing what it says on the tin.
>
> But that's a server chip, surely the DMA controller is fully cache coherent
> as required by SBSA? (please?)
>
> Maybe just a misannotation on the device node?
>
> > Do we know whether Falkor and Kryo share any part of their design?
>
> I'm fairly sure the Snapdragon 821 / msm8996 is not cache coherent.
>
> I can only speculate on how much got reused between the two, but
> as Falkor was released only after they had already given up on
> the full-custom Kryo core, it's plausible that it incorporates bits from
> that one. In particular the cache controller is probably easy to reuse
> even if the rest of it was a new design.
I think the million dollar question is whether the 128-byte cache-lines
live in a cache above the PoC or not. If it's just a system level cache
through which all DMA is "coherent", then it doesn't matter.
Digging around on the web, it's unclear whether msm8996 has an L3 or not.
Will
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prev parent reply other threads:[~2021-07-06 16:22 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20210602132541eucas1p17127696041c26c00d1d2f50bef9cfaf0@eucas1p1.samsung.com>
2021-05-27 12:43 ` [PATCH] arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES) Will Deacon
2021-05-27 13:11 ` Catalin Marinas
2021-05-27 13:19 ` Mark Rutland
2021-05-28 9:35 ` Arnd Bergmann
2021-06-01 10:14 ` Catalin Marinas
2021-05-31 5:38 ` Ard Biesheuvel
2021-06-01 18:21 ` Will Deacon
2021-06-02 13:25 ` Marek Szyprowski
2021-06-02 13:51 ` Mark Rutland
2021-06-02 14:09 ` Marek Szyprowski
2021-06-02 14:14 ` Arnd Bergmann
2021-06-02 14:28 ` Marek Szyprowski
2021-06-02 14:52 ` Arnd Bergmann
2021-06-07 12:17 ` Arnd Bergmann
2021-06-04 10:01 ` Mark Rutland
2021-06-07 9:58 ` Marek Szyprowski
2021-06-07 12:01 ` Mark Rutland
2021-06-07 13:08 ` Mark Rutland
2021-06-07 13:39 ` Will Deacon
2021-06-07 13:56 ` Mark Rutland
2021-06-07 13:57 ` Arnd Bergmann
2021-06-07 15:17 ` Maxime Ripard
2021-06-07 15:50 ` Arnd Bergmann
2021-06-08 8:57 ` Mark Rutland
2021-06-07 15:32 ` Mark Rutland
2021-06-02 14:11 ` Arnd Bergmann
2021-06-02 14:15 ` Marek Szyprowski
[not found] ` <uHgsRacR8hJ7nW-I-pIcehzg-lNIn7NJvaL7bP9tfAftFsBjsgaY2qTjG9zyBgxHkjNL1WPNrD7YVv2JVD2_Wy-a5VTbcq-1xEi8ZnwrXBo=@protonmail.com>
2021-07-06 10:26 ` Catalin Marinas
2021-07-06 13:29 ` Robin Murphy
2021-07-06 13:33 ` Will Deacon
2021-07-06 13:44 ` Marc Zyngier
2021-07-06 14:21 ` Robin Murphy
2021-07-06 14:30 ` Arnd Bergmann
2021-07-06 14:46 ` Marc Zyngier
2021-07-06 15:43 ` Arnd Bergmann
2021-07-06 17:15 ` Yassine Oudjana
2021-07-06 20:33 ` Arnd Bergmann
2021-07-06 22:27 ` Bjorn Andersson
2021-07-07 9:27 ` Will Deacon
2021-07-07 8:24 ` Yassine Oudjana
2021-07-07 9:29 ` Arnd Bergmann
2021-07-07 14:41 ` Jeffrey Hugo
2021-07-08 20:59 ` Jeffrey Hugo
2021-07-09 8:48 ` Will Deacon
2021-07-09 17:10 ` Catalin Marinas
2021-07-06 16:20 ` Will Deacon [this message]
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