From: Catalin Marinas <catalin.marinas@arm.com>
To: Mark Rutland <mark.rutland@arm.com>
Cc: Peter Collingbourne <pcc@google.com>,
Vincenzo Frascino <vincenzo.frascino@arm.com>,
Will Deacon <will@kernel.org>,
Andrey Konovalov <andreyknvl@gmail.com>,
Evgenii Stepanov <eugenis@google.com>,
Szabolcs Nagy <szabolcs.nagy@arm.com>,
Tejas Belagod <Tejas.Belagod@arm.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v4] arm64: mte: optimize GCR_EL1 modification on kernel entry/exit
Date: Wed, 28 Jul 2021 18:18:12 +0100 [thread overview]
Message-ID: <20210728171811.GD7408@arm.com> (raw)
In-Reply-To: <20210714140442.GA28555@C02TD0UTHF1T.local>
On Wed, Jul 14, 2021 at 03:04:42PM +0100, Mark Rutland wrote:
> On Tue, Jul 13, 2021 at 06:36:38PM -0700, Peter Collingbourne wrote:
> > diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
> > index ce59280355c5..2d6dc62d929a 100644
> > --- a/arch/arm64/kernel/entry.S
> > +++ b/arch/arm64/kernel/entry.S
> > @@ -175,15 +175,11 @@ alternative_else_nop_endif
> > #endif
> > .endm
> >
> > - .macro mte_set_gcr, tmp, tmp2
> > + .macro mte_set_gcr, mte_ctrl, tmp
> > #ifdef CONFIG_ARM64_MTE
> > - /*
> > - * Calculate and set the exclude mask preserving
> > - * the RRND (bit[16]) setting.
> > - */
> > - mrs_s \tmp2, SYS_GCR_EL1
> > - bfxil \tmp2, \tmp, #MTE_CTRL_GCR_USER_EXCL_SHIFT, #16
> > - msr_s SYS_GCR_EL1, \tmp2
> > + ubfx \tmp, \mte_ctrl, #MTE_CTRL_GCR_USER_EXCL_SHIFT, #16
> > + orr \tmp, \tmp, #SYS_GCR_EL1_RRND
> > + msr_s SYS_GCR_EL1, \tmp
> > #endif
> > .endm
>
> Since the mte_ctrl value only has the Exclude bits set, we can make this
> even simpler:
>
> orr \tmp, \mte_ctrl, #SYS_GCR_EL1_RRND
> msr_s SYS_GCR_EL1, \tmp
I don't think we can guarantee it following this patch (some other bits
added to mte_ctrl):
https://lore.kernel.org/r/20210727205300.2554659-3-pcc@google.com
--
Catalin
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next prev parent reply other threads:[~2021-07-28 17:20 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-14 1:36 [PATCH v4] arm64: mte: optimize GCR_EL1 modification on kernel entry/exit Peter Collingbourne
2021-07-14 14:04 ` Mark Rutland
2021-07-28 17:18 ` Catalin Marinas [this message]
2021-07-28 17:46 ` Catalin Marinas
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