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From: jason-jh.lin <jason-jh.lin@mediatek.com>
To: Rob Herring <robh+dt@kernel.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Chun-Kuang Hu <chunkuang.hu@kernel.org>, <fshao@chromium.org>
Cc: Philipp Zabel <p.zabel@pengutronix.de>,
	Enric Balletbo i Serra <enric.balletbo@collabora.com>,
	David Airlie <airlied@linux.ie>,
	"Daniel Vetter" <daniel@ffwll.ch>,
	Fabien Parent <fparent@baylibre.com>, <hsinyi@chromium.org>,
	"jason-jh . lin" <jason-jh.lin@mediatek.com>,
	Yongqiang Niu <yongqiang.niu@mediatek.com>,
	Jitao shi <jitao.shi@mediatek.com>, <nancy.lin@mediatek.com>,
	<singo.chang@mediatek.com>, <devicetree@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-mediatek@lists.infradead.org>,
	 <linux-kernel@vger.kernel.org>,
	<dri-devel@lists.freedesktop.org>
Subject: [PATCH v8 04/13] dt-bindings: mediatek: display: add mt8195 SoC binding
Date: Thu, 19 Aug 2021 10:23:18 +0800	[thread overview]
Message-ID: <20210819022327.13040-5-jason-jh.lin@mediatek.com> (raw)
In-Reply-To: <20210819022327.13040-1-jason-jh.lin@mediatek.com>

1. Add mt8195 SoC binding to AAL, CCORR, COLOR, DITHER, GAMMA, MERGE,
   MUTEX, OVL and RDMA yaml schema.

2. Add MERGE additional property description for mt8195
- async clock
- fifo setting enable
- reset controller

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 .../display/mediatek/mediatek,aal.yaml        |  1 +
 .../display/mediatek/mediatek,ccorr.yaml      |  5 +++
 .../display/mediatek/mediatek,color.yaml      |  1 +
 .../display/mediatek/mediatek,dither.yaml     |  5 +++
 .../display/mediatek/mediatek,gamma.yaml      |  5 +++
 .../display/mediatek/mediatek,merge.yaml      | 40 +++++++++++++++++++
 .../display/mediatek/mediatek,mutex.yaml      |  2 +
 .../display/mediatek/mediatek,ovl.yaml        |  5 +++
 .../display/mediatek/mediatek,rdma.yaml       |  2 +
 9 files changed, 66 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
index 7be772d77e36..e1820238db43 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
@@ -25,6 +25,7 @@ properties:
           - enum:
               - mediatek,mt2712-disp-aal
               - mediatek,mt8183-disp-aal
+              - mediatek,mt8195-disp-aal
           - enum:
               - mediatek,mt8173-disp-aal
 
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
index 5a1c27d6b3e2..4c556a2bc64a 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
@@ -21,6 +21,11 @@ properties:
     oneOf:
       - items:
           - const: mediatek,mt8183-disp-ccorr
+      - items:
+          - enum:
+              - mediatek,mt8195-disp-ccorr
+          - enum:
+              - mediatek,mt8183-disp-ccorr
 
   reg:
     maxItems: 1
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
index 9a3edf6f0b8e..a13096196a0c 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
@@ -35,6 +35,7 @@ properties:
       - items:
           - enum:
               - mediatek,mt8183-disp-color
+              - mediatek,mt8195-disp-color
           - enum:
               - mediatek,mt8173-disp-color
   reg:
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
index 20419f876410..e89fe7393291 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
@@ -22,6 +22,11 @@ properties:
     oneOf:
       - items:
           - const: mediatek,mt8183-disp-dither
+      - items:
+          - enum:
+              - mediatek,mt8195-disp-dither
+          - enum:
+              - mediatek,mt8183-disp-dither
 
   reg:
     maxItems: 1
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
index e2a1fc218e4f..dc78d6d05dee 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
@@ -23,6 +23,11 @@ properties:
           - const: mediatek,mt8173-disp-gamma
       - items:
           - const: mediatek,mt8183-disp-gamma
+      - items:
+          - enum:
+              - mediatek,mt8195-disp-gamma
+          - enum:
+              - mediatek,mt8183-disp-gamma
 
   reg:
     maxItems: 1
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
index 4cdce11d7fcd..1a27b037086b 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
@@ -21,6 +21,8 @@ properties:
     oneOf:
       - items:
           - const: mediatek,mt8173-disp-merge
+      - items:
+          - const: mediatek,mt8195-disp-merge
 
   reg:
     maxItems: 1
@@ -36,6 +38,31 @@ properties:
   clocks:
     items:
       - description: MERGE Clock
+      - description: MERGE Async Clock
+          Controlling the synchronous process between MERGE and other display function
+          blocks cross clock domain.
+
+  mediatek,merge-fifo-en:
+      description:
+	    The setting of merge fifo is mainly provided for the display latency buffer.
+        to ensure that the back-end panel display data will not be underrun,
+        a little more data is needed in the fifo. According to the merge fifo settings,
+        when the water level is detected to be insufficient, it will trigger RDMA sending
+        ultra and preulra command to SMI to speed up the data rate.
+      type: boolean
+
+  mediatek,gce-client-reg:
+    description:
+      The register of display function block to be set by gce. There are 4 arguments,
+      such as gce node, subsys id, offset and register size. The subsys id that is
+      mapping to the register of display function blocks is defined in the gce header
+      include/include/dt-bindings/gce/<chip>-gce.h of each chips.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+
+  resets:
+    description: reset controller
+      See Documentation/devicetree/bindings/reset/reset.txt for details.
 
 required:
   - compatible
@@ -55,3 +82,16 @@ examples:
         clocks = <&mmsys CLK_MM_DISP_MERGE>;
     };
 
+    merge5: disp_vpp_merge5@1c110000 {
+        compatible = "mediatek,mt8195-disp-merge";
+        reg = <0 0x1c110000 0 0x1000>;
+        interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
+        clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
+                 <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
+        clock-names = "merge","merge_async";
+        power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+        mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>;
+        mediatek,merge-fifo-en = <1>;
+        resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
+    };
+
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
index aaba6bbfb4da..0dced7a53329 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
@@ -30,6 +30,8 @@ properties:
           - const: mediatek,mt8173-disp-mutex
       - items:
           - const: mediatek,mt8183-disp-mutex
+      - items:
+          - const: mediatek,mt8195-disp-mutex
 
   reg:
     maxItems: 1
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
index 833b0ca09b21..1973eee4244f 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
@@ -31,6 +31,11 @@ properties:
               - mediatek,mt2712-disp-ovl
           - enum:
               - mediatek,mt2701-disp-ovl
+      - items:
+          - enum:
+              - mediatek,mt8195-disp-ovl
+          - enum:
+              - mediatek,mt8183-disp-ovl
 
   reg:
     maxItems: 1
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
index ce3bcca30609..847bc55252ca 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
@@ -27,6 +27,8 @@ properties:
           - const: mediatek,mt8173-disp-rdma
       - items:
           - const: mediatek,mt8183-disp-rdma
+      - items:
+          - const: mediatek,mt8195-disp-rdma
       - items:
           - enum:
               - mediatek,mt7623-disp-rdma
-- 
2.18.0
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  parent reply	other threads:[~2021-08-19  2:28 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-19  2:23 [PATCH v8 00/13] Add Mediatek Soc DRM (vdosys0) support for mt8195 jason-jh.lin
2021-08-19  2:23 ` [PATCH v8 01/13] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding jason-jh.lin
2021-08-19 15:00   ` Chun-Kuang Hu
2021-08-24 16:11     ` Jason-JH Lin
2021-08-19  2:23 ` [PATCH v8 02/13] dt-bindings: mediatek: display: split each block to individual yaml jason-jh.lin
2021-08-19  2:23 ` [PATCH v8 03/13] dt-bindings: mediatek: add mediatek, dsc.yaml for mt8195 SoC binding jason-jh.lin
2021-08-21 23:14   ` Chun-Kuang Hu
2021-08-24 17:59     ` [PATCH v8 03/13] dt-bindings: mediatek: add mediatek,dsc.yaml " Jason-JH Lin
2021-08-19  2:23 ` jason-jh.lin [this message]
2021-08-19  2:23 ` [PATCH v8 05/13] arm64: dts: mt8195: add display node for vdosys0 jason-jh.lin
2021-08-19  2:23 ` [PATCH v8 06/13] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 jason-jh.lin
2021-08-19  2:23 ` [PATCH v8 07/13] soc: mediatek: add mtk-mutex " jason-jh.lin
2021-08-19 15:12   ` Chun-Kuang Hu
2021-08-24 17:47     ` Jason-JH Lin
2021-08-19  2:23 ` [PATCH v8 08/13] drm/mediatek: remove unused define in mtk_drm_ddp_comp.c jason-jh.lin
2021-08-19 15:14   ` Chun-Kuang Hu
2021-08-19  2:23 ` [PATCH v8 09/13] drm/mediatek: rename the define of register offset jason-jh.lin
2021-08-19 15:17   ` Chun-Kuang Hu
2021-08-19  2:23 ` [PATCH v8 10/13] drm/mediatek: adjust to the alphabetic order for mediatek-drm jason-jh.lin
2021-08-19 23:14   ` Chun-Kuang Hu
2021-08-24 17:55     ` Jason-JH Lin
2021-08-19  2:23 ` [PATCH v8 11/13] drm/mediatek: add DSC support " jason-jh.lin
2021-08-19 23:16   ` Chun-Kuang Hu
2021-08-19  2:23 ` [PATCH v8 12/13] drm/mediatek: add MERGE " jason-jh.lin
2021-08-20  9:37   ` CK Hu
2021-08-20 15:43   ` Chun-Kuang Hu
2021-08-25  9:34     ` Jason-JH Lin
2021-08-19  2:23 ` [PATCH v8 13/13] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195 jason-jh.lin

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