From: Jason-JH Lin <jason-jh.lin@mediatek.com>
To: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>, <fshao@chromium.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Enric Balletbo i Serra <enric.balletbo@collabora.com>,
David Airlie <airlied@linux.ie>,
"Daniel Vetter" <daniel@ffwll.ch>,
Fabien Parent <fparent@baylibre.com>,
"Hsin-Yi Wang" <hsinyi@chromium.org>,
Yongqiang Niu <yongqiang.niu@mediatek.com>,
Jitao shi <jitao.shi@mediatek.com>,
Nancy Lin <nancy.lin@mediatek.com>, <singo.chang@mediatek.com>,
DTML <devicetree@vger.kernel.org>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@lists.infradead.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
DRI Development <dri-devel@lists.freedesktop.org>
Subject: Re: [PATCH v8 10/13] drm/mediatek: adjust to the alphabetic order for mediatek-drm
Date: Wed, 25 Aug 2021 01:55:26 +0800 [thread overview]
Message-ID: <655a9f82a9f19f506acfc05bf7bac4502e32b785.camel@mediatek.com> (raw)
In-Reply-To: <CAAOTY__k28K1LeH-ctavFi9GE9p32kL6K3sxhA0TW54XPsEB-w@mail.gmail.com>
Hi Chun-Kuang,
Thanks for the review.
On Fri, 2021-08-20 at 07:14 +0800, Chun-Kuang Hu wrote:
> Hi, Jason:
>
> jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月19日 週四 上午10:24寫道：
> >
> > Adjust to the alphabetic order for the define, function, struct
> > and array in mediatek-drm driver
> >
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 133 ++++++++++----
> > ------
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 22 ++--
> > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 76 +++++------
> > 3 files changed, 115 insertions(+), 116 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > index 93beb980414f..28bc42fd0b8a 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > @@ -20,17 +20,9 @@
> > #include "mtk_drm_ddp_comp.h"
> > #include "mtk_drm_crtc.h"
> >
> > -#define DISP_REG_OD_EN 0x0000
> > -#define DISP_REG_OD_CFG 0x0020
> > -#define DISP_REG_OD_SIZE 0x0030
> > -#define DISP_REG_DITHER_5 0x0114
> > -#define DISP_REG_DITHER_7 0x011c
> > -#define DISP_REG_DITHER_15 0x013c
> > -#define DISP_REG_DITHER_16 0x0140
> > -
> > -#define DISP_REG_UFO_START 0x0000
> >
> > #define DISP_REG_AAL_EN 0x0000
> > +#define AAL_EN BIT(0)
> > #define DISP_REG_AAL_SIZE 0x0030
> >
> > #define DISP_REG_DITHER_EN 0x0000
> > @@ -38,23 +30,29 @@
> > #define DISP_REG_DITHER_CFG 0x0020
> > #define DITHER_RELAY_MODE BIT(0)
> > #define DITHER_ENGINE_EN BIT(1)
> > -#define DISP_REG_DITHER_SIZE 0x0030
> > -
> > -#define OD_RELAYMODE BIT(0)
> > -
> > -#define UFO_BYPASS BIT(2)
> > -
> > -#define AAL_EN BIT(0)
> >
> > #define DISP_DITHERING BIT(2)
> > +#define DISP_REG_DITHER_SIZE 0x0030
> > +#define DISP_REG_DITHER_5 0x0114
> > +#define DISP_REG_DITHER_7 0x011c
> > +#define DISP_REG_DITHER_15 0x013c
> > #define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28)
> > #define DITHER_ADD_LSHIFT_R(x) (((x) & 0x7) << 20)
> > #define DITHER_NEW_BIT_MODE BIT(0)
> > +#define DISP_REG_DITHER_16 0x0140
> > #define DITHER_LSB_ERR_SHIFT_B(x) (((x) & 0x7) << 28)
> > #define DITHER_ADD_LSHIFT_B(x) (((x) & 0x7) << 20)
> > #define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12)
> > #define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4)
> >
> > +#define DISP_REG_OD_EN 0x0000
> > +#define DISP_REG_OD_CFG 0x0020
> > +#define OD_RELAYMODE BIT(0)
> > +#define DISP_REG_OD_SIZE 0x0030
> > +
> > +#define DISP_REG_UFO_START 0x0000
> > +#define UFO_BYPASS BIT(2)
> > +
> > struct mtk_ddp_comp_dev {
> > struct clk *clk;
> > void __iomem *regs;
> > @@ -106,20 +104,6 @@ void mtk_ddp_write_mask(struct cmdq_pkt
> > *cmdq_pkt, unsigned int value,
> > #endif
> > }
> >
> > -static int mtk_ddp_clk_enable(struct device *dev)
> > -{
> > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > -
> > - return clk_prepare_enable(priv->clk);
> > -}
> > -
> > -static void mtk_ddp_clk_disable(struct device *dev)
> > -{
> > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > -
> > - clk_disable_unprepare(priv->clk);
> > -}
> > -
>
> I would like to place the same group together. mtk_ddp_clk_enable()
> and mtk_ddp_clk_disable() are common function not belong to any sub
> driver. So I would like keep these function here.
>
> Regards,
> Chun-Kuang.
OK, I'll kepp them here.
Regards,
Jason-JH.Lin
>
> > void mtk_dither_set_common(void __iomem *regs, struct
> > cmdq_client_reg *cmdq_reg,
> > unsigned int bpc, unsigned int cfg,
> > unsigned int dither_en, struct cmdq_pkt
> > *cmdq_pkt)
> > @@ -146,38 +130,19 @@ void mtk_dither_set_common(void __iomem
> > *regs, struct cmdq_client_reg *cmdq_reg,
> > }
> > }
> >
> > -static void mtk_dither_set(struct device *dev, unsigned int bpc,
> > - unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
> > -{
> > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > -
> > - mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc,
> > cfg,
> > - DISP_DITHERING, cmdq_pkt);
> > -}
> > -
> > -static void mtk_od_config(struct device *dev, unsigned int w,
> > - unsigned int h, unsigned int vrefresh,
> > - unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt)
> > -{
> > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > -
> > - mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv-
> > >regs, DISP_REG_OD_SIZE);
> > - mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg,
> > priv->regs, DISP_REG_OD_CFG);
> > - mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt);
> > -}
> >
> > -static void mtk_od_start(struct device *dev)
> > +static int mtk_ddp_clk_enable(struct device *dev)
> > {
> > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> >
> > - writel(1, priv->regs + DISP_REG_OD_EN);
> > + return clk_prepare_enable(priv->clk);
> > }
> >
> > -static void mtk_ufoe_start(struct device *dev)
> > +static void mtk_ddp_clk_disable(struct device *dev)
> > {
> > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> >
> > - writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
> > + clk_disable_unprepare(priv->clk);
> > }
> >
> > static void mtk_aal_config(struct device *dev, unsigned int w,
> > @@ -237,6 +202,40 @@ static void mtk_dither_stop(struct device
> > *dev)
> > writel_relaxed(0x0, priv->regs + DISP_REG_DITHER_EN);
> > }
> >
> > +static void mtk_dither_set(struct device *dev, unsigned int bpc,
> > + unsigned int cfg, struct cmdq_pkt
> > *cmdq_pkt)
> > +{
> > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > + mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc,
> > cfg,
> > + DISP_DITHERING, cmdq_pkt);
> > +}
> > +
> > +static void mtk_od_config(struct device *dev, unsigned int w,
> > + unsigned int h, unsigned int vrefresh,
> > + unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt)
> > +{
> > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv-
> > >regs, DISP_REG_OD_SIZE);
> > + mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg,
> > priv->regs, DISP_REG_OD_CFG);
> > + mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt);
> > +}
> > +
> > +static void mtk_od_start(struct device *dev)
> > +{
> > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > + writel(1, priv->regs + DISP_REG_OD_EN);
> > +}
> > +
> > +static void mtk_ufoe_start(struct device *dev)
> > +{
> > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > + writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
> > +}
> > +
> > static const struct mtk_ddp_comp_funcs ddp_aal = {
> > .clk_enable = mtk_ddp_clk_enable,
> > .clk_disable = mtk_ddp_clk_disable,
> > @@ -331,22 +330,22 @@ static const struct mtk_ddp_comp_funcs
> > ddp_ufoe = {
> > };
> >
> > static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX]
> > = {
> > + [MTK_DISP_AAL] = "aal",
> > + [MTK_DISP_BLS] = "bls",
> > + [MTK_DISP_CCORR] = "ccorr",
> > + [MTK_DISP_COLOR] = "color",
> > + [MTK_DISP_DITHER] = "dither",
> > + [MTK_DISP_GAMMA] = "gamma",
> > + [MTK_DISP_MUTEX] = "mutex",
> > + [MTK_DISP_OD] = "od",
> > [MTK_DISP_OVL] = "ovl",
> > [MTK_DISP_OVL_2L] = "ovl-2l",
> > + [MTK_DISP_PWM] = "pwm",
> > [MTK_DISP_RDMA] = "rdma",
> > - [MTK_DISP_WDMA] = "wdma",
> > - [MTK_DISP_COLOR] = "color",
> > - [MTK_DISP_CCORR] = "ccorr",
> > - [MTK_DISP_AAL] = "aal",
> > - [MTK_DISP_GAMMA] = "gamma",
> > - [MTK_DISP_DITHER] = "dither",
> > [MTK_DISP_UFOE] = "ufoe",
> > - [MTK_DSI] = "dsi",
> > + [MTK_DISP_WDMA] = "wdma",
> > [MTK_DPI] = "dpi",
> > - [MTK_DISP_PWM] = "pwm",
> > - [MTK_DISP_MUTEX] = "mutex",
> > - [MTK_DISP_OD] = "od",
> > - [MTK_DISP_BLS] = "bls",
> > + [MTK_DSI] = "dsi",
> > };
> >
> > struct mtk_ddp_comp_match {
> > @@ -500,12 +499,12 @@ int mtk_ddp_comp_init(struct device_node
> > *node, struct mtk_ddp_comp *comp,
> > type == MTK_DISP_CCORR ||
> > type == MTK_DISP_COLOR ||
> > type == MTK_DISP_GAMMA ||
> > - type == MTK_DPI ||
> > - type == MTK_DSI ||
> > type == MTK_DISP_OVL ||
> > type == MTK_DISP_OVL_2L ||
> > type == MTK_DISP_PWM ||
> > - type == MTK_DISP_RDMA)
> > + type == MTK_DISP_RDMA ||
> > + type == MTK_DPI ||
> > + type == MTK_DSI)
> > return 0;
> >
> > priv = devm_kzalloc(comp->dev, sizeof(*priv), GFP_KERNEL);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > index bb914d976cf5..d317b944df66 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > @@ -18,22 +18,22 @@ struct mtk_plane_state;
> > struct drm_crtc_state;
> >
> > enum mtk_ddp_comp_type {
> > - MTK_DISP_OVL,
> > - MTK_DISP_OVL_2L,
> > - MTK_DISP_RDMA,
> > - MTK_DISP_WDMA,
> > - MTK_DISP_COLOR,
> > + MTK_DISP_AAL,
> > + MTK_DISP_BLS,
> > MTK_DISP_CCORR,
> > + MTK_DISP_COLOR,
> > MTK_DISP_DITHER,
> > - MTK_DISP_AAL,
> > MTK_DISP_GAMMA,
> > - MTK_DISP_UFOE,
> > - MTK_DSI,
> > - MTK_DPI,
> > - MTK_DISP_PWM,
> > MTK_DISP_MUTEX,
> > MTK_DISP_OD,
> > - MTK_DISP_BLS,
> > + MTK_DISP_OVL,
> > + MTK_DISP_OVL_2L,
> > + MTK_DISP_PWM,
> > + MTK_DISP_RDMA,
> > + MTK_DISP_UFOE,
> > + MTK_DISP_WDMA,
> > + MTK_DPI,
> > + MTK_DSI,
> > MTK_DDP_COMP_TYPE_MAX,
> > };
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index b46bdb8985da..a95dc1006b82 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -396,50 +396,20 @@ static const struct component_master_ops
> > mtk_drm_ops = {
> > };
> >
> > static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> > - { .compatible = "mediatek,mt2701-disp-ovl",
> > - .data = (void *)MTK_DISP_OVL },
> > - { .compatible = "mediatek,mt8173-disp-ovl",
> > - .data = (void *)MTK_DISP_OVL },
> > - { .compatible = "mediatek,mt8183-disp-ovl",
> > - .data = (void *)MTK_DISP_OVL },
> > - { .compatible = "mediatek,mt8183-disp-ovl-2l",
> > - .data = (void *)MTK_DISP_OVL_2L },
> > - { .compatible = "mediatek,mt2701-disp-rdma",
> > - .data = (void *)MTK_DISP_RDMA },
> > - { .compatible = "mediatek,mt8173-disp-rdma",
> > - .data = (void *)MTK_DISP_RDMA },
> > - { .compatible = "mediatek,mt8183-disp-rdma",
> > - .data = (void *)MTK_DISP_RDMA },
> > - { .compatible = "mediatek,mt8173-disp-wdma",
> > - .data = (void *)MTK_DISP_WDMA },
> > + { .compatible = "mediatek,mt8173-disp-aal",
> > + .data = (void *)MTK_DISP_AAL},
> > { .compatible = "mediatek,mt8183-disp-ccorr",
> > .data = (void *)MTK_DISP_CCORR },
> > { .compatible = "mediatek,mt2701-disp-color",
> > .data = (void *)MTK_DISP_COLOR },
> > { .compatible = "mediatek,mt8173-disp-color",
> > .data = (void *)MTK_DISP_COLOR },
> > - { .compatible = "mediatek,mt8173-disp-aal",
> > - .data = (void *)MTK_DISP_AAL},
> > + { .compatible = "mediatek,mt8183-disp-dither",
> > + .data = (void *)MTK_DISP_DITHER },
> > { .compatible = "mediatek,mt8173-disp-gamma",
> > .data = (void *)MTK_DISP_GAMMA, },
> > { .compatible = "mediatek,mt8183-disp-gamma",
> > .data = (void *)MTK_DISP_GAMMA, },
> > - { .compatible = "mediatek,mt8183-disp-dither",
> > - .data = (void *)MTK_DISP_DITHER },
> > - { .compatible = "mediatek,mt8173-disp-ufoe",
> > - .data = (void *)MTK_DISP_UFOE },
> > - { .compatible = "mediatek,mt2701-dsi",
> > - .data = (void *)MTK_DSI },
> > - { .compatible = "mediatek,mt8173-dsi",
> > - .data = (void *)MTK_DSI },
> > - { .compatible = "mediatek,mt8183-dsi",
> > - .data = (void *)MTK_DSI },
> > - { .compatible = "mediatek,mt2701-dpi",
> > - .data = (void *)MTK_DPI },
> > - { .compatible = "mediatek,mt8173-dpi",
> > - .data = (void *)MTK_DPI },
> > - { .compatible = "mediatek,mt8183-dpi",
> > - .data = (void *)MTK_DPI },
> > { .compatible = "mediatek,mt2701-disp-mutex",
> > .data = (void *)MTK_DISP_MUTEX },
> > { .compatible = "mediatek,mt2712-disp-mutex",
> > @@ -448,12 +418,42 @@ static const struct of_device_id
> > mtk_ddp_comp_dt_ids[] = {
> > .data = (void *)MTK_DISP_MUTEX },
> > { .compatible = "mediatek,mt8183-disp-mutex",
> > .data = (void *)MTK_DISP_MUTEX },
> > + { .compatible = "mediatek,mt8173-disp-od",
> > + .data = (void *)MTK_DISP_OD },
> > + { .compatible = "mediatek,mt2701-disp-ovl",
> > + .data = (void *)MTK_DISP_OVL },
> > + { .compatible = "mediatek,mt8173-disp-ovl",
> > + .data = (void *)MTK_DISP_OVL },
> > + { .compatible = "mediatek,mt8183-disp-ovl",
> > + .data = (void *)MTK_DISP_OVL },
> > + { .compatible = "mediatek,mt8183-disp-ovl-2l",
> > + .data = (void *)MTK_DISP_OVL_2L },
> > { .compatible = "mediatek,mt2701-disp-pwm",
> > .data = (void *)MTK_DISP_BLS },
> > { .compatible = "mediatek,mt8173-disp-pwm",
> > .data = (void *)MTK_DISP_PWM },
> > - { .compatible = "mediatek,mt8173-disp-od",
> > - .data = (void *)MTK_DISP_OD },
> > + { .compatible = "mediatek,mt2701-disp-rdma",
> > + .data = (void *)MTK_DISP_RDMA },
> > + { .compatible = "mediatek,mt8173-disp-rdma",
> > + .data = (void *)MTK_DISP_RDMA },
> > + { .compatible = "mediatek,mt8183-disp-rdma",
> > + .data = (void *)MTK_DISP_RDMA },
> > + { .compatible = "mediatek,mt8173-disp-ufoe",
> > + .data = (void *)MTK_DISP_UFOE },
> > + { .compatible = "mediatek,mt8173-disp-wdma",
> > + .data = (void *)MTK_DISP_WDMA },
> > + { .compatible = "mediatek,mt2701-dpi",
> > + .data = (void *)MTK_DPI },
> > + { .compatible = "mediatek,mt8173-dpi",
> > + .data = (void *)MTK_DPI },
> > + { .compatible = "mediatek,mt8183-dpi",
> > + .data = (void *)MTK_DPI },
> > + { .compatible = "mediatek,mt2701-dsi",
> > + .data = (void *)MTK_DSI },
> > + { .compatible = "mediatek,mt8173-dsi",
> > + .data = (void *)MTK_DSI },
> > + { .compatible = "mediatek,mt8183-dsi",
> > + .data = (void *)MTK_DSI },
> > { }
> > };
> >
> > @@ -542,8 +542,8 @@ static int mtk_drm_probe(struct platform_device
> > *pdev)
> > comp_type == MTK_DISP_OVL ||
> > comp_type == MTK_DISP_OVL_2L ||
> > comp_type == MTK_DISP_RDMA ||
> > - comp_type == MTK_DSI ||
> > - comp_type == MTK_DPI) {
> > + comp_type == MTK_DPI ||
> > + comp_type == MTK_DSI) {
> > dev_info(dev, "Adding component match for
> > %pOF\n",
> > node);
> > drm_of_component_match_add(dev, &match,
> > compare_of,
> > --
> > 2.18.0
> >
--
Jason-JH Lin <jason-jh.lin@mediatek.com>
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next prev parent reply other threads:[~2021-08-24 17:58 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-19 2:23 [PATCH v8 00/13] Add Mediatek Soc DRM (vdosys0) support for mt8195 jason-jh.lin
2021-08-19 2:23 ` [PATCH v8 01/13] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding jason-jh.lin
2021-08-19 15:00 ` Chun-Kuang Hu
2021-08-24 16:11 ` Jason-JH Lin
2021-08-19 2:23 ` [PATCH v8 02/13] dt-bindings: mediatek: display: split each block to individual yaml jason-jh.lin
2021-08-19 2:23 ` [PATCH v8 03/13] dt-bindings: mediatek: add mediatek, dsc.yaml for mt8195 SoC binding jason-jh.lin
2021-08-21 23:14 ` Chun-Kuang Hu
2021-08-24 17:59 ` [PATCH v8 03/13] dt-bindings: mediatek: add mediatek,dsc.yaml " Jason-JH Lin
2021-08-19 2:23 ` [PATCH v8 04/13] dt-bindings: mediatek: display: add " jason-jh.lin
2021-08-19 2:23 ` [PATCH v8 05/13] arm64: dts: mt8195: add display node for vdosys0 jason-jh.lin
2021-08-19 2:23 ` [PATCH v8 06/13] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 jason-jh.lin
2021-08-19 2:23 ` [PATCH v8 07/13] soc: mediatek: add mtk-mutex " jason-jh.lin
2021-08-19 15:12 ` Chun-Kuang Hu
2021-08-24 17:47 ` Jason-JH Lin
2021-08-19 2:23 ` [PATCH v8 08/13] drm/mediatek: remove unused define in mtk_drm_ddp_comp.c jason-jh.lin
2021-08-19 15:14 ` Chun-Kuang Hu
2021-08-19 2:23 ` [PATCH v8 09/13] drm/mediatek: rename the define of register offset jason-jh.lin
2021-08-19 15:17 ` Chun-Kuang Hu
2021-08-19 2:23 ` [PATCH v8 10/13] drm/mediatek: adjust to the alphabetic order for mediatek-drm jason-jh.lin
2021-08-19 23:14 ` Chun-Kuang Hu
2021-08-24 17:55 ` Jason-JH Lin [this message]
2021-08-19 2:23 ` [PATCH v8 11/13] drm/mediatek: add DSC support " jason-jh.lin
2021-08-19 23:16 ` Chun-Kuang Hu
2021-08-19 2:23 ` [PATCH v8 12/13] drm/mediatek: add MERGE " jason-jh.lin
2021-08-20 9:37 ` CK Hu
2021-08-20 15:43 ` Chun-Kuang Hu
2021-08-25 9:34 ` Jason-JH Lin
2021-08-19 2:23 ` [PATCH v8 13/13] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195 jason-jh.lin
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