From: Will Deacon <will@kernel.org>
To: Marc Zyngier <maz@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Mark Rutland <mark.rutland@arm.com>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Peter Shier <pshier@google.com>,
Raghavendra Rao Ananta <rananta@google.com>,
Ricardo Koller <ricarkol@google.com>,
Oliver Upton <oupton@google.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Linus Walleij <linus.walleij@linaro.org>,
kernel-team@android.com
Subject: Re: [PATCH v3 17/17] arm64: Add HWCAP for self-synchronising virtual counter
Date: Mon, 11 Oct 2021 12:00:09 +0100 [thread overview]
Message-ID: <20211011110008.GA4068@willie-the-truck> (raw)
In-Reply-To: <20211010114306.2910453-18-maz@kernel.org>
On Sun, Oct 10, 2021 at 12:43:06PM +0100, Marc Zyngier wrote:
> Since userspace can make use of the CNTVSS_EL0 instruction, expose
> it via a HWCAP.
>
> Suggested-by: Will Deacon <will@kernel.org>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> ---
> Documentation/arm64/elf_hwcaps.rst | 4 ++++
> arch/arm64/include/asm/hwcap.h | 1 +
> arch/arm64/include/uapi/asm/hwcap.h | 1 +
> arch/arm64/kernel/cpufeature.c | 3 ++-
> arch/arm64/kernel/cpuinfo.c | 1 +
> 5 files changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/arm64/elf_hwcaps.rst b/Documentation/arm64/elf_hwcaps.rst
> index ec1a5a63c1d0..af106af8e1c0 100644
> --- a/Documentation/arm64/elf_hwcaps.rst
> +++ b/Documentation/arm64/elf_hwcaps.rst
> @@ -247,6 +247,10 @@ HWCAP2_MTE
> Functionality implied by ID_AA64PFR1_EL1.MTE == 0b0010, as described
> by Documentation/arm64/memory-tagging-extension.rst.
>
> +HWCAP2_ECV
> +
> + Functionality implied by ID_AA64MMFR0_EL1.ECV == 0b0001.
> +
> 4. Unused AT_HWCAP bits
> -----------------------
>
> diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h
> index 8c129db8232a..b100e0055eab 100644
> --- a/arch/arm64/include/asm/hwcap.h
> +++ b/arch/arm64/include/asm/hwcap.h
> @@ -105,6 +105,7 @@
> #define KERNEL_HWCAP_RNG __khwcap2_feature(RNG)
> #define KERNEL_HWCAP_BTI __khwcap2_feature(BTI)
> #define KERNEL_HWCAP_MTE __khwcap2_feature(MTE)
> +#define KERNEL_HWCAP_ECV __khwcap2_feature(ECV)
>
> /*
> * This yields a mask that user programs can use to figure out what
> diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h
> index b8f41aa234ee..7b23b16f21ce 100644
> --- a/arch/arm64/include/uapi/asm/hwcap.h
> +++ b/arch/arm64/include/uapi/asm/hwcap.h
> @@ -75,5 +75,6 @@
> #define HWCAP2_RNG (1 << 16)
> #define HWCAP2_BTI (1 << 17)
> #define HWCAP2_MTE (1 << 18)
> +#define HWCAP2_ECV (1 << 19)
>
> #endif /* _UAPI__ASM_HWCAP_H */
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 26b11ce8fff6..97ed37c6ce5e 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -279,7 +279,7 @@ static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
> };
>
> static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
> - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0),
> + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0),
> ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0),
> ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0),
This needs an update to Documentation/arm64/cpu-feature-registers.rst.
With that:
Acked-by: Will Deacon <will@kernel.org>
Will
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next prev parent reply other threads:[~2021-10-11 11:01 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-10 11:42 [PATCH v3 00/17] clocksource/arm_arch_timer: Add basic ARMv8.6 support Marc Zyngier
2021-10-10 11:42 ` [PATCH v3 01/17] clocksource/arm_arch_timer: Add build-time guards for unhandled register accesses Marc Zyngier
2021-10-10 11:42 ` [PATCH v3 02/17] clocksource/arm_arch_timer: Drop CNT*_TVAL read accessors Marc Zyngier
2021-10-10 11:42 ` [PATCH v3 03/17] clocksource/arm_arch_timer: Extend write side of timer register accessors to u64 Marc Zyngier
2021-10-10 11:42 ` [PATCH v3 04/17] clocksource/arm_arch_timer: Move system register timer programming over to CVAL Marc Zyngier
2021-10-10 11:42 ` [PATCH v3 05/17] clocksource/arm_arch_timer: Move drop _tval from erratum function names Marc Zyngier
2021-10-10 11:42 ` [PATCH v3 06/17] clocksource/arm_arch_timer: Fix MMIO base address vs callback ordering issue Marc Zyngier
2021-10-10 11:42 ` [PATCH v3 07/17] clocksource/arm_arch_timer: Move MMIO timer programming over to CVAL Marc Zyngier
2021-10-10 11:42 ` [PATCH v3 08/17] clocksource/arm_arch_timer: Advertise 56bit timer to the core code Marc Zyngier
2021-10-10 11:42 ` [PATCH v3 09/17] clocksource/arm_arch_timer: Work around broken CVAL implementations Marc Zyngier
2021-10-10 11:42 ` [PATCH v3 10/17] clocksource/arm_arch_timer: Remove any trace of the TVAL programming interface Marc Zyngier
2021-10-10 11:43 ` [PATCH v3 11/17] clocksource/arm_arch_timer: Drop unnecessary ISB on CVAL programming Marc Zyngier
2021-10-10 11:43 ` [PATCH v3 12/17] clocksource/arm_arch_timer: Fix masking for high freq counters Marc Zyngier
2021-10-10 11:43 ` [PATCH v3 13/17] clocksource/arch_arm_timer: Move workaround synchronisation around Marc Zyngier
2021-10-10 11:43 ` [PATCH v3 14/17] arm64: Add a capability for FEAT_ECV Marc Zyngier
2021-10-11 10:56 ` Will Deacon
2021-10-11 10:57 ` Will Deacon
2021-10-10 11:43 ` [PATCH v3 15/17] arm64: Add CNT{P, V}CTSS_EL0 alternatives to cnt{p, v}ct_el0 Marc Zyngier
2021-10-11 10:33 ` [PATCH v3 15/17] arm64: Add CNT{P,V}CTSS_EL0 alternatives to cnt{p,v}ct_el0 Will Deacon
2021-10-10 11:43 ` [PATCH v3 16/17] arm64: Add handling of CNTVCTSS traps Marc Zyngier
2021-10-11 10:54 ` Will Deacon
2021-10-10 11:43 ` [PATCH v3 17/17] arm64: Add HWCAP for self-synchronising virtual counter Marc Zyngier
2021-10-11 11:00 ` Will Deacon [this message]
2021-10-11 11:02 ` [PATCH v3 00/17] clocksource/arm_arch_timer: Add basic ARMv8.6 support Will Deacon
2021-10-11 13:39 ` Marc Zyngier
2021-10-16 21:59 ` Daniel Lezcano
2021-10-17 9:57 ` Marc Zyngier
2021-10-18 7:51 ` Daniel Lezcano
2021-10-19 8:00 ` Marc Zyngier
2021-10-19 8:04 ` Daniel Lezcano
2021-10-19 11:09 ` Will Deacon
2021-10-19 11:10 ` Daniel Lezcano
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