From: Leo Yan <leo.yan@linaro.org>
To: Ali Saidi <alisaidi@amazon.com>
Cc: acme@kernel.org, alexander.shishkin@linux.intel.com,
andrew.kilroy@arm.com, benh@kernel.crashing.org,
german.gomez@arm.com, james.clark@arm.com, john.garry@huawei.com,
jolsa@kernel.org, kjain@linux.ibm.com, lihuafei1@huawei.com,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
mark.rutland@arm.com, mathieu.poirier@linaro.org,
mingo@redhat.com, namhyung@kernel.org, peterz@infradead.org,
will@kernel.org, yao.jin@linux.intel.com
Subject: Re: [PATCH v2 2/2] perf mem: Support HITM for when mem_lvl_num is used
Date: Mon, 14 Mar 2022 14:33:53 +0800 [thread overview]
Message-ID: <20220314063353.GB163961@leoy-ThinkPad-X240s> (raw)
In-Reply-To: <20220313191933.26621-1-alisaidi@amazon.com>
On Sun, Mar 13, 2022 at 07:19:33PM +0000, Ali Saidi wrote:
[...]
> > > > + if (lvl & P(LVL, L3) || lnum == P(LVLNUM, L4)) {
> > >
> > > According to a comment in the previous patch, using L4 is specific to Neoverse, right?
> > >
> > > Maybe we need to distinguish the Neoverse case from the generic one here as well
> > >
> > > if (is_neoverse)
> > > // treat L4 as llc
> > > else
> > > // treat L3 as llc
> >
> > I personally think it's not good idea to distinguish platforms in the decoding code.
>
> I agree here. The more we talk about this, the more I'm wondering if we're
> spending too much code solving a problem that doesn't exist. I know of no
> Neoverse systems that actually have 4 cache levels, they all actually have three
> even though it's technically possible to have four. I have some doubts anyone
> will actually build four levels of cache and perhaps the most prudent path here
> is to assume only three levels (and adjust the previous patch) until someone
> actually produces a system with four levels instead of a lot of code that is
> never actually exercised?
I am not right person to say L4 cache is not implemented in Neoverse
platforms; my guess for a "System cache" data source might be L3 or
L4 and it is a implementation dependent. Maybe German or Arm mates
could confirm for this.
Thanks,
Leo
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next prev parent reply other threads:[~2022-03-14 6:35 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-21 22:47 [PATCH v2 1/2] perf arm-spe: Use SPE data source for neoverse cores Ali Saidi
2022-02-21 22:48 ` [PATCH v2 2/2] perf mem: Support HITM for when mem_lvl_num is used Ali Saidi
2022-03-02 15:39 ` German Gomez
2022-03-13 12:44 ` Leo Yan
2022-03-13 19:19 ` Ali Saidi
2022-03-14 6:33 ` Leo Yan [this message]
2022-03-14 18:00 ` German Gomez
2022-03-14 18:37 ` Ali Saidi
2022-03-15 18:44 ` German Gomez
2022-03-16 11:43 ` German Gomez
2022-03-16 12:42 ` Leo Yan
2022-03-16 15:10 ` German Gomez
2022-03-02 11:59 ` [PATCH v2 1/2] perf arm-spe: Use SPE data source for neoverse cores German Gomez
2022-03-13 11:46 ` Leo Yan
2022-03-13 19:06 ` Ali Saidi
2022-03-14 4:05 ` Leo Yan
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