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From: Leo Yan <leo.yan@linaro.org>
To: German Gomez <german.gomez@arm.com>
Cc: Ali Saidi <alisaidi@amazon.com>,
	acme@kernel.org, alexander.shishkin@linux.intel.com,
	andrew.kilroy@arm.com, benh@kernel.crashing.org,
	james.clark@arm.com, john.garry@huawei.com, jolsa@kernel.org,
	kjain@linux.ibm.com, lihuafei1@huawei.com,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
	mark.rutland@arm.com, mathieu.poirier@linaro.org,
	mingo@redhat.com, namhyung@kernel.org, peterz@infradead.org,
	will@kernel.org, yao.jin@linux.intel.com,
	Nick.Forrington@arm.com
Subject: Re: [PATCH v2 2/2] perf mem: Support HITM for when mem_lvl_num is used
Date: Wed, 16 Mar 2022 20:42:08 +0800	[thread overview]
Message-ID: <20220316124208.GA310478@leoy-ThinkPad-X240s> (raw)
In-Reply-To: <7b3aaa4d-5194-a729-f8ad-d55ada7fa58f@arm.com>

On Wed, Mar 16, 2022 at 11:43:52AM +0000, German Gomez wrote:

[...]

> >>> I had a look at the TRMs for the N1[1], V1[2] and N2[3] Neoverse cores
> >>> (specifically the LL_CACHE_RD pmu events). If we were to assign a number
> >>> to the system cache (assuming all caches are implemented):
> >>>
> >>> *For N1*, if L2 and L3 are implemented, system cache would follow at *L4*
> >> To date no one has built 4 level though. Everyone has only built three.
> > The N1SDP board advertises 4 levels (we use it regularly for testing perf patches)
> 
> That said, it's probably the odd one out.
> 
> I'm not against assuming 3 levels. Later if there's is a strong need for L4, indeed we can go back and change it.

Thanks for the info.

For exploring cache hierarchy via sysFS is a good idea, the only one
concern for me is: can we simply take the system cache as the same
thing as the highest level cache?  If so, I think another option is to
define a cache level as "PERF_MEM_LVLNUM_SYSTEM_CACHE" and extend the
decoding code for support it.

With PERF_MEM_LVLNUM_SYSTEM_CACHE, it can tell users clearly the data
source from system cache, and users can easily map this info with the
cache media on the working platform.

In practice, I don't object to use cache level 3 at first step.  At
least this can meet the requirement at current stage.

Thanks,
Leo

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  reply	other threads:[~2022-03-16 12:43 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-21 22:47 [PATCH v2 1/2] perf arm-spe: Use SPE data source for neoverse cores Ali Saidi
2022-02-21 22:48 ` [PATCH v2 2/2] perf mem: Support HITM for when mem_lvl_num is used Ali Saidi
2022-03-02 15:39   ` German Gomez
2022-03-13 12:44     ` Leo Yan
2022-03-13 19:19       ` Ali Saidi
2022-03-14  6:33         ` Leo Yan
2022-03-14 18:00           ` German Gomez
2022-03-14 18:37             ` Ali Saidi
2022-03-15 18:44               ` German Gomez
2022-03-16 11:43                 ` German Gomez
2022-03-16 12:42                   ` Leo Yan [this message]
2022-03-16 15:10                     ` German Gomez
2022-03-02 11:59 ` [PATCH v2 1/2] perf arm-spe: Use SPE data source for neoverse cores German Gomez
2022-03-13 11:46   ` Leo Yan
2022-03-13 19:06     ` Ali Saidi
2022-03-14  4:05       ` Leo Yan

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