* [PATCH v4 1/4] dt-bindings: soc: Add i.MX8MP media block control DT bindings
2022-03-28 7:20 [PATCH v4 0/4] imx8mp: Add media block control Laurent Pinchart
@ 2022-03-28 7:20 ` Laurent Pinchart
2022-03-28 7:20 ` [PATCH v4 2/4] soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl Laurent Pinchart
` (3 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Laurent Pinchart @ 2022-03-28 7:20 UTC (permalink / raw)
To: linux-arm-kernel, Shawn Guo, Sascha Hauer
Cc: Pengutronix Kernel Team, NXP Linux Team, Fabio Estevam,
Paul Elder, Lucas Stach, Marek Vasut, Alexander Stein
From: Paul Elder <paul.elder@ideasonboard.com>
The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level
peripheral providing access to the NoC and ensuring proper power
sequencing of the peripherals within the MEDIAMIX domain. Add DT
bindings for it.
There is already a driver for block controls of other SoCs in the i.MX8M
family, so these bindings will expand upon that.
Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Marek Vasut <marex@denx.de>
---
Changes since v3:
- Drop ISP2 power domain, it turned out to be incorrect
Changes since v1:
- Lower reg size to 0x138
- Add ISP2 power domain and rename ISP to ISP1
---
.../soc/imx/fsl,imx8mp-media-blk-ctrl.yaml | 104 ++++++++++++++++++
include/dt-bindings/power/imx8mp-power.h | 10 ++
2 files changed, 114 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml
diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml
new file mode 100644
index 000000000000..21d3ee486295
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml
@@ -0,0 +1,104 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8MP Media Block Control
+
+maintainers:
+ - Paul Elder <paul.elder@ideasonboard.com>
+
+description:
+ The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level peripheral
+ providing access to the NoC and ensuring proper power sequencing of the
+ peripherals within the MEDIAMIX domain.
+
+properties:
+ compatible:
+ items:
+ - const: fsl,imx8mp-media-blk-ctrl
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ power-domains:
+ maxItems: 10
+
+ power-domain-names:
+ items:
+ - const: bus
+ - const: mipi-dsi1
+ - const: mipi-csi1
+ - const: lcdif1
+ - const: isi
+ - const: mipi-csi2
+ - const: lcdif2
+ - const: isp
+ - const: dwe
+ - const: mipi-dsi2
+
+ clocks:
+ items:
+ - description: The APB clock
+ - description: The AXI clock
+ - description: The pixel clock for the first CSI2 receiver (aclk)
+ - description: The pixel clock for the second CSI2 receiver (aclk)
+ - description: The pixel clock for the first LCDIF (pix_clk)
+ - description: The pixel clock for the second LCDIF (pix_clk)
+ - description: The core clock for the ISP (clk)
+ - description: The MIPI-PHY reference clock used by DSI
+
+ clock-names:
+ items:
+ - const: apb
+ - const: axi
+ - const: cam1
+ - const: cam2
+ - const: disp1
+ - const: disp2
+ - const: isp
+ - const: phy
+
+required:
+ - compatible
+ - reg
+ - '#power-domain-cells'
+ - power-domains
+ - power-domain-names
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8mp-clock.h>
+ #include <dt-bindings/power/imx8mp-power.h>
+
+ media_blk_ctl: blk-ctl@32ec0000 {
+ compatible = "fsl,imx8mp-media-blk-ctrl", "syscon";
+ reg = <0x32ec0000 0x138>;
+ power-domains = <&mediamix_pd>, <&mipi_phy1_pd>, <&mipi_phy1_pd>,
+ <&mediamix_pd>, <&mediamix_pd>, <&mipi_phy2_pd>,
+ <&mediamix_pd>, <&ispdwp_pd>, <&ispdwp_pd>,
+ <&mipi_phy2_pd>;
+ power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", "lcdif1", "isi",
+ "mipi-csi2", "lcdif2", "isp1", "dwe", "mipi-dsi2";
+ clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
+ clock-names = "apb", "axi", "cam1", "cam2", "disp1", "disp2",
+ "isp", "phy";
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/include/dt-bindings/power/imx8mp-power.h b/include/dt-bindings/power/imx8mp-power.h
index 9f90c40a2c6c..bc8458f1e725 100644
--- a/include/dt-bindings/power/imx8mp-power.h
+++ b/include/dt-bindings/power/imx8mp-power.h
@@ -32,4 +32,14 @@
#define IMX8MP_HSIOBLK_PD_PCIE 3
#define IMX8MP_HSIOBLK_PD_PCIE_PHY 4
+#define IMX8MP_MEDIABLK_PD_MIPI_DSI_1 0
+#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_1 1
+#define IMX8MP_MEDIABLK_PD_LCDIF_1 2
+#define IMX8MP_MEDIABLK_PD_ISI 3
+#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_2 4
+#define IMX8MP_MEDIABLK_PD_LCDIF_2 5
+#define IMX8MP_MEDIABLK_PD_ISP 6
+#define IMX8MP_MEDIABLK_PD_DWE 7
+#define IMX8MP_MEDIABLK_PD_MIPI_DSI_2 8
+
#endif
--
Regards,
Laurent Pinchart
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v4 2/4] soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl
2022-03-28 7:20 [PATCH v4 0/4] imx8mp: Add media block control Laurent Pinchart
2022-03-28 7:20 ` [PATCH v4 1/4] dt-bindings: soc: Add i.MX8MP media block control DT bindings Laurent Pinchart
@ 2022-03-28 7:20 ` Laurent Pinchart
2022-03-28 7:20 ` [PATCH v4 3/4] arm64: dts: imx8mp: Add MEDIAMIX power domains Laurent Pinchart
` (2 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Laurent Pinchart @ 2022-03-28 7:20 UTC (permalink / raw)
To: linux-arm-kernel, Shawn Guo, Sascha Hauer
Cc: Pengutronix Kernel Team, NXP Linux Team, Fabio Estevam,
Paul Elder, Lucas Stach, Marek Vasut, Alexander Stein
From: Paul Elder <paul.elder@ideasonboard.com>
Add the description for the i.MX8MP media blk-ctrl.
Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Tested-by: Marek Vasut <marex@denx.de> # MX8MP LCDIF #1 and #2
---
Changes since v3:
- Drop ISP2 power domain, it turned out to be incorrect
- Rebase on top of Shawn's for-next branch
Changes since v1:
- Add ISP2 power domain and rename ISP to ISP1
---
drivers/soc/imx/imx8m-blk-ctrl.c | 123 ++++++++++++++++++++++++++++++-
1 file changed, 121 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c
index 122f9c884b38..7061c69fd25c 100644
--- a/drivers/soc/imx/imx8m-blk-ctrl.c
+++ b/drivers/soc/imx/imx8m-blk-ctrl.c
@@ -15,11 +15,12 @@
#include <dt-bindings/power/imx8mm-power.h>
#include <dt-bindings/power/imx8mn-power.h>
+#include <dt-bindings/power/imx8mp-power.h>
#include <dt-bindings/power/imx8mq-power.h>
#define BLK_SFT_RSTN 0x0
#define BLK_CLK_EN 0x4
-#define BLK_MIPI_RESET_DIV 0x8 /* Mini/Nano DISPLAY_BLK_CTRL only */
+#define BLK_MIPI_RESET_DIV 0x8 /* Mini/Nano/Plus DISPLAY_BLK_CTRL only */
struct imx8m_blk_ctrl_domain;
@@ -41,7 +42,7 @@ struct imx8m_blk_ctrl_domain_data {
u32 clk_mask;
/*
- * i.MX8M Mini and Nano have a third DISPLAY_BLK_CTRL register
+ * i.MX8M Mini, Nano and Plus have a third DISPLAY_BLK_CTRL register
* which is used to control the reset for the MIPI Phy.
* Since it's only present in certain circumstances,
* an if-statement should be used before setting and clearing this
@@ -590,6 +591,121 @@ static const struct imx8m_blk_ctrl_data imx8mn_disp_blk_ctl_dev_data = {
.num_domains = ARRAY_SIZE(imx8mn_disp_blk_ctl_domain_data),
};
+static int imx8mp_media_power_notifier(struct notifier_block *nb,
+ unsigned long action, void *data)
+{
+ struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
+ power_nb);
+
+ if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)
+ return NOTIFY_OK;
+
+ /* Enable bus clock and deassert bus reset */
+ regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(8));
+ regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(8));
+
+ /*
+ * On power up we have no software backchannel to the GPC to
+ * wait for the ADB handshake to happen, so we just delay for a
+ * bit. On power down the GPC driver waits for the handshake.
+ */
+ if (action == GENPD_NOTIFY_ON)
+ udelay(5);
+
+ return NOTIFY_OK;
+}
+
+/*
+ * From i.MX 8M Plus Applications Processor Reference Manual, Rev. 1,
+ * section 13.2.2, 13.2.3
+ * isp-ahb and dwe are not in Figure 13-5. Media BLK_CTRL Clocks
+ */
+static const struct imx8m_blk_ctrl_domain_data imx8mp_media_blk_ctl_domain_data[] = {
+ [IMX8MP_MEDIABLK_PD_MIPI_DSI_1] = {
+ .name = "mediablk-mipi-dsi-1",
+ .clk_names = (const char *[]){ "apb", "phy", },
+ .num_clks = 2,
+ .gpc_name = "mipi-dsi1",
+ .rst_mask = BIT(0) | BIT(1),
+ .clk_mask = BIT(0) | BIT(1),
+ .mipi_phy_rst_mask = BIT(17),
+ },
+ [IMX8MP_MEDIABLK_PD_MIPI_CSI2_1] = {
+ .name = "mediablk-mipi-csi2-1",
+ .clk_names = (const char *[]){ "apb", "cam1" },
+ .num_clks = 2,
+ .gpc_name = "mipi-csi1",
+ .rst_mask = BIT(2) | BIT(3),
+ .clk_mask = BIT(2) | BIT(3),
+ .mipi_phy_rst_mask = BIT(16),
+ },
+ [IMX8MP_MEDIABLK_PD_LCDIF_1] = {
+ .name = "mediablk-lcdif-1",
+ .clk_names = (const char *[]){ "disp1", "apb", "axi", },
+ .num_clks = 3,
+ .gpc_name = "lcdif1",
+ .rst_mask = BIT(4) | BIT(5) | BIT(23),
+ .clk_mask = BIT(4) | BIT(5) | BIT(23),
+ },
+ [IMX8MP_MEDIABLK_PD_ISI] = {
+ .name = "mediablk-isi",
+ .clk_names = (const char *[]){ "axi", "apb" },
+ .num_clks = 2,
+ .gpc_name = "isi",
+ .rst_mask = BIT(6) | BIT(7),
+ .clk_mask = BIT(6) | BIT(7),
+ },
+ [IMX8MP_MEDIABLK_PD_MIPI_CSI2_2] = {
+ .name = "mediablk-mipi-csi2-2",
+ .clk_names = (const char *[]){ "apb", "cam2" },
+ .num_clks = 2,
+ .gpc_name = "mipi-csi2",
+ .rst_mask = BIT(9) | BIT(10),
+ .clk_mask = BIT(9) | BIT(10),
+ .mipi_phy_rst_mask = BIT(30),
+ },
+ [IMX8MP_MEDIABLK_PD_LCDIF_2] = {
+ .name = "mediablk-lcdif-2",
+ .clk_names = (const char *[]){ "disp1", "apb", "axi", },
+ .num_clks = 3,
+ .gpc_name = "lcdif2",
+ .rst_mask = BIT(11) | BIT(12) | BIT(24),
+ .clk_mask = BIT(11) | BIT(12) | BIT(24),
+ },
+ [IMX8MP_MEDIABLK_PD_ISP] = {
+ .name = "mediablk-isp",
+ .clk_names = (const char *[]){ "isp", "axi", "apb" },
+ .num_clks = 3,
+ .gpc_name = "isp",
+ .rst_mask = BIT(16) | BIT(17) | BIT(18),
+ .clk_mask = BIT(16) | BIT(17) | BIT(18),
+ },
+ [IMX8MP_MEDIABLK_PD_DWE] = {
+ .name = "mediablk-dwe",
+ .clk_names = (const char *[]){ "axi", "apb" },
+ .num_clks = 2,
+ .gpc_name = "dwe",
+ .rst_mask = BIT(19) | BIT(20) | BIT(21),
+ .clk_mask = BIT(19) | BIT(20) | BIT(21),
+ },
+ [IMX8MP_MEDIABLK_PD_MIPI_DSI_2] = {
+ .name = "mediablk-mipi-dsi-2",
+ .clk_names = (const char *[]){ "phy", },
+ .num_clks = 1,
+ .gpc_name = "mipi-dsi2",
+ .rst_mask = BIT(22),
+ .clk_mask = BIT(22),
+ .mipi_phy_rst_mask = BIT(29),
+ },
+};
+
+static const struct imx8m_blk_ctrl_data imx8mp_media_blk_ctl_dev_data = {
+ .max_reg = 0x138,
+ .power_notifier_fn = imx8mp_media_power_notifier,
+ .domains = imx8mp_media_blk_ctl_domain_data,
+ .num_domains = ARRAY_SIZE(imx8mp_media_blk_ctl_domain_data),
+};
+
static int imx8mq_vpu_power_notifier(struct notifier_block *nb,
unsigned long action, void *data)
{
@@ -662,6 +778,9 @@ static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
}, {
.compatible = "fsl,imx8mn-disp-blk-ctrl",
.data = &imx8mn_disp_blk_ctl_dev_data
+ }, {
+ .compatible = "fsl,imx8mp-media-blk-ctrl",
+ .data = &imx8mp_media_blk_ctl_dev_data
}, {
.compatible = "fsl,imx8mq-vpu-blk-ctrl",
.data = &imx8mq_vpu_blk_ctl_dev_data
--
Regards,
Laurent Pinchart
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v4 3/4] arm64: dts: imx8mp: Add MEDIAMIX power domains
2022-03-28 7:20 [PATCH v4 0/4] imx8mp: Add media block control Laurent Pinchart
2022-03-28 7:20 ` [PATCH v4 1/4] dt-bindings: soc: Add i.MX8MP media block control DT bindings Laurent Pinchart
2022-03-28 7:20 ` [PATCH v4 2/4] soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl Laurent Pinchart
@ 2022-03-28 7:20 ` Laurent Pinchart
2022-03-30 9:56 ` paul.elder
2022-03-28 7:20 ` [PATCH v4 4/4] arm64: dts: imx8mp: Add MEDIA_BLK_CTRL Laurent Pinchart
2022-03-31 8:12 ` [PATCH v4 0/4] imx8mp: Add media block control Peng Fan
4 siblings, 1 reply; 7+ messages in thread
From: Laurent Pinchart @ 2022-03-28 7:20 UTC (permalink / raw)
To: linux-arm-kernel, Shawn Guo, Sascha Hauer
Cc: Pengutronix Kernel Team, NXP Linux Team, Fabio Estevam,
Paul Elder, Lucas Stach, Marek Vasut, Alexander Stein
Add the power domains related to the MEDIAMIX to the GPC.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Marek Vasut <marex@denx.de>
---
Changes since v2:
- Drop assigned clocks, they moved to the media-blk-ctrl node
---
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 096139d7c365..55f2fa2a562d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -488,6 +488,11 @@ pgc {
#address-cells = <1>;
#size-cells = <0>;
+ pgc_mipi_phy1: power-domain@0 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>;
+ };
+
pgc_pcie_phy: power-domain@1 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
@@ -530,6 +535,18 @@ pgc_gpu3d: power-domain@9 {
power-domains = <&pgc_gpumix>;
};
+ pgc_mediamix: power-domain@10 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>;
+ clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
+ };
+
+ pgc_mipi_phy2: power-domain@16 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
+ };
+
pgc_hsiomix: power-domains@17 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
@@ -539,6 +556,12 @@ pgc_hsiomix: power-domains@17 {
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
assigned-clock-rates = <500000000>;
};
+
+ pgc_ispdwp: power-domain@18 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>;
+ clocks = <&clk IMX8MP_CLK_MEDIA_ISP_DIV>;
+ };
};
};
};
--
Regards,
Laurent Pinchart
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v4 3/4] arm64: dts: imx8mp: Add MEDIAMIX power domains
2022-03-28 7:20 ` [PATCH v4 3/4] arm64: dts: imx8mp: Add MEDIAMIX power domains Laurent Pinchart
@ 2022-03-30 9:56 ` paul.elder
0 siblings, 0 replies; 7+ messages in thread
From: paul.elder @ 2022-03-30 9:56 UTC (permalink / raw)
To: Laurent Pinchart
Cc: linux-arm-kernel, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, NXP Linux Team, Fabio Estevam,
Lucas Stach, Marek Vasut, Alexander Stein
Hi Laurent,
On Mon, Mar 28, 2022 at 10:20:08AM +0300, Laurent Pinchart wrote:
> Add the power domains related to the MEDIAMIX to the GPC.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Paul Elder <paul.elder@ideasonboard.com>
> ---
> Changes since v2:
>
> - Drop assigned clocks, they moved to the media-blk-ctrl node
> ---
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 23 +++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> index 096139d7c365..55f2fa2a562d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -488,6 +488,11 @@ pgc {
> #address-cells = <1>;
> #size-cells = <0>;
>
> + pgc_mipi_phy1: power-domain@0 {
> + #power-domain-cells = <0>;
> + reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>;
> + };
> +
> pgc_pcie_phy: power-domain@1 {
> #power-domain-cells = <0>;
> reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
> @@ -530,6 +535,18 @@ pgc_gpu3d: power-domain@9 {
> power-domains = <&pgc_gpumix>;
> };
>
> + pgc_mediamix: power-domain@10 {
> + #power-domain-cells = <0>;
> + reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>;
> + clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
> + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
> + };
> +
> + pgc_mipi_phy2: power-domain@16 {
> + #power-domain-cells = <0>;
> + reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
> + };
> +
> pgc_hsiomix: power-domains@17 {
> #power-domain-cells = <0>;
> reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
> @@ -539,6 +556,12 @@ pgc_hsiomix: power-domains@17 {
> assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
> assigned-clock-rates = <500000000>;
> };
> +
> + pgc_ispdwp: power-domain@18 {
> + #power-domain-cells = <0>;
> + reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>;
> + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_DIV>;
> + };
> };
> };
> };
> --
> Regards,
>
> Laurent Pinchart
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
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^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v4 4/4] arm64: dts: imx8mp: Add MEDIA_BLK_CTRL
2022-03-28 7:20 [PATCH v4 0/4] imx8mp: Add media block control Laurent Pinchart
` (2 preceding siblings ...)
2022-03-28 7:20 ` [PATCH v4 3/4] arm64: dts: imx8mp: Add MEDIAMIX power domains Laurent Pinchart
@ 2022-03-28 7:20 ` Laurent Pinchart
2022-03-31 8:12 ` [PATCH v4 0/4] imx8mp: Add media block control Peng Fan
4 siblings, 0 replies; 7+ messages in thread
From: Laurent Pinchart @ 2022-03-28 7:20 UTC (permalink / raw)
To: linux-arm-kernel, Shawn Guo, Sascha Hauer
Cc: Pengutronix Kernel Team, NXP Linux Team, Fabio Estevam,
Paul Elder, Lucas Stach, Marek Vasut, Alexander Stein
From: Paul Elder <paul.elder@ideasonboard.com>
Add a DT node for the MEDIA_BLK_CTRL, which provides power domains for
the camera and display devices.
Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Marek Vasut <marex@denx.de>
---
Changes since v3:
- Drop ISP2 power domain, it turned out to be incorrect
Changes since v2:
- Add assigned clocks
---
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 38 +++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 55f2fa2a562d..9e68e897d644 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -988,6 +988,44 @@ aips4: bus@32c00000 {
#size-cells = <1>;
ranges;
+ media_blk_ctrl: blk-ctrl@32ec0000 {
+ compatible = "fsl,imx8mp-media-blk-ctrl",
+ "syscon";
+ reg = <0x32ec0000 0x10000>;
+ power-domains = <&pgc_mediamix>,
+ <&pgc_mipi_phy1>,
+ <&pgc_mipi_phy1>,
+ <&pgc_mediamix>,
+ <&pgc_mediamix>,
+ <&pgc_mipi_phy2>,
+ <&pgc_mediamix>,
+ <&pgc_ispdwp>,
+ <&pgc_ispdwp>,
+ <&pgc_mipi_phy2>;
+ power-domain-names = "bus", "mipi-dsi1", "mipi-csi1",
+ "lcdif1", "isi", "mipi-csi2",
+ "lcdif2", "isp", "dwe",
+ "mipi-dsi2";
+ clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
+ clock-names = "apb", "axi", "cam1", "cam2",
+ "disp1", "disp2", "isp", "phy";
+
+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
+ <&clk IMX8MP_CLK_MEDIA_APB>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
+ <&clk IMX8MP_SYS_PLL1_800M>;
+ assigned-clock-rates = <500000000>, <200000000>;
+
+ #power-domain-cells = <1>;
+ };
+
hsio_blk_ctrl: blk-ctrl@32f10000 {
compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
reg = <0x32f10000 0x24>;
--
Regards,
Laurent Pinchart
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 7+ messages in thread* RE: [PATCH v4 0/4] imx8mp: Add media block control
2022-03-28 7:20 [PATCH v4 0/4] imx8mp: Add media block control Laurent Pinchart
` (3 preceding siblings ...)
2022-03-28 7:20 ` [PATCH v4 4/4] arm64: dts: imx8mp: Add MEDIA_BLK_CTRL Laurent Pinchart
@ 2022-03-31 8:12 ` Peng Fan
4 siblings, 0 replies; 7+ messages in thread
From: Peng Fan @ 2022-03-31 8:12 UTC (permalink / raw)
To: Laurent Pinchart, linux-arm-kernel@lists.infradead.org, Shawn Guo,
Sascha Hauer
Cc: Pengutronix Kernel Team, dl-linux-imx, Fabio Estevam, Paul Elder,
Lucas Stach, Marek Vasut, Alexander Stein
> Subject: [PATCH v4 0/4] imx8mp: Add media block control
>
> Hello,
>
> This patch series adds support for the MEDIA_BLK_CTRL of the i.MX8MP to
> the imx8m-blk-ctrl driver, and integrates it in the i.MX8MP device tree.
>
> The patches depend on v2 of the series "soc: imx: gpcv2: add PGC control
> register indirection" from Lucas Stach [1]. For testing convenience, a branch
> that includes the dependency, based on Shawn's latest for-next branch, is
> available at [2].
>
> The series starts with DT bindings (1/4) and driver support (2/4), followed by
> addition of the MEDIAMIX power domains to the GPC DT node
> (3/4) and finally the new DT node for the MEDIA_BLK_CTRL.
>
> Changes since v3 are listed in changelogs in the individual patches.
>
> The patches have been tested with the ISI and ISP on the i.MX8MP. The ISI
> driver is still under development [3], and will be posted in the not too distant
> future. ISP support is in a dirty prototype state and will require more work.
Tested-by: Peng Fan <peng.fan@nxp.com>
>
> [1]
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.ke
> rnel.org%2Fall%2F20220207192547.1997549-1-l.stach%40pengutronix.de%2
> F&data=04%7C01%7Cpeng.fan%40nxp.com%7C7b6ea3d39e2240d9e92
> c08da108b6959%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63
> 7840488192591173%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMD
> AiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata
> =tf0Ct7LhL%2BOT6djWwNlD1%2Fe57mvEmc0asP9oAibX1cs%3D&reser
> ved=0
> [2]
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.linu
> xtv.org%2Fpinchartl%2Fmedia.git%2Flog%2F%3Fh%3Dnxp%2Fnext%2Fpower
> domains&data=04%7C01%7Cpeng.fan%40nxp.com%7C7b6ea3d39e224
> 0d9e92c08da108b6959%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C
> 0%7C637840488192591173%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4w
> LjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&a
> mp;sdata=%2FfC5OymggcxB6frrxYpEAtpE4F8n2yx0Ita3JevhBuw%3D&re
> served=0
> [3]
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.
> com%2Fideasonboard%2Fnxp%2Flinux%2F-%2Ftree%2Fpinchartl%2Fv5.17%2
> Fisi&data=04%7C01%7Cpeng.fan%40nxp.com%7C7b6ea3d39e2240d9e9
> 2c08da108b6959%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C6
> 37840488192591173%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwM
> DAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdat
> a=zX%2BwhXoap1ZaOWGSmGcowIfzoPji35OeZPGs%2FVuqGpk%3D&res
> erved=0
>
> Laurent Pinchart (1):
> arm64: dts: imx8mp: Add MEDIAMIX power domains
>
> Paul Elder (3):
> dt-bindings: soc: Add i.MX8MP media block control DT bindings
> soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl
> arm64: dts: imx8mp: Add MEDIA_BLK_CTRL
>
> .../soc/imx/fsl,imx8mp-media-blk-ctrl.yaml | 104 +++++++++++++++
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 61 +++++++++
> drivers/soc/imx/imx8m-blk-ctrl.c | 123
> +++++++++++++++++-
> include/dt-bindings/power/imx8mp-power.h | 10 ++
> 4 files changed, 296 insertions(+), 2 deletions(-) create mode 100644
> Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml
>
> --
> Regards,
>
> Laurent Pinchart
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