From: Conor Dooley <mail@conchuod.ie>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Palmer Dabbelt <palmer@rivosinc.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Sudeep Holla <sudeep.holla@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
"Rafael J . Wysocki" <rafael@kernel.org>
Cc: Daire McNamara <daire.mcnamara@microchip.com>,
Conor Dooley <conor.dooley@microchip.com>,
Niklas Cassel <niklas.cassel@wdc.com>,
Damien Le Moal <damien.lemoal@opensource.wdc.com>,
Geert Uytterhoeven <geert@linux-m68k.org>,
Zong Li <zong.li@sifive.com>,
Emil Renner Berthing <kernel@esmil.dk>,
Jonas Hahnfeld <hahnjo@hahnjo.de>, Guo Ren <guoren@kernel.org>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Changbin Du <changbin.du@intel.com>,
Heiko Stuebner <heiko@sntech.de>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
Rob Herring <robh@kernel.org>, Marc Zyngier <maz@kernel.org>,
Viresh Kumar <viresh.kumar@linaro.org>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Brice Goglin <Brice.Goglin@inria.fr>
Subject: [RFC 4/4] arm64: arch-topology move arm64 to the generic store_cpu_topology()
Date: Thu, 7 Jul 2022 23:04:37 +0100 [thread overview]
Message-ID: <20220707220436.4105443-5-mail@conchuod.ie> (raw)
In-Reply-To: <20220707220436.4105443-1-mail@conchuod.ie>
From: Conor Dooley <conor.dooley@microchip.com>
The default implementation of store_cpu_topology() was derived from the
arm64 implementation, but with the mpidr bits removed. Extract the mpidr
bits from the arch implementation to the callsites & use the generic
version.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/arm64/kernel/smp.c | 16 +++++++++++++--
arch/arm64/kernel/topology.c | 40 ------------------------------------
2 files changed, 14 insertions(+), 42 deletions(-)
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index 62ed361a4376..9e8acaa4c2f7 100644
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@ -234,7 +234,12 @@ asmlinkage notrace void secondary_start_kernel(void)
* Log the CPU info before it is marked online and might get read.
*/
cpuinfo_store_cpu();
- store_cpu_topology(cpu);
+
+ /*
+ * Uniprocessor systems can rely on default topology values
+ */
+ if (!(mpidr & MPIDR_UP_BITMASK))
+ store_cpu_topology(cpu);
/*
* Enable GIC and timers.
@@ -719,6 +724,7 @@ void __init smp_init_cpus(void)
void __init smp_prepare_cpus(unsigned int max_cpus)
{
const struct cpu_operations *ops;
+ u64 mpidr;
int err;
unsigned int cpu;
unsigned int this_cpu;
@@ -726,7 +732,13 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
init_cpu_topology();
this_cpu = smp_processor_id();
- store_cpu_topology(this_cpu);
+ mpidr = read_cpuid_mpidr();
+
+ /*
+ * Uniprocessor systems can rely on default topology values
+ */
+ if (!(mpidr & MPIDR_UP_BITMASK))
+ store_cpu_topology(this_cpu);
numa_store_cpu_info(this_cpu);
numa_add_cpu(this_cpu);
diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c
index 869ffc4d4484..7889a00f5487 100644
--- a/arch/arm64/kernel/topology.c
+++ b/arch/arm64/kernel/topology.c
@@ -22,46 +22,6 @@
#include <asm/cputype.h>
#include <asm/topology.h>
-void store_cpu_topology(unsigned int cpuid)
-{
- struct cpu_topology *cpuid_topo = &cpu_topology[cpuid];
- u64 mpidr;
-
- if (cpuid_topo->package_id != -1)
- goto topology_populated;
-
- mpidr = read_cpuid_mpidr();
-
- /* Uniprocessor systems can rely on default topology values */
- if (mpidr & MPIDR_UP_BITMASK)
- return;
-
- /*
- * This would be the place to create cpu topology based on MPIDR.
- *
- * However, it cannot be trusted to depict the actual topology; some
- * pieces of the architecture enforce an artificial cap on Aff0 values
- * (e.g. GICv3's ICC_SGI1R_EL1 limits it to 15), leading to an
- * artificial cycling of Aff1, Aff2 and Aff3 values. IOW, these end up
- * having absolutely no relationship to the actual underlying system
- * topology, and cannot be reasonably used as core / package ID.
- *
- * If the MT bit is set, Aff0 *could* be used to define a thread ID, but
- * we still wouldn't be able to obtain a sane core ID. This means we
- * need to entirely ignore MPIDR for any topology deduction.
- */
- cpuid_topo->thread_id = -1;
- cpuid_topo->core_id = cpuid;
- cpuid_topo->package_id = cpu_to_node(cpuid);
-
- pr_debug("CPU%u: cluster %d core %d thread %d mpidr %#016llx\n",
- cpuid, cpuid_topo->package_id, cpuid_topo->core_id,
- cpuid_topo->thread_id, mpidr);
-
-topology_populated:
- update_siblings_masks(cpuid);
-}
-
#ifdef CONFIG_ACPI
static bool __init acpi_cpu_is_threaded(int cpu)
{
--
2.37.0
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next prev parent reply other threads:[~2022-07-07 22:06 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-07 22:04 [PATCH/RFC 0/4] Fix RISC-V's arch-topology reporting Conor Dooley
2022-07-07 22:04 ` [RFC 1/4] riscv: arch-topology: fix default topology reporting Conor Dooley
2022-07-07 22:04 ` [RFC 2/4] arch-topology: add a default implementation of store_cpu_topology() Conor Dooley
2022-07-08 8:24 ` Sudeep Holla
2022-07-08 8:35 ` Conor.Dooley
2022-07-08 9:21 ` Sudeep Holla
2022-07-08 9:28 ` Geert Uytterhoeven
2022-07-08 9:47 ` Sudeep Holla
2022-07-08 10:03 ` Greg KH
2022-07-08 11:39 ` Sudeep Holla
2022-07-08 11:57 ` Conor.Dooley
2022-07-08 13:59 ` Sudeep Holla
2022-07-08 10:02 ` Conor.Dooley
2022-07-07 22:04 ` [RFC 3/4] riscv: arch-topology: move riscv to the generic store_cpu_topology() Conor Dooley
2022-07-07 22:04 ` Conor Dooley [this message]
2022-07-07 22:06 ` [PATCH/RFC 0/4] Fix RISC-V's arch-topology reporting Conor.Dooley
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