From: James Morse <james.morse@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Mark Brown <broonie@kernel.org>, Will Deacon <will@kernel.org>,
James Morse <james.morse@arm.com>
Subject: [PATCH 03/38] arm64/sysreg: Standardise naming for ID_MMFR5_EL1
Date: Fri, 28 Oct 2022 17:53:51 +0100 [thread overview]
Message-ID: <20221028165426.1707896-4-james.morse@arm.com> (raw)
In-Reply-To: <20221028165426.1707896-1-james.morse@arm.com>
To convert the 32bit id registers to use the sysreg generation, they
must first have a regular pattern, to match the symbols the script
generates.
Ensure symbols for the ID_MMFR5_EL1 register have an _EL1 suffix.
No functional change.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/sysreg.h | 2 +-
arch/arm64/kernel/cpufeature.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index f7d003b975c5..7a719c9804fc 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -751,7 +751,7 @@
#define ID_MMFR4_EL1_AC2_SHIFT 4
#define ID_MMFR4_EL1_SpecSEI_SHIFT 0
-#define ID_MMFR5_ETS_SHIFT 0
+#define ID_MMFR5_EL1_ETS_SHIFT 0
#define ID_PFR0_DIT_SHIFT 24
#define ID_PFR0_CSV2_SHIFT 16
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 436ff36242a8..09b53c2fb86e 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -498,7 +498,7 @@ static const struct arm64_ftr_bits ftr_id_isar4[] = {
};
static const struct arm64_ftr_bits ftr_id_mmfr5[] = {
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0),
ARM64_FTR_END,
};
--
2.30.2
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next prev parent reply other threads:[~2022-10-28 17:01 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-28 16:53 [PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
2022-10-28 16:53 ` [PATCH 01/38] arm64/sysreg: Standardise naming for ID_MMFR0_EL1 James Morse
2022-10-28 16:53 ` [PATCH 02/38] arm64/sysreg: Standardise naming for ID_MMFR4_EL1 James Morse
2022-10-28 16:53 ` James Morse [this message]
2022-10-28 16:53 ` [PATCH 04/38] arm64/sysreg: Standardise naming for ID_ISAR0_EL1 James Morse
2022-10-28 16:53 ` [PATCH 05/38] arm64/sysreg: Standardise naming for ID_ISAR4_EL1 James Morse
2022-10-28 16:53 ` [PATCH 06/38] arm64/sysreg: Standardise naming for ID_ISAR5_EL1 James Morse
2022-10-28 16:53 ` [PATCH 07/38] arm64/sysreg: Standardise naming for ID_ISAR6_EL1 James Morse
2022-10-28 16:53 ` [PATCH 08/38] arm64/sysreg: Standardise naming for ID_PFR0_EL1 James Morse
2022-10-28 16:53 ` [PATCH 09/38] arm64/sysreg: Standardise naming for ID_PFR1_EL1 James Morse
2022-10-28 16:53 ` [PATCH 10/38] arm64/sysreg: Standardise naming for ID_PFR2_EL1 James Morse
2022-10-28 16:53 ` [PATCH 11/38] arm64/sysreg: Standardise naming for ID_DFR0_EL1 James Morse
2022-10-28 16:54 ` [PATCH 12/38] arm64/sysreg: Standardise naming for ID_DFR1_EL1 James Morse
2022-10-28 16:54 ` [PATCH 13/38] arm64/sysreg: Standardise naming for MVFR0_EL1 James Morse
2022-10-28 16:54 ` [PATCH 14/38] arm64/sysreg: Standardise naming for MVFR1_EL1 James Morse
2022-10-28 16:54 ` [PATCH 15/38] arm64/sysreg: Standardise naming for MVFR2_EL1 James Morse
2022-10-28 16:54 ` [PATCH 16/38] arm64/sysreg: Extend the maximum width of a register and symbol name James Morse
2022-10-28 16:54 ` [PATCH 17/38] arm64/sysreg: Convert ID_MMFR0_EL1 to automatic generation James Morse
2022-10-28 16:54 ` [PATCH 18/38] arm64/sysreg: Convert ID_MMFR1_EL1 " James Morse
2022-10-28 16:54 ` [PATCH 19/38] arm64/sysreg: Convert ID_MMFR2_EL1 " James Morse
2022-10-28 17:12 ` Mark Brown
2022-10-28 16:54 ` [PATCH 20/38] arm64/sysreg: Convert ID_MMFR3_EL1 " James Morse
2022-10-28 16:54 ` [PATCH 21/38] arm64/sysreg: Convert ID_MMFR4_EL1 " James Morse
2022-10-28 16:54 ` [PATCH 22/38] arm64/sysreg: Convert ID_ISAR0_EL1 " James Morse
2022-10-28 16:54 ` [PATCH 23/38] arm64/sysreg: Convert ID_ISAR1_EL1 " James Morse
2022-10-28 16:54 ` [PATCH 24/38] arm64/sysreg: Convert ID_ISAR2_EL1 " James Morse
2022-10-28 16:54 ` [PATCH 25/38] arm64/sysreg: Convert ID_ISAR3_EL1 " James Morse
2022-10-28 16:54 ` [PATCH 26/38] arm64/sysreg: Convert ID_ISAR4_EL1 " James Morse
2022-10-28 16:54 ` [PATCH 27/38] arm64/sysreg: Convert ID_ISAR5_EL1 " James Morse
2022-10-28 17:14 ` Mark Brown
2022-10-28 16:54 ` [PATCH 28/38] arm64/sysreg: Convert ID_ISAR6_EL1 " James Morse
2022-10-28 16:54 ` [PATCH 29/38] arm64/sysreg: Convert ID_PFR0_EL1 " James Morse
2022-10-28 17:17 ` Mark Brown
2022-11-14 15:02 ` Will Deacon
2022-11-30 17:16 ` James Morse
2022-10-28 16:54 ` [PATCH 30/38] arm64/sysreg: Convert ID_PFR1_EL1 " James Morse
2022-10-28 16:54 ` [PATCH 31/38] arm64/sysreg: Convert ID_PFR2_EL1 " James Morse
2022-10-28 16:54 ` [PATCH 32/38] arm64/sysreg: Convert MVFR0_EL1 " James Morse
2022-10-28 16:54 ` [PATCH 33/38] arm64/sysreg: Convert MVFR1_EL1 " James Morse
2022-10-28 16:54 ` [PATCH 34/38] arm64/sysreg: Convert MVFR2_EL1 " James Morse
2022-10-28 17:19 ` Mark Brown
2022-10-28 16:54 ` [PATCH 35/38] arm64/sysreg: Convert ID_MMFR5_EL1 " James Morse
2022-10-28 16:54 ` [PATCH 36/38] arm64/sysreg: Convert ID_AFR0_EL1 " James Morse
2022-10-28 16:54 ` [PATCH 37/38] arm64/sysreg: Convert ID_DFR0_EL1 " James Morse
2022-10-28 17:22 ` Mark Brown
2022-11-30 17:17 ` James Morse
2022-10-28 16:54 ` [PATCH 38/38] arm64/sysreg: Convert ID_DFR1_EL1 " James Morse
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