* [PATCH 1/8] arm64: dts: ti: k3-j721e-main: Add MCSPI nodes
2023-03-20 5:30 [PATCH 0/8] arm64: dts: ti: j7: Add device-tree nodes for MCSPI Vaishnav Achath
@ 2023-03-20 5:30 ` Vaishnav Achath
2023-03-20 5:30 ` [PATCH 2/8] arm64: dts: ti: k3-j721e-mcu-wakeup: " Vaishnav Achath
` (7 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Vaishnav Achath @ 2023-03-20 5:30 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt
Cc: linux-arm-kernel, devicetree, linux-kernel, j-keerthy, u-kumar1,
vaishnav.a
J721E has 8 MCSPI instances in the main domain. Add the
DT nodes for all the 8 instances and keep them disabled.
Co-developed-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 88 +++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index bfa296dce3a3..a90f076776ce 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -2328,4 +2328,92 @@
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
status = "disabled";
};
+
+ main_spi0: spi@2100000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02100000 0x00 0x400>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 266 1>;
+ status = "disabled";
+ };
+
+ main_spi1: spi@2110000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02110000 0x00 0x400>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 267 1>;
+ status = "disabled";
+ };
+
+ main_spi2: spi@2120000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02120000 0x00 0x400>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 268 1>;
+ status = "disabled";
+ };
+
+ main_spi3: spi@2130000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02130000 0x00 0x400>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 269 1>;
+ status = "disabled";
+ };
+
+ main_spi4: spi@2140000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02140000 0x00 0x400>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 270 1>;
+ status = "disabled";
+ };
+
+ main_spi5: spi@2150000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02150000 0x00 0x400>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 271 1>;
+ status = "disabled";
+ };
+
+ main_spi6: spi@2160000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02160000 0x00 0x400>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 272 1>;
+ status = "disabled";
+ };
+
+ main_spi7: spi@2170000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02170000 0x00 0x400>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 273 1>;
+ status = "disabled";
+ };
};
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 2/8] arm64: dts: ti: k3-j721e-mcu-wakeup: Add MCSPI nodes
2023-03-20 5:30 [PATCH 0/8] arm64: dts: ti: j7: Add device-tree nodes for MCSPI Vaishnav Achath
2023-03-20 5:30 ` [PATCH 1/8] arm64: dts: ti: k3-j721e-main: Add MCSPI nodes Vaishnav Achath
@ 2023-03-20 5:30 ` Vaishnav Achath
2023-03-20 5:30 ` [PATCH 3/8] arm64: dts: ti: k3-j7200-main: " Vaishnav Achath
` (6 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Vaishnav Achath @ 2023-03-20 5:30 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt
Cc: linux-arm-kernel, devicetree, linux-kernel, j-keerthy, u-kumar1,
vaishnav.a
J721E has 3 MCSPI instances in the MCU domain. Add the
DT nodes for all the 3 instances and keep them disabled.
Co-developed-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
---
.../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 33 +++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
index 8ac78034d5d6..24e8125db8c4 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
@@ -425,4 +425,37 @@
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
status = "disabled";
};
+
+ mcu_spi0: spi@40300000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x040300000 0x00 0x400>;
+ interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 274 0>;
+ status = "disabled";
+ };
+
+ mcu_spi1: spi@40310000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x040310000 0x00 0x400>;
+ interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 275 0>;
+ status = "disabled";
+ };
+
+ mcu_spi2: spi@40320000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x040320000 0x00 0x400>;
+ interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 276 0>;
+ status = "disabled";
+ };
};
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 3/8] arm64: dts: ti: k3-j7200-main: Add MCSPI nodes
2023-03-20 5:30 [PATCH 0/8] arm64: dts: ti: j7: Add device-tree nodes for MCSPI Vaishnav Achath
2023-03-20 5:30 ` [PATCH 1/8] arm64: dts: ti: k3-j721e-main: Add MCSPI nodes Vaishnav Achath
2023-03-20 5:30 ` [PATCH 2/8] arm64: dts: ti: k3-j721e-mcu-wakeup: " Vaishnav Achath
@ 2023-03-20 5:30 ` Vaishnav Achath
2023-03-20 5:30 ` [PATCH 4/8] arm64: dts: ti: k3-j7200-mcu-wakeup: " Vaishnav Achath
` (5 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Vaishnav Achath @ 2023-03-20 5:30 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt
Cc: linux-arm-kernel, devicetree, linux-kernel, j-keerthy, u-kumar1,
vaishnav.a
J7200 has 8 MCSPI instances in the main domain. Add the
DT nodes for all the 8 instances and keep them disabled.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 88 +++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 138381f43ce4..e7ede18e75fa 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -777,6 +777,94 @@
clock-names = "gpio";
};
+ main_spi0: spi@2100000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02100000 0x00 0x400>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 266 1>;
+ status = "disabled";
+ };
+
+ main_spi1: spi@2110000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02110000 0x00 0x400>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 267 1>;
+ status = "disabled";
+ };
+
+ main_spi2: spi@2120000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02120000 0x00 0x400>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 268 1>;
+ status = "disabled";
+ };
+
+ main_spi3: spi@2130000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02130000 0x00 0x400>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 269 1>;
+ status = "disabled";
+ };
+
+ main_spi4: spi@2140000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02140000 0x00 0x400>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 270 1>;
+ status = "disabled";
+ };
+
+ main_spi5: spi@2150000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02150000 0x00 0x400>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 271 1>;
+ status = "disabled";
+ };
+
+ main_spi6: spi@2160000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02160000 0x00 0x400>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 272 1>;
+ status = "disabled";
+ };
+
+ main_spi7: spi@2170000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02170000 0x00 0x400>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 273 1>;
+ status = "disabled";
+ };
+
watchdog0: watchdog@2200000 {
compatible = "ti,j7-rti-wdt";
reg = <0x0 0x2200000 0x0 0x100>;
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 4/8] arm64: dts: ti: k3-j7200-mcu-wakeup: Add MCSPI nodes
2023-03-20 5:30 [PATCH 0/8] arm64: dts: ti: j7: Add device-tree nodes for MCSPI Vaishnav Achath
` (2 preceding siblings ...)
2023-03-20 5:30 ` [PATCH 3/8] arm64: dts: ti: k3-j7200-main: " Vaishnav Achath
@ 2023-03-20 5:30 ` Vaishnav Achath
2023-03-20 5:30 ` [PATCH 5/8] arm64: dts: ti: k3-j721s2-main: " Vaishnav Achath
` (4 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Vaishnav Achath @ 2023-03-20 5:30 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt
Cc: linux-arm-kernel, devicetree, linux-kernel, j-keerthy, u-kumar1,
vaishnav.a
J7200 has 3 MCSPI instances in the MCU domain. Add the
DT nodes for all the 3 instances and keep them disabled.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
---
.../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 33 +++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
index de56a0165bd0..331b4e482e41 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
@@ -305,6 +305,39 @@
status = "disabled";
};
+ mcu_spi0: spi@40300000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x040300000 0x00 0x400>;
+ interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 274 0>;
+ status = "disabled";
+ };
+
+ mcu_spi1: spi@40310000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x040310000 0x00 0x400>;
+ interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 275 0>;
+ status = "disabled";
+ };
+
+ mcu_spi2: spi@40320000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x040320000 0x00 0x400>;
+ interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 276 0>;
+ status = "disabled";
+ };
+
fss: syscon@47000000 {
compatible = "syscon", "simple-mfd";
reg = <0x00 0x47000000 0x00 0x100>;
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 5/8] arm64: dts: ti: k3-j721s2-main: Add MCSPI nodes
2023-03-20 5:30 [PATCH 0/8] arm64: dts: ti: j7: Add device-tree nodes for MCSPI Vaishnav Achath
` (3 preceding siblings ...)
2023-03-20 5:30 ` [PATCH 4/8] arm64: dts: ti: k3-j7200-mcu-wakeup: " Vaishnav Achath
@ 2023-03-20 5:30 ` Vaishnav Achath
2023-03-20 5:30 ` [PATCH 6/8] arm64: dts: ti: k3-j721s2-mcu-wakeup: " Vaishnav Achath
` (3 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Vaishnav Achath @ 2023-03-20 5:30 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt
Cc: linux-arm-kernel, devicetree, linux-kernel, j-keerthy, u-kumar1,
vaishnav.a
J721S2 has 8 MCSPI instances in the main domain. Add the
DT nodes for all the 8 instances and keep them disabled.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 88 ++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 8915132efcc1..2dd7865f7654 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -1014,4 +1014,92 @@
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
status = "disabled";
};
+
+ main_spi0: spi@2100000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02100000 0x00 0x400>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 339 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 339 1>;
+ status = "disabled";
+ };
+
+ main_spi1: spi@2110000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02110000 0x00 0x400>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 340 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 340 1>;
+ status = "disabled";
+ };
+
+ main_spi2: spi@2120000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02120000 0x00 0x400>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 341 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 341 1>;
+ status = "disabled";
+ };
+
+ main_spi3: spi@2130000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02130000 0x00 0x400>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 342 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 342 1>;
+ status = "disabled";
+ };
+
+ main_spi4: spi@2140000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02140000 0x00 0x400>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 343 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 343 1>;
+ status = "disabled";
+ };
+
+ main_spi5: spi@2150000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02150000 0x00 0x400>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 344 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 344 1>;
+ status = "disabled";
+ };
+
+ main_spi6: spi@2160000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02160000 0x00 0x400>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 345 1>;
+ status = "disabled";
+ };
+
+ main_spi7: spi@2170000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02170000 0x00 0x400>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 346 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 346 1>;
+ status = "disabled";
+ };
};
--
2.17.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 6/8] arm64: dts: ti: k3-j721s2-mcu-wakeup: Add MCSPI nodes
2023-03-20 5:30 [PATCH 0/8] arm64: dts: ti: j7: Add device-tree nodes for MCSPI Vaishnav Achath
` (4 preceding siblings ...)
2023-03-20 5:30 ` [PATCH 5/8] arm64: dts: ti: k3-j721s2-main: " Vaishnav Achath
@ 2023-03-20 5:30 ` Vaishnav Achath
2023-03-20 5:30 ` [PATCH 7/8] arm64: dts: ti: k3-j784s4-main: " Vaishnav Achath
` (2 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Vaishnav Achath @ 2023-03-20 5:30 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt
Cc: linux-arm-kernel, devicetree, linux-kernel, j-keerthy, u-kumar1,
vaishnav.a
J721S2 has 3 MCSPI instances in the MCU domain. Add the
DT nodes for all the 3 instances and keep them disabled.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
---
.../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 33 +++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
index 0af242aa9816..9e5a8a35a01b 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
@@ -203,6 +203,39 @@
status = "disabled";
};
+ mcu_spi0: spi@40300000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x040300000 0x00 0x400>;
+ interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 347 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 347 0>;
+ status = "disabled";
+ };
+
+ mcu_spi1: spi@40310000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x040310000 0x00 0x400>;
+ interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 348 0>;
+ status = "disabled";
+ };
+
+ mcu_spi2: spi@40320000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x040320000 0x00 0x400>;
+ interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 349 0>;
+ status = "disabled";
+ };
+
mcu_navss: bus@28380000{
compatible = "simple-mfd";
#address-cells = <2>;
--
2.17.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 7/8] arm64: dts: ti: k3-j784s4-main: Add MCSPI nodes
2023-03-20 5:30 [PATCH 0/8] arm64: dts: ti: j7: Add device-tree nodes for MCSPI Vaishnav Achath
` (5 preceding siblings ...)
2023-03-20 5:30 ` [PATCH 6/8] arm64: dts: ti: k3-j721s2-mcu-wakeup: " Vaishnav Achath
@ 2023-03-20 5:30 ` Vaishnav Achath
2023-03-20 5:30 ` [PATCH 8/8] arm64: dts: ti: k3-j784s4-mcu-wakeup: " Vaishnav Achath
2023-03-20 15:16 ` [PATCH 0/8] arm64: dts: ti: j7: Add device-tree nodes for MCSPI Nishanth Menon
8 siblings, 0 replies; 11+ messages in thread
From: Vaishnav Achath @ 2023-03-20 5:30 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt
Cc: linux-arm-kernel, devicetree, linux-kernel, j-keerthy, u-kumar1,
vaishnav.a
J784S4 has 8 MCSPI instances in the main domain. Add the
DT nodes for all the 8 instances and keep them disabled.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
---
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 88 ++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index 80a1b08c51a8..432592ef3bc4 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -1005,4 +1005,92 @@
bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
status = "disabled";
};
+
+ main_spi0: spi@2100000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02100000 0x00 0x400>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 376 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 376 1>;
+ status = "disabled";
+ };
+
+ main_spi1: spi@2110000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02110000 0x00 0x400>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 377 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 377 1>;
+ status = "disabled";
+ };
+
+ main_spi2: spi@2120000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02120000 0x00 0x400>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 378 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 378 1>;
+ status = "disabled";
+ };
+
+ main_spi3: spi@2130000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02130000 0x00 0x400>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 379 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 379 1>;
+ status = "disabled";
+ };
+
+ main_spi4: spi@2140000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02140000 0x00 0x400>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 380 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 380 1>;
+ status = "disabled";
+ };
+
+ main_spi5: spi@2150000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02150000 0x00 0x400>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 381 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 381 1>;
+ status = "disabled";
+ };
+
+ main_spi6: spi@2160000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02160000 0x00 0x400>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 382 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 382 1>;
+ status = "disabled";
+ };
+
+ main_spi7: spi@2170000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x02170000 0x00 0x400>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 383 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 383 1>;
+ status = "disabled";
+ };
};
--
2.17.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 8/8] arm64: dts: ti: k3-j784s4-mcu-wakeup: Add MCSPI nodes
2023-03-20 5:30 [PATCH 0/8] arm64: dts: ti: j7: Add device-tree nodes for MCSPI Vaishnav Achath
` (6 preceding siblings ...)
2023-03-20 5:30 ` [PATCH 7/8] arm64: dts: ti: k3-j784s4-main: " Vaishnav Achath
@ 2023-03-20 5:30 ` Vaishnav Achath
2023-03-20 15:16 ` [PATCH 0/8] arm64: dts: ti: j7: Add device-tree nodes for MCSPI Nishanth Menon
8 siblings, 0 replies; 11+ messages in thread
From: Vaishnav Achath @ 2023-03-20 5:30 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt
Cc: linux-arm-kernel, devicetree, linux-kernel, j-keerthy, u-kumar1,
vaishnav.a
J784S4 has 3 MCSPI instances in the MCU domain. Add the
DT nodes for all the 3 instances and keep them disabled.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
---
.../boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 33 +++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
index 64bd3dee14aa..f04fcb614cbe 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
@@ -204,6 +204,39 @@
status = "disabled";
};
+ mcu_spi0: spi@40300000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x040300000 0x00 0x400>;
+ interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 384 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 384 0>;
+ status = "disabled";
+ };
+
+ mcu_spi1: spi@40310000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x040310000 0x00 0x400>;
+ interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 385 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 385 0>;
+ status = "disabled";
+ };
+
+ mcu_spi2: spi@40320000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x040320000 0x00 0x400>;
+ interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 386 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 386 0>;
+ status = "disabled";
+ };
+
mcu_navss: bus@28380000{
compatible = "simple-bus";
#address-cells = <2>;
--
2.17.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH 0/8] arm64: dts: ti: j7: Add device-tree nodes for MCSPI
2023-03-20 5:30 [PATCH 0/8] arm64: dts: ti: j7: Add device-tree nodes for MCSPI Vaishnav Achath
` (7 preceding siblings ...)
2023-03-20 5:30 ` [PATCH 8/8] arm64: dts: ti: k3-j784s4-mcu-wakeup: " Vaishnav Achath
@ 2023-03-20 15:16 ` Nishanth Menon
2023-03-21 6:59 ` Vaishnav Achath
8 siblings, 1 reply; 11+ messages in thread
From: Nishanth Menon @ 2023-03-20 15:16 UTC (permalink / raw)
To: Vaishnav Achath
Cc: vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt,
linux-arm-kernel, devicetree, linux-kernel, j-keerthy, u-kumar1
On 11:00-20230320, Vaishnav Achath wrote:
> This series adds device tree nodes for Multi Channel Serial Peripheral
> Interface (MCSPI) on J721E, J7200, J721S2 and J784S4 platforms. All the
> MCSPI instances are disabled by default and can be enabled through overlays
> as required, the changes were tested using spidev loopback test for all
> instances and the data verified only for main_spi4 which is connected
> internally as slave to mcu_spi2 for all existing J7 devices.
>
> Vaishnav Achath (8):
> arm64: dts: ti: k3-j721e-main: Add MCSPI nodes
> arm64: dts: ti: k3-j721e-mcu-wakeup: Add MCSPI nodes
> arm64: dts: ti: k3-j7200-main: Add MCSPI nodes
> arm64: dts: ti: k3-j7200-mcu-wakeup: Add MCSPI nodes
> arm64: dts: ti: k3-j721s2-main: Add MCSPI nodes
> arm64: dts: ti: k3-j721s2-mcu-wakeup: Add MCSPI nodes
> arm64: dts: ti: k3-j784s4-main: Add MCSPI nodes
> arm64: dts: ti: k3-j784s4-mcu-wakeup: Add MCSPI nodes
Why split the patches per bus? why not club the patches at SoC level?
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
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^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH 0/8] arm64: dts: ti: j7: Add device-tree nodes for MCSPI
2023-03-20 15:16 ` [PATCH 0/8] arm64: dts: ti: j7: Add device-tree nodes for MCSPI Nishanth Menon
@ 2023-03-21 6:59 ` Vaishnav Achath
0 siblings, 0 replies; 11+ messages in thread
From: Vaishnav Achath @ 2023-03-21 6:59 UTC (permalink / raw)
To: Nishanth Menon
Cc: vigneshr, kristo, robh+dt, krzysztof.kozlowski+dt,
linux-arm-kernel, devicetree, linux-kernel, j-keerthy, u-kumar1
Hi Nishanth,
On 20/03/23 20:46, Nishanth Menon wrote:
> On 11:00-20230320, Vaishnav Achath wrote:
>> This series adds device tree nodes for Multi Channel Serial Peripheral
>> Interface (MCSPI) on J721E, J7200, J721S2 and J784S4 platforms. All the
>> MCSPI instances are disabled by default and can be enabled through overlays
>> as required, the changes were tested using spidev loopback test for all
>> instances and the data verified only for main_spi4 which is connected
>> internally as slave to mcu_spi2 for all existing J7 devices.
>>
>> Vaishnav Achath (8):
>> arm64: dts: ti: k3-j721e-main: Add MCSPI nodes
>> arm64: dts: ti: k3-j721e-mcu-wakeup: Add MCSPI nodes
>> arm64: dts: ti: k3-j7200-main: Add MCSPI nodes
>> arm64: dts: ti: k3-j7200-mcu-wakeup: Add MCSPI nodes
>> arm64: dts: ti: k3-j721s2-main: Add MCSPI nodes
>> arm64: dts: ti: k3-j721s2-mcu-wakeup: Add MCSPI nodes
>> arm64: dts: ti: k3-j784s4-main: Add MCSPI nodes
>> arm64: dts: ti: k3-j784s4-mcu-wakeup: Add MCSPI nodes
>
> Why split the patches per bus? why not club the patches at SoC level?
>
I split them initially since the changes were in two different files, I have
combined the changes at SoC level and send a V2,
https://lore.kernel.org/all/20230321065447.6997-1-vaishnav.a@ti.com/#r
--
Regards,
Vaishnav
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^ permalink raw reply [flat|nested] 11+ messages in thread