* [PATCH v2 1/3] dt-bindings: mtd: Add AC5 specific binding
2023-06-26 3:12 [PATCH v2 0/3] mtd: rawnand: marvell: add support for AC5 SoC Chris Packham
@ 2023-06-26 3:12 ` Chris Packham
2023-06-26 17:18 ` Conor Dooley
2023-06-26 3:12 ` [PATCH v2 2/3] arm64: dts: marvell: Add NAND flash controller to AC5 Chris Packham
2023-06-26 3:12 ` [PATCH v2 3/3] mtd: rawnand: marvell: add support for AC5 SoC Chris Packham
2 siblings, 1 reply; 6+ messages in thread
From: Chris Packham @ 2023-06-26 3:12 UTC (permalink / raw)
To: miquel.raynal, richard, vigneshr, robh+dt, krzysztof.kozlowski+dt,
conor+dt, gregory.clement, pierre.gondois, arnd, f.fainelli
Cc: linux-mtd, devicetree, linux-kernel, linux-arm-kernel,
Chris Packham
Add binding for AC5 SoC. This SoC only supports NAND SDR timings up to
mode 3 so a specific compatible value is needed.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
Notes:
Changes in v2:
- Keep compatibles in alphabetical order
- Explain AC5 limitations in commit message
.../devicetree/bindings/mtd/marvell,nand-controller.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml b/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml
index a10729bb1840..1ecea848e8b9 100644
--- a/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml
+++ b/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml
@@ -16,6 +16,7 @@ properties:
- const: marvell,armada-8k-nand-controller
- const: marvell,armada370-nand-controller
- enum:
+ - marvell,ac5-nand-controller
- marvell,armada370-nand-controller
- marvell,pxa3xx-nand-controller
- description: legacy bindings
--
2.41.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v2 2/3] arm64: dts: marvell: Add NAND flash controller to AC5
2023-06-26 3:12 [PATCH v2 0/3] mtd: rawnand: marvell: add support for AC5 SoC Chris Packham
2023-06-26 3:12 ` [PATCH v2 1/3] dt-bindings: mtd: Add AC5 specific binding Chris Packham
@ 2023-06-26 3:12 ` Chris Packham
2023-06-30 4:06 ` Chris Packham
2023-06-26 3:12 ` [PATCH v2 3/3] mtd: rawnand: marvell: add support for AC5 SoC Chris Packham
2 siblings, 1 reply; 6+ messages in thread
From: Chris Packham @ 2023-06-26 3:12 UTC (permalink / raw)
To: miquel.raynal, richard, vigneshr, robh+dt, krzysztof.kozlowski+dt,
conor+dt, gregory.clement, pierre.gondois, arnd, f.fainelli
Cc: linux-mtd, devicetree, linux-kernel, linux-arm-kernel,
Chris Packham
The AC5/AC5X SoC has a NAND flash controller (NFC). Add this to
the base SoC dtsi file as a disabled node. The NFC integration
on the AC5/AC5X only supports SDR timing modes up to 3 so requires a
dedicated compatible property so this limitation can be enforced.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
Notes:
Changes in v2:
- New.
arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
index 8bce64069138..74d644e0c29e 100644
--- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
@@ -296,6 +296,16 @@ spi1: spi@805a8000 {
status = "disabled";
};
+ nand: nand-controller@805b0000 {
+ compatible = "marvell,ac5-nand-controller";
+ reg = <0x0 0x805b0000 0x0 0x00000054>;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cnm_clock>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@80600000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
--
2.41.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v2 3/3] mtd: rawnand: marvell: add support for AC5 SoC
2023-06-26 3:12 [PATCH v2 0/3] mtd: rawnand: marvell: add support for AC5 SoC Chris Packham
2023-06-26 3:12 ` [PATCH v2 1/3] dt-bindings: mtd: Add AC5 specific binding Chris Packham
2023-06-26 3:12 ` [PATCH v2 2/3] arm64: dts: marvell: Add NAND flash controller to AC5 Chris Packham
@ 2023-06-26 3:12 ` Chris Packham
2 siblings, 0 replies; 6+ messages in thread
From: Chris Packham @ 2023-06-26 3:12 UTC (permalink / raw)
To: miquel.raynal, richard, vigneshr, robh+dt, krzysztof.kozlowski+dt,
conor+dt, gregory.clement, pierre.gondois, arnd, f.fainelli
Cc: linux-mtd, devicetree, linux-kernel, linux-arm-kernel,
Chris Packham
Add support for the AC5/AC5X SoC from Marvell. The NFC on this SoC only
supports SDR modes up to 3.
Marvell's SDK includes some predefined values for the ndtr registers.
These haven't been incorporated as the existing code seems to get good
values based on measurements taken with an oscilloscope.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
Notes:
Changes in v2:
- None
drivers/mtd/nand/raw/Kconfig | 2 +-
drivers/mtd/nand/raw/marvell_nand.c | 16 ++++++++++++++++
2 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index b523354dfb00..0f4cbb497010 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -160,7 +160,7 @@ config MTD_NAND_MARVELL
including:
- PXA3xx processors (NFCv1)
- 32-bit Armada platforms (XP, 37x, 38x, 39x) (NFCv2)
- - 64-bit Aramda platforms (7k, 8k) (NFCv2)
+ - 64-bit Aramda platforms (7k, 8k, ac5) (NFCv2)
config MTD_NAND_SLC_LPC32XX
tristate "NXP LPC32xx SLC NAND controller"
diff --git a/drivers/mtd/nand/raw/marvell_nand.c b/drivers/mtd/nand/raw/marvell_nand.c
index 30c15e4e1cc0..b9a8dd324211 100644
--- a/drivers/mtd/nand/raw/marvell_nand.c
+++ b/drivers/mtd/nand/raw/marvell_nand.c
@@ -375,6 +375,7 @@ static inline struct marvell_nand_chip_sel *to_nand_sel(struct marvell_nand_chip
* BCH error detection and correction algorithm,
* NDCB3 register has been added
* @use_dma: Use dma for data transfers
+ * @max_mode_number: Maximum timing mode supported by the controller
*/
struct marvell_nfc_caps {
unsigned int max_cs_nb;
@@ -383,6 +384,7 @@ struct marvell_nfc_caps {
bool legacy_of_bindings;
bool is_nfcv2;
bool use_dma;
+ unsigned int max_mode_number;
};
/**
@@ -2376,6 +2378,9 @@ static int marvell_nfc_setup_interface(struct nand_chip *chip, int chipnr,
if (IS_ERR(sdr))
return PTR_ERR(sdr);
+ if (nfc->caps->max_mode_number && nfc->caps->max_mode_number < conf->timings.mode)
+ return -EOPNOTSUPP;
+
/*
* SDR timings are given in pico-seconds while NFC timings must be
* expressed in NAND controller clock cycles, which is half of the
@@ -3073,6 +3078,13 @@ static const struct marvell_nfc_caps marvell_armada_8k_nfc_caps = {
.is_nfcv2 = true,
};
+static const struct marvell_nfc_caps marvell_ac5_caps = {
+ .max_cs_nb = 2,
+ .max_rb_nb = 1,
+ .is_nfcv2 = true,
+ .max_mode_number = 3,
+};
+
static const struct marvell_nfc_caps marvell_armada370_nfc_caps = {
.max_cs_nb = 4,
.max_rb_nb = 2,
@@ -3121,6 +3133,10 @@ static const struct of_device_id marvell_nfc_of_ids[] = {
.compatible = "marvell,armada-8k-nand-controller",
.data = &marvell_armada_8k_nfc_caps,
},
+ {
+ .compatible = "marvell,ac5-nand-controller",
+ .data = &marvell_ac5_caps,
+ },
{
.compatible = "marvell,armada370-nand-controller",
.data = &marvell_armada370_nfc_caps,
--
2.41.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 6+ messages in thread