From: Will Deacon <will@kernel.org>
To: Joey Gouly <joey.gouly@arm.com>
Cc: linux-arm-kernel@lists.infradead.org, nd@arm.com,
catalin.marinas@arm.com
Subject: Re: [PATCH v1 1/2] arm64: add HWCAP for FEAT_HBC (hinted conditional branches)
Date: Tue, 1 Aug 2023 16:12:30 +0100 [thread overview]
Message-ID: <20230801151229.GI26253@willie-the-truck> (raw)
In-Reply-To: <20230801100008.3125054-2-joey.gouly@arm.com>
Hey Joey,
On Tue, Aug 01, 2023 at 11:00:07AM +0100, Joey Gouly wrote:
> Add a HWCAP for FEAT_HBC, so that userspace can make a decision on using
> this feature.
>
> Signed-off-by: Joey Gouly <joey.gouly@arm.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
[...]
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index f9d456fe132d..ac764c1dac36 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -222,7 +222,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
> static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
> ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0),
> ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0),
> - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0),
> + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0),
> ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0),
> ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
> FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0),
> @@ -2844,6 +2844,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
> HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES),
> HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT),
> HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS),
> + HWCAP_CAP(ID_AA64ISAR2_EL1, BC, IMP, CAP_HWCAP, KERNEL_HWCAP_HBC),
> #ifdef CONFIG_ARM64_SME
> HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME),
> HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64),
> diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
> index 58622dc85917..98fda8500535 100644
> --- a/arch/arm64/kernel/cpuinfo.c
> +++ b/arch/arm64/kernel/cpuinfo.c
> @@ -126,6 +126,7 @@ static const char *const hwcap_str[] = {
> [KERNEL_HWCAP_SME_B16B16] = "smeb16b16",
> [KERNEL_HWCAP_SME_F16F16] = "smef16f16",
> [KERNEL_HWCAP_MOPS] = "mops",
> + [KERNEL_HWCAP_HBC] = "hbc",
I'm a bit confused from the Arm ARM as to the use of "hbc" vs "bc"... I
don't really mind what we go for, but given this is userspace-visible, have
you run the string past the toolchain folks at all? I guess I'm wary of
what a future extension might look like and whether we'll be stuck with
non-architectural terminology such as "hbc2" to advertise it if we go with
your suggestion here rather than "bc".
Will
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next prev parent reply other threads:[~2023-08-01 15:13 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-01 10:00 [PATCH v1 0/2] HWCAP for FEAT_HBC Joey Gouly
2023-08-01 10:00 ` [PATCH v1 1/2] arm64: add HWCAP for FEAT_HBC (hinted conditional branches) Joey Gouly
2023-08-01 15:12 ` Will Deacon [this message]
2023-08-02 11:54 ` Joey Gouly
2023-08-04 13:19 ` Will Deacon
2023-08-01 10:00 ` [PATCH v1 2/2] selftests/arm64: add HWCAP2_HBC test Joey Gouly
2023-08-01 15:09 ` Will Deacon
2023-08-01 15:26 ` Joey Gouly
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