Re: [PATCH v1 1/2] arm64: add HWCAP for FEAT_HBC (hinted conditional branches)

[Will Deacon <will@kernel.org>]

On Wed, Aug 02, 2023 at 12:54:01PM +0100, Joey Gouly wrote:
> On Tue, Aug 01, 2023 at 04:12:30PM +0100, Will Deacon wrote:
> > Hey Joey,
> > 
> > On Tue, Aug 01, 2023 at 11:00:07AM +0100, Joey Gouly wrote:
> > > Add a HWCAP for FEAT_HBC, so that userspace can make a decision on using
> > > this feature.
> > > 
> > > Signed-off-by: Joey Gouly <joey.gouly@arm.com>
> > > Cc: Catalin Marinas <catalin.marinas@arm.com>
> > > Cc: Will Deacon <will@kernel.org>
> > 
> > [...]
> > 
> > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> > > index f9d456fe132d..ac764c1dac36 100644
> > > --- a/arch/arm64/kernel/cpufeature.c
> > > +++ b/arch/arm64/kernel/cpufeature.c
> > > @@ -222,7 +222,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
> > >  static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
> > >  	ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0),
> > >  	ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0),
> > > -	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0),
> > > +	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0),
> > >  	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0),
> > >  	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
> > >  		       FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0),
> > > @@ -2844,6 +2844,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
> > >  	HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES),
> > >  	HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT),
> > >  	HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS),
> > > +	HWCAP_CAP(ID_AA64ISAR2_EL1, BC, IMP, CAP_HWCAP, KERNEL_HWCAP_HBC),
> > >  #ifdef CONFIG_ARM64_SME
> > >  	HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME),
> > >  	HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64),
> > > diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
> > > index 58622dc85917..98fda8500535 100644
> > > --- a/arch/arm64/kernel/cpuinfo.c
> > > +++ b/arch/arm64/kernel/cpuinfo.c
> > > @@ -126,6 +126,7 @@ static const char *const hwcap_str[] = {
> > >  	[KERNEL_HWCAP_SME_B16B16]	= "smeb16b16",
> > >  	[KERNEL_HWCAP_SME_F16F16]	= "smef16f16",
> > >  	[KERNEL_HWCAP_MOPS]		= "mops",
> > > +	[KERNEL_HWCAP_HBC]		= "hbc",
> > 
> > I'm a bit confused from the Arm ARM as to the use of "hbc" vs "bc"... I
> > don't really mind what we go for, but given this is userspace-visible, have
> > you run the string past the toolchain folks at all? I guess I'm wary of
> > what a future extension might look like and whether we'll be stuck with
> > non-architectural terminology such as "hbc2" to advertise it if we go with
> > your suggestion here rather than "bc".
> 
> I just checked LLVM and binutils, they also call it 'hbc'.
> 
> 	.arch   armv8.7-a+hbc
> 
> https://sourceware.org/git/?p=binutils-gdb.git;a=blob;f=gas/testsuite/gas/aarch64/hbc.s;h=23af6ba8edd662463ae3403e62d94ef838f87fd1;hb=HEAD#l35
> 
> https://github.com/llvm/llvm-project/blob/b31be75ff4d1aed94914d5ef53a903d034d5b6ad/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp#L3600
> 
> So it seems that's the name that has been settled on? If you're fine with
> that, I will send a v2 fixing up the inline asm.

Thanks for checking. If that's what they've gone for, then so be it!

Will

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