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From: Linu Cherian <lcherian@marvell.com>
To: <suzuki.poulose@arm.com>, <mike.leach@linaro.org>,
	<james.clark@arm.com>, <leo.yan@linaro.org>
Cc: <linux-arm-kernel@lists.infradead.org>,
	<coresight@lists.linaro.org>, <linux-kernel@vger.kernel.org>,
	<robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
	<conor+dt@kernel.org>, <devicetree@vger.kernel.org>,
	<sgoutham@marvell.com>, <gcherian@marvell.com>,
	Linu Cherian <lcherian@marvell.com>
Subject: [PATCH 6/7] coresight: tmc: Stop trace capture on FlIn
Date: Fri, 29 Sep 2023 19:07:53 +0530	[thread overview]
Message-ID: <20230929133754.857678-7-lcherian@marvell.com> (raw)
In-Reply-To: <20230929133754.857678-1-lcherian@marvell.com>

Configure TMC ETR and ETF to flush and stop trace capture
on FlIn event. As a side effect, do manual flush only if
auto flush fails.

Signed-off-by: Linu Cherian <lcherian@marvell.com>
---
 drivers/hwtracing/coresight/coresight-tmc-etf.c | 10 ++++++++--
 drivers/hwtracing/coresight/coresight-tmc-etr.c | 10 ++++++++--
 drivers/hwtracing/coresight/coresight-tmc.h     |  3 +++
 3 files changed, 19 insertions(+), 4 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c
index 496b44aad56d..cc73cd1f4d11 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
@@ -34,7 +34,7 @@ static int __tmc_etb_enable_hw(struct tmc_drvdata *drvdata)
 	writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE);
 	writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI |
 		       TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT |
-		       TMC_FFCR_TRIGON_TRIGIN,
+		       TMC_FFCR_TRIGON_TRIGIN | TMC_FFCR_STOP_ON_FLUSH,
 		       drvdata->base + TMC_FFCR);
 
 	writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG);
@@ -613,7 +613,13 @@ static int tmc_panic_sync_etf(struct coresight_device *csdev)
 	if (val != TMC_MODE_CIRCULAR_BUFFER)
 		goto out;
 
-	tmc_flush_and_stop(drvdata);
+	val = readl(drvdata->base + TMC_FFSR);
+	/* Do manual flush and stop only if its not auto-stopped */
+	if (!(val & TMC_FFSR_FT_STOPPED)) {
+		dev_info(&csdev->dev,
+			 "%s: Triggering manual flush\n", __func__);
+		tmc_flush_and_stop(drvdata);
+	}
 
 	/* Sync registers from hardware to metadata region */
 	tmc->sts = csdev_access_relaxed_read32(csa, TMC_STS);
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index c31c71e02833..c84f24333ebc 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -1112,7 +1112,7 @@ static int __tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
 
 	writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI |
 		       TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT |
-		       TMC_FFCR_TRIGON_TRIGIN,
+		       TMC_FFCR_TRIGON_TRIGIN | TMC_FFCR_STOP_ON_FLUSH,
 		       drvdata->base + TMC_FFCR);
 	writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG);
 	tmc_enable_hw(drvdata);
@@ -1843,7 +1843,13 @@ static int tmc_panic_sync_etr(struct coresight_device *csdev)
 	if (!(val & TMC_CTL_CAPT_EN))
 		goto out;
 
-	tmc_flush_and_stop(drvdata);
+	val = readl(drvdata->base + TMC_FFSR);
+	/* Do manual flush and stop only if its not auto-stopped */
+	if (!(val & TMC_FFSR_FT_STOPPED)) {
+		dev_info(&csdev->dev,
+			 "%s: Triggering manual flush\n", __func__);
+		tmc_flush_and_stop(drvdata);
+	}
 
 	/* Sync registers from hardware to metadata region */
 	tmc->size = csdev_access_relaxed_read32(csa, TMC_RSZ);
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index f8b79eaac0bd..0975afca1f95 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -76,6 +76,9 @@
 #define TMC_AXICTL_AXCACHE_OS	(0xf << 2)
 #define TMC_AXICTL_ARCACHE_OS	(0xf << 16)
 
+/* TMC_FFSR - 0x300 */
+#define TMC_FFSR_FT_STOPPED	BIT(1)
+
 /* TMC_FFCR - 0x304 */
 #define TMC_FFCR_FLUSHMAN_BIT	6
 #define TMC_FFCR_EN_FMT		BIT(0)
-- 
2.34.1


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  parent reply	other threads:[~2023-09-29 13:39 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-29 13:37 [PATCH 0/7] Coresight for Kernel panic and watchdog reset Linu Cherian
2023-09-29 13:37 ` [PATCH 1/7] dt-bindings: arm: coresight-tmc: Add "memory-region" property Linu Cherian
2023-09-30 15:28   ` Krzysztof Kozlowski
2023-10-03  4:33     ` [EXT] " Linu Cherian
2023-10-03  6:31       ` Krzysztof Kozlowski
2023-10-06  4:27         ` Linu Cherian
2023-10-06 11:03   ` Mike Leach
2023-10-14 11:36     ` [EXT] " Linu Cherian
2023-10-14 13:25       ` Conor Dooley
2023-10-19  1:12         ` Linu Cherian
2023-11-07 11:07       ` Linu Cherian
2023-09-29 13:37 ` [PATCH 2/7] coresight: tmc-etr: Add support to use reserved trace memory Linu Cherian
2023-10-02 14:28   ` James Clark
2023-10-02 14:41     ` James Clark
2023-10-02 15:03   ` James Clark
2023-10-03  4:34     ` [EXT] " Linu Cherian
2023-09-29 13:37 ` [PATCH 3/7] coresight: core: Add provision for panic callbacks Linu Cherian
2023-09-29 13:37 ` [PATCH 4/7] coresight: tmc: Enable panic sync handling Linu Cherian
2023-09-29 13:37 ` [PATCH 5/7] coresight: tmc: Add support for reading tracedata from previous boot Linu Cherian
2023-10-03 16:43   ` James Clark
2023-10-04 13:48     ` James Clark
2023-10-10 13:23       ` [EXT] " Linu Cherian
2023-11-09  1:08         ` Linu Cherian
2023-11-09 10:15           ` James Clark
2023-09-29 13:37 ` Linu Cherian [this message]
2023-09-29 13:37 ` [PATCH 7/7] coresight: config: Add preloaded configuration Linu Cherian

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