From: Siddharth Vadapalli <s-vadapalli@ti.com>
To: <lpieralisi@kernel.org>, <robh@kernel.org>, <kw@linux.com>,
<bhelgaas@google.com>, <krzysztof.kozlowski+dt@linaro.org>,
<conor+dt@kernel.org>, <vigneshr@ti.com>, <tjoseph@cadence.com>
Cc: <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <r-gunasekaran@ti.com>,
<danishanwar@ti.com>, <srk@ti.com>, <nm@ti.com>,
<s-vadapalli@ti.com>
Subject: [PATCH v13 4/5] PCI: j721e: Add PCIe 4x lane selection support
Date: Tue, 28 Nov 2023 11:14:01 +0530 [thread overview]
Message-ID: <20231128054402.2155183-5-s-vadapalli@ti.com> (raw)
In-Reply-To: <20231128054402.2155183-1-s-vadapalli@ti.com>
From: Matt Ranostay <mranostay@ti.com>
Add support for setting of two-bit field that allows selection of 4x lane
PCIe which was previously limited to only 2x lanes.
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Achal Verma <a-verma1@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
drivers/pci/controller/cadence/pci-j721e.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index 63c758b14314..645597856a1d 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -42,7 +42,6 @@ enum link_status {
};
#define J721E_MODE_RC BIT(7)
-#define LANE_COUNT_MASK BIT(8)
#define LANE_COUNT(n) ((n) << 8)
#define GENERATION_SEL_MASK GENMASK(1, 0)
@@ -52,6 +51,7 @@ struct j721e_pcie {
struct clk *refclk;
u32 mode;
u32 num_lanes;
+ u32 max_lanes;
void __iomem *user_cfg_base;
void __iomem *intd_cfg_base;
u32 linkdown_irq_regfield;
@@ -205,11 +205,15 @@ static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie,
{
struct device *dev = pcie->cdns_pcie->dev;
u32 lanes = pcie->num_lanes;
+ u32 mask = BIT(8);
u32 val = 0;
int ret;
+ if (pcie->max_lanes == 4)
+ mask = GENMASK(9, 8);
+
val = LANE_COUNT(lanes - 1);
- ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val);
+ ret = regmap_update_bits(syscon, offset, mask, val);
if (ret)
dev_err(dev, "failed to set link count\n");
@@ -441,7 +445,9 @@ static int j721e_pcie_probe(struct platform_device *pdev)
dev_warn(dev, "num-lanes property not provided or invalid, setting num-lanes to 1\n");
num_lanes = 1;
}
+
pcie->num_lanes = num_lanes;
+ pcie->max_lanes = data->max_lanes;
if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)))
return -EINVAL;
--
2.34.1
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next prev parent reply other threads:[~2023-11-28 5:45 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-28 5:43 [PATCH v13 0/5] PCI: add 4x lane support for pci-j721e controllers Siddharth Vadapalli
2023-11-28 5:43 ` [PATCH v13 1/5] dt-bindings: PCI: ti,j721e-pci-*: add checks for num-lanes Siddharth Vadapalli
2023-11-28 5:43 ` [PATCH v13 2/5] dt-bindings: PCI: ti,j721e-pci-*: add j784s4-pci-* compatible strings Siddharth Vadapalli
2023-11-28 5:44 ` [PATCH v13 3/5] PCI: j721e: Add per platform maximum lane settings Siddharth Vadapalli
2023-12-05 5:12 ` Ravi Gunasekaran
2023-11-28 5:44 ` Siddharth Vadapalli [this message]
2023-11-28 5:44 ` [PATCH v13 5/5] PCI: j721e: add j784s4 PCIe configuration Siddharth Vadapalli
2023-12-11 8:57 ` [PATCH v13 0/5] PCI: add 4x lane support for pci-j721e controllers Maxime Ripard
2023-12-13 19:13 ` Krzysztof Wilczyński
2023-12-13 19:05 ` Krzysztof Wilczyński
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