From: Conor Dooley <conor@kernel.org>
To: "Ghennadi Procopciuc (OSS)" <ghennadi.procopciuc@oss.nxp.com>
Cc: Chester Lin <chester62515@gmail.com>,
Andreas Farber <afaerber@suse.de>,
Matthias Brugger <mbrugger@suse.com>,
Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, NXP S32 Linux Team <s32@nxp.com>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
NXP Linux Team <linux-imx@nxp.com>,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>,
Ciprian Costea <ciprianmarian.costea@nxp.com>
Subject: Re: [PATCH 1/3] dt-bindings: clock: s32g: add uSDHC clock IDs
Date: Fri, 19 Jan 2024 16:14:12 +0000 [thread overview]
Message-ID: <20240119-cattle-antarctic-432fa8e1c0ef@spud> (raw)
In-Reply-To: <20240119-magnetic-racing-0adf8e5fbd4a@spud>
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On Fri, Jan 19, 2024 at 04:11:37PM +0000, Conor Dooley wrote:
> On Fri, Jan 19, 2024 at 03:02:28PM +0200, Ghennadi Procopciuc (OSS) wrote:
> > From: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
> >
> > Add the SCMI clock IDs for the uSDHC controller present on
> > S32G SoCs.
> >
> > Signed-off-by: Ciprian Costea <ciprianmarian.costea@nxp.com>
> > Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
> > ---
> > include/dt-bindings/clock/s32g-scmi-clock.h | 14 ++++++++++++++
> > 1 file changed, 14 insertions(+)
> > create mode 100644 include/dt-bindings/clock/s32g-scmi-clock.h
> >
> > diff --git a/include/dt-bindings/clock/s32g-scmi-clock.h b/include/dt-bindings/clock/s32g-scmi-clock.h
> > new file mode 100644
> > index 000000000000..739f98a924c3
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/s32g-scmi-clock.h
> > @@ -0,0 +1,14 @@
> > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
> > +/*
> > + * Copyright 2020-2024 NXP
> > + */
> > +#ifndef _DT_BINDINGS_SCMI_CLK_S32G_H
> > +#define _DT_BINDINGS_SCMI_CLK_S32G_H
> > +
> > +/* uSDHC */
> > +#define S32G_SCMI_CLK_USDHC_AHB 31
> > +#define S32G_SCMI_CLK_USDHC_MODULE 32
> > +#define S32G_SCMI_CLK_USDHC_CORE 33
> > +#define S32G_SCMI_CLK_USDHC_MOD32K 34
>
> Why do these numbers not start at 0?
Ah, because these are the SCMI IDs directly. If these are numbers that
are in the TRM, just use the numbers directly - there's no need to
create bindings for that.
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next prev parent reply other threads:[~2024-01-19 16:15 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-19 13:02 [PATCH 0/3] add uSDHC and SCMI nodes to the S32G2 SoC Ghennadi Procopciuc (OSS)
2024-01-19 13:02 ` [PATCH 1/3] dt-bindings: clock: s32g: add uSDHC clock IDs Ghennadi Procopciuc (OSS)
2024-01-19 16:11 ` Conor Dooley
2024-01-19 16:14 ` Conor Dooley [this message]
2024-01-19 21:25 ` Ghennadi Procopciuc
2024-01-21 13:32 ` Conor Dooley
2024-01-22 10:09 ` Ghennadi Procopciuc
2024-02-05 6:34 ` Ghennadi Procopciuc
2024-01-19 13:02 ` [PATCH 2/3] arm64: dts: s32g: add SCMI firmware node Ghennadi Procopciuc (OSS)
2024-01-19 13:02 ` [PATCH 3/3] arm64: dts: s32g: add uSDHC node Ghennadi Procopciuc (OSS)
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