[PATCH v1 0/2] Patches for rockchip clk input / output switch

[PATCH v1 0/2] Patches for rockchip clk input / output switch

[Sugar Zhang]

These patches add support for rockchip clk input / output switch.


Sugar Zhang (2):
  clk: rockchip: Add support for clk input / output switch
  dt-bindings: clock: rockchip: Add support for clk input / output
    switch

 .../bindings/clock/rockchip,clk-out.yaml           | 107 +++++++++++++++++++++
 drivers/clk/rockchip/Kconfig                       |   6 ++
 drivers/clk/rockchip/Makefile                      |   2 +
 drivers/clk/rockchip/clk-out.c                     |  99 +++++++++++++++++++
 4 files changed, 214 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/rockchip,clk-out.yaml
 create mode 100644 drivers/clk/rockchip/clk-out.c

-- 
2.7.4


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[PATCH v1 1/2] clk: rockchip: Add support for clk input / output switch

[Sugar Zhang]

This patch add support switch for clk-bidirection which located
at GRF, such as SAIx_MCLK_{IN OUT} which share the same pin.
and these config maybe located in many pieces of GRF,
which hard to addressed in one single clk driver. so, we add
this simple helper driver to address this situation.

In order to simplify implement and usage, and also for safety
clk usage (avoid high freq glitch), we set all clk out as disabled
(which means Input default for clk-bidrection) in the pre-stage,
such boot-loader or init by HW default. And then set a safety freq
before enable clk-out, such as "assign-clock-rates" or clk_set_rate
in drivers.

e.g.

1. mclk{out,in}_sai0 define:

  mclkin_sai0: mclkin-sai0 {
      compatible = "fixed-clock";
      #clock-cells = <0>;
      clock-frequency = <12288000>;
      clock-output-names = "mclk_sai0_from_io";
  };

  mclkout_sai0: mclkout-sai0@ff040070 {
      compatible = "rockchip,clk-out";
      reg = <0 0xff040070 0 0x4>;
      clocks = <&cru MCLK_SAI0_OUT2IO>;
      #clock-cells = <0>;
      clock-output-names = "mclk_sai0_to_io";
      rockchip,bit-shift = <4>;
      //example with PD if reg access needed
      power-domains = <&power RK3562_PD_VO>;
  };

Note:

clock-output-names of mclkin_sai0 should equal to strings in drivers. such as:

drivers/clk/rockchip/clk-rk3562.c:
PNAME(clk_sai0_p) = { "clk_sai0_src", "clk_sai0_frac", "xin_osc0_half", "mclk_sai0_from_io" };

2. mclkout_sai0 usage:

  &ext_codec {
      clocks = <&mclkout_sai0>;
      clock-names = "mclk";
      assigned-clocks = <&mclkout_sai0>;
      assigned-clock-rates = <12288000>;
      pinctrl-names = "default";
      pinctrl-0 = <&i2s0m0_mclk>;
  };

  clk_summary on sai0 work:

  cat /sys/kernel/debug/clk/clk_summary | egrep "pll|sai0"

  clk_sai0_src                1        1        0  1188000000          0     0  50000
    clk_sai0_frac             1        1        0    12288000          0     0  50000
      clk_sai0                1        1        0    12288000          0     0  50000
        mclk_sai0             1        1        0    12288000          0     0  50000
          mclk_sai0_out2io    1        1        0    12288000          0     0  50000
            mclk_sai0_to_io   1        1        0    12288000          0     0  50000

  example with PD if reg access needed:

  * PD status when mclk_sai0_to_io on:

  cat /sys/kernel/debug/pm_genpd/pm_genpd_summary

  domain                          status          children
    /device                                                runtime status
  ----------------------------------------------------------------------
  ...

  vo                              on
    /devices/platform/clocks/ff040070.mclkout-sai0         active
  ...

  * PD status when mclk_sai0_to_io off:

  cat /sys/kernel/debug/pm_genpd/pm_genpd_summary

  domain                          status          children
    /device                                                runtime status
  ----------------------------------------------------------------------
  ...

  vo                              off-0
    /devices/platform/clocks/ff040070.mclkout-sai0         suspended
  ...

3. mclkin_sai0 usage:

  please override freq of mclkin as the real external clkin, such as:

  &mclkin_sai0 {
      clock-frequency = <24576000>;
  }

  &ext_codec {
      clocks = <&mclkin_sai0>;
      clock-names = "mclk";
      assigned-clocks = <&cru CLK_SAI0>;
      assigned-clock-parents = <&mclkin_sai0>;
      pinctrl-names = "default";
      pinctrl-0 = <&i2s0m0_mclk>;
  };

  clk_summary on sai0 work:

  cat /sys/kernel/debug/clk/clk_summary | egrep "pll|sai0"

  mclk_sai0_from_io          1        1        0    12288000          0     0  50000
    clk_sai0                 1        1        0    12288000          0     0  50000
      mclk_sai0              1        1        0    12288000          0     0  50000
        mclk_sai0_out2io     0        0        0    12288000          0     0  50000
          mclk_sai0_to_io    0        0        0    12288000          0     0  50000

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
---

 drivers/clk/rockchip/Kconfig   |  6 +++
 drivers/clk/rockchip/Makefile  |  2 +
 drivers/clk/rockchip/clk-out.c | 99 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 107 insertions(+)
 create mode 100644 drivers/clk/rockchip/clk-out.c

diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig
index 9aad869..0e7eee8 100644
--- a/drivers/clk/rockchip/Kconfig
+++ b/drivers/clk/rockchip/Kconfig
@@ -107,4 +107,10 @@ config CLK_RK3588
 	help
 	  Build the driver for RK3588 Clock Driver.
 
+config ROCKCHIP_CLK_OUT
+	tristate "Rockchip Clk Out / Input Switch"
+	default y
+	help
+	  Say y here to enable clk out / input switch.
+
 endif
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 36894f6..30d6060 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -29,3 +29,5 @@ obj-$(CONFIG_CLK_RK3368)        += clk-rk3368.o
 obj-$(CONFIG_CLK_RK3399)        += clk-rk3399.o
 obj-$(CONFIG_CLK_RK3568)	+= clk-rk3568.o
 obj-$(CONFIG_CLK_RK3588)	+= clk-rk3588.o rst-rk3588.o
+
+obj-$(CONFIG_ROCKCHIP_CLK_OUT)  += clk-out.o
diff --git a/drivers/clk/rockchip/clk-out.c b/drivers/clk/rockchip/clk-out.c
new file mode 100644
index 0000000..22dcd98
--- /dev/null
+++ b/drivers/clk/rockchip/clk-out.c
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+
+static DEFINE_SPINLOCK(clk_out_lock);
+
+static int rockchip_clk_out_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *node = pdev->dev.of_node;
+	struct clk_hw *hw;
+	struct resource *res;
+	const char *clk_name = node->name;
+	const char *parent_name;
+	void __iomem *reg;
+	u32 shift = 0;
+	u8 clk_gate_flags = CLK_GATE_HIWORD_MASK;
+	int ret;
+
+	ret = device_property_read_string(dev, "clock-output-names", &clk_name);
+	if (ret)
+		return ret;
+
+	ret = device_property_read_u32(dev, "rockchip,bit-shift", &shift);
+	if (ret)
+		return ret;
+
+	if (device_property_read_bool(dev, "rockchip,bit-set-to-disable"))
+		clk_gate_flags |= CLK_GATE_SET_TO_DISABLE;
+
+	ret = of_clk_parent_fill(node, &parent_name, 1);
+	if (ret != 1)
+		return -EINVAL;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENOMEM;
+
+	reg = devm_ioremap(dev, res->start, resource_size(res));
+	if (!reg)
+		return -ENOMEM;
+
+	pm_runtime_enable(dev);
+
+	hw = clk_hw_register_gate(dev, clk_name, parent_name, CLK_SET_RATE_PARENT,
+				  reg, shift, clk_gate_flags, &clk_out_lock);
+	if (IS_ERR(hw)) {
+		ret = -EINVAL;
+		goto err_disable_pm_runtime;
+	}
+
+	of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
+
+	return 0;
+
+err_disable_pm_runtime:
+	pm_runtime_disable(dev);
+
+	return ret;
+}
+
+static int rockchip_clk_out_remove(struct platform_device *pdev)
+{
+	struct device_node *node = pdev->dev.of_node;
+
+	of_clk_del_provider(node);
+	pm_runtime_disable(&pdev->dev);
+
+	return 0;
+}
+
+static const struct of_device_id rockchip_clk_out_match[] = {
+	{ .compatible = "rockchip,clk-out", },
+	{},
+};
+
+static struct platform_driver rockchip_clk_out_driver = {
+	.driver = {
+		.name = "rockchip-clk-out",
+		.of_match_table = rockchip_clk_out_match,
+	},
+	.probe = rockchip_clk_out_probe,
+	.remove = rockchip_clk_out_remove,
+};
+
+module_platform_driver(rockchip_clk_out_driver);
+
+MODULE_DESCRIPTION("Rockchip Clock Input-Output-Switch");
+MODULE_AUTHOR("Sugar Zhang <sugar.zhang@rock-chips.com>");
+MODULE_LICENSE("GPL");
+MODULE_DEVICE_TABLE(of, rockchip_clk_out_match);
-- 
2.7.4


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[PATCH v1 2/2] dt-bindings: clock: rockchip: Add support for clk input / output switch

[Sugar Zhang]

This patch add support switch for clk-bidirection which located
at GRF, such as SAIx_MCLK_{IN OUT} which share the same pin.
and these config maybe located in many pieces of GRF,
which hard to addressed in one single clk driver. so, we add
this simple helper driver to address this situation.

In order to simplify implement and usage, and also for safety
clk usage (avoid high freq glitch), we set all clk out as disabled
(which means Input default for clk-bidrection) in the pre-stage,
such boot-loader or init by HW default. And then set a safety freq
before enable clk-out, such as "assign-clock-rates" or clk_set_rate
in drivers.

e.g.

1. mclk{out,in}_sai0 define:

  mclkin_sai0: mclkin-sai0 {
      compatible = "fixed-clock";
      #clock-cells = <0>;
      clock-frequency = <12288000>;
      clock-output-names = "mclk_sai0_from_io";
  };

  mclkout_sai0: mclkout-sai0@ff040070 {
      compatible = "rockchip,clk-out";
      reg = <0 0xff040070 0 0x4>;
      clocks = <&cru MCLK_SAI0_OUT2IO>;
      #clock-cells = <0>;
      clock-output-names = "mclk_sai0_to_io";
      rockchip,bit-shift = <4>;
      //example with PD if reg access needed
      power-domains = <&power RK3562_PD_VO>;
  };

Note:

clock-output-names of mclkin_sai0 should equal to strings in drivers. such as:

drivers/clk/rockchip/clk-rk3562.c:
PNAME(clk_sai0_p) = { "clk_sai0_src", "clk_sai0_frac", "xin_osc0_half", "mclk_sai0_from_io" };

2. mclkout_sai0 usage:

  &ext_codec {
      clocks = <&mclkout_sai0>;
      clock-names = "mclk";
      assigned-clocks = <&mclkout_sai0>;
      assigned-clock-rates = <12288000>;
      pinctrl-names = "default";
      pinctrl-0 = <&i2s0m0_mclk>;
  };

  clk_summary on sai0 work:

  cat /sys/kernel/debug/clk/clk_summary | egrep "pll|sai0"

  clk_sai0_src                1        1        0  1188000000          0     0  50000
    clk_sai0_frac             1        1        0    12288000          0     0  50000
      clk_sai0                1        1        0    12288000          0     0  50000
        mclk_sai0             1        1        0    12288000          0     0  50000
          mclk_sai0_out2io    1        1        0    12288000          0     0  50000
            mclk_sai0_to_io   1        1        0    12288000          0     0  50000

  example with PD if reg access needed:

  * PD status when mclk_sai0_to_io on:

  cat /sys/kernel/debug/pm_genpd/pm_genpd_summary

  domain                          status          children
    /device                                                runtime status
  ----------------------------------------------------------------------
  ...

  vo                              on
    /devices/platform/clocks/ff040070.mclkout-sai0         active
  ...

  * PD status when mclk_sai0_to_io off:

  cat /sys/kernel/debug/pm_genpd/pm_genpd_summary

  domain                          status          children
    /device                                                runtime status
  ----------------------------------------------------------------------
  ...

  vo                              off-0
    /devices/platform/clocks/ff040070.mclkout-sai0         suspended
  ...

3. mclkin_sai0 usage:

  please override freq of mclkin as the real external clkin, such as:

  &mclkin_sai0 {
      clock-frequency = <24576000>;
  }

  &ext_codec {
      clocks = <&mclkin_sai0>;
      clock-names = "mclk";
      assigned-clocks = <&cru CLK_SAI0>;
      assigned-clock-parents = <&mclkin_sai0>;
      pinctrl-names = "default";
      pinctrl-0 = <&i2s0m0_mclk>;
  };

  clk_summary on sai0 work:

  cat /sys/kernel/debug/clk/clk_summary | egrep "pll|sai0"

  mclk_sai0_from_io          1        1        0    12288000          0     0  50000
    clk_sai0                 1        1        0    12288000          0     0  50000
      mclk_sai0              1        1        0    12288000          0     0  50000
        mclk_sai0_out2io     0        0        0    12288000          0     0  50000
          mclk_sai0_to_io    0        0        0    12288000          0     0  50000

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
---

 .../bindings/clock/rockchip,clk-out.yaml           | 107 +++++++++++++++++++++
 1 file changed, 107 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/rockchip,clk-out.yaml

diff --git a/Documentation/devicetree/bindings/clock/rockchip,clk-out.yaml b/Documentation/devicetree/bindings/clock/rockchip,clk-out.yaml
new file mode 100644
index 0000000..6582605
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,clk-out.yaml
@@ -0,0 +1,107 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,clk-out.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip Clock Out Control Module Binding
+
+maintainers:
+  - Sugar Zhang <sugar.zhang@rock-chips.com>
+
+description: |
+  This add support switch for clk-bidirection which located
+  at GRF, such as SAIx_MCLK_{IN OUT} which share the same pin.
+  and these config maybe located in many pieces of GRF,
+  which hard to addressed in one single clk driver. so, we add
+  this simple helper driver to address this situation.
+
+  In order to simplify implement and usage, and also for safety
+  clk usage (avoid high freq glitch), we set all clk out as disabled
+  (which means Input default for clk-bidrection) in the pre-stage,
+  such boot-loader or init by HW default. And then set a safety freq
+  before enable clk-out, such as "assign-clock-rates" or clk_set_rate
+  in drivers.
+
+properties:
+  compatible:
+    enum:
+      - rockchip,clk-out
+
+  reg:
+    maxItems: 1
+
+  "#clock-cells":
+    const: 1
+
+  clocks:
+    maxItems: 1
+    description: parent clocks.
+
+  power-domains:
+    maxItems: 1
+
+  clock-output-names:
+    maxItems: 1
+
+  rockchip,bit-shift:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: Defines the bit shift of clk out enable.
+
+  rockchip,bit-set-to-disable:
+    type: boolean
+    description: |
+      By default this clock sets the bit at bit-shift to enable the clock.
+      Setting this property does the opposite: setting the bit disable
+      the clock and clearing it enables the clock.
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - "#clock-cells"
+  - clock-output-names
+  - rockchip,bit-shift
+
+additionalProperties: false
+
+examples:
+  # Clock Provider node:
+  - |
+    mclkin_sai0: mclkin-sai0 {
+        compatible = "fixed-clock";
+        #clock-cells = <0>;
+        clock-frequency = <12288000>;
+        clock-output-names = "mclk_sai0_from_io";
+    };
+
+    mclkout_sai0: mclkout-sai0@ff040070 {
+        compatible = "rockchip,clk-out";
+        reg = <0 0xff040070 0 0x4>;
+        clocks = <&cru MCLK_SAI0_OUT2IO>;
+        #clock-cells = <0>;
+        clock-output-names = "mclk_sai0_to_io";
+        rockchip,bit-shift = <4>;
+    };
+
+  # Clock mclkout Consumer node:
+  - |
+    ext_codec {
+        clocks = <&mclkout_sai0>;
+        clock-names = "mclk";
+        assigned-clocks = <&mclkout_sai0>;
+        assigned-clock-rates = <12288000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2s0m0_mclk>;
+    };
+
+  # Clock mclkin Consumer node:
+  - |
+    ext_codec {
+        clocks = <&mclkin_sai0>;
+        clock-names = "mclk";
+        assigned-clocks = <&cru CLK_SAI0>;
+        assigned-clock-parents = <&mclkin_sai0>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2s0m0_mclk>;
+    };
-- 
2.7.4


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Re: [PATCH v1 2/2] dt-bindings: clock: rockchip: Add support for clk input / output switch

[Rob Herring]

On Mon, 25 Mar 2024 12:16:30 +0800, Sugar Zhang wrote:
> This patch add support switch for clk-bidirection which located
> at GRF, such as SAIx_MCLK_{IN OUT} which share the same pin.
> and these config maybe located in many pieces of GRF,
> which hard to addressed in one single clk driver. so, we add
> this simple helper driver to address this situation.
> 
> In order to simplify implement and usage, and also for safety
> clk usage (avoid high freq glitch), we set all clk out as disabled
> (which means Input default for clk-bidrection) in the pre-stage,
> such boot-loader or init by HW default. And then set a safety freq
> before enable clk-out, such as "assign-clock-rates" or clk_set_rate
> in drivers.
> 
> e.g.
> 
> 1. mclk{out,in}_sai0 define:
> 
>   mclkin_sai0: mclkin-sai0 {
>       compatible = "fixed-clock";
>       #clock-cells = <0>;
>       clock-frequency = <12288000>;
>       clock-output-names = "mclk_sai0_from_io";
>   };
> 
>   mclkout_sai0: mclkout-sai0@ff040070 {
>       compatible = "rockchip,clk-out";
>       reg = <0 0xff040070 0 0x4>;
>       clocks = <&cru MCLK_SAI0_OUT2IO>;
>       #clock-cells = <0>;
>       clock-output-names = "mclk_sai0_to_io";
>       rockchip,bit-shift = <4>;
>       //example with PD if reg access needed
>       power-domains = <&power RK3562_PD_VO>;
>   };
> 
> Note:
> 
> clock-output-names of mclkin_sai0 should equal to strings in drivers. such as:
> 
> drivers/clk/rockchip/clk-rk3562.c:
> PNAME(clk_sai0_p) = { "clk_sai0_src", "clk_sai0_frac", "xin_osc0_half", "mclk_sai0_from_io" };
> 
> 2. mclkout_sai0 usage:
> 
>   &ext_codec {
>       clocks = <&mclkout_sai0>;
>       clock-names = "mclk";
>       assigned-clocks = <&mclkout_sai0>;
>       assigned-clock-rates = <12288000>;
>       pinctrl-names = "default";
>       pinctrl-0 = <&i2s0m0_mclk>;
>   };
> 
>   clk_summary on sai0 work:
> 
>   cat /sys/kernel/debug/clk/clk_summary | egrep "pll|sai0"
> 
>   clk_sai0_src                1        1        0  1188000000          0     0  50000
>     clk_sai0_frac             1        1        0    12288000          0     0  50000
>       clk_sai0                1        1        0    12288000          0     0  50000
>         mclk_sai0             1        1        0    12288000          0     0  50000
>           mclk_sai0_out2io    1        1        0    12288000          0     0  50000
>             mclk_sai0_to_io   1        1        0    12288000          0     0  50000
> 
>   example with PD if reg access needed:
> 
>   * PD status when mclk_sai0_to_io on:
> 
>   cat /sys/kernel/debug/pm_genpd/pm_genpd_summary
> 
>   domain                          status          children
>     /device                                                runtime status
>   ----------------------------------------------------------------------
>   ...
> 
>   vo                              on
>     /devices/platform/clocks/ff040070.mclkout-sai0         active
>   ...
> 
>   * PD status when mclk_sai0_to_io off:
> 
>   cat /sys/kernel/debug/pm_genpd/pm_genpd_summary
> 
>   domain                          status          children
>     /device                                                runtime status
>   ----------------------------------------------------------------------
>   ...
> 
>   vo                              off-0
>     /devices/platform/clocks/ff040070.mclkout-sai0         suspended
>   ...
> 
> 3. mclkin_sai0 usage:
> 
>   please override freq of mclkin as the real external clkin, such as:
> 
>   &mclkin_sai0 {
>       clock-frequency = <24576000>;
>   }
> 
>   &ext_codec {
>       clocks = <&mclkin_sai0>;
>       clock-names = "mclk";
>       assigned-clocks = <&cru CLK_SAI0>;
>       assigned-clock-parents = <&mclkin_sai0>;
>       pinctrl-names = "default";
>       pinctrl-0 = <&i2s0m0_mclk>;
>   };
> 
>   clk_summary on sai0 work:
> 
>   cat /sys/kernel/debug/clk/clk_summary | egrep "pll|sai0"
> 
>   mclk_sai0_from_io          1        1        0    12288000          0     0  50000
>     clk_sai0                 1        1        0    12288000          0     0  50000
>       mclk_sai0              1        1        0    12288000          0     0  50000
>         mclk_sai0_out2io     0        0        0    12288000          0     0  50000
>           mclk_sai0_to_io    0        0        0    12288000          0     0  50000
> 
> Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
> ---
> 
>  .../bindings/clock/rockchip,clk-out.yaml           | 107 +++++++++++++++++++++
>  1 file changed, 107 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/rockchip,clk-out.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/rockchip,clk-out.yaml: title: 'Rockchip Clock Out Control Module Binding' should not be valid under {'pattern': '([Bb]inding| [Ss]chema)'}
	hint: Everything is a binding/schema, no need to say it. Describe what hardware the binding is for.
	from schema $id: http://devicetree.org/meta-schemas/base.yaml#
Error: Documentation/devicetree/bindings/clock/rockchip,clk-out.example.dts:28.28-29 syntax error
FATAL ERROR: Unable to parse input tree
make[2]: *** [scripts/Makefile.lib:427: Documentation/devicetree/bindings/clock/rockchip,clk-out.example.dtb] Error 1
make[2]: *** Waiting for unfinished jobs....
make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1430: dt_binding_check] Error 2
make: *** [Makefile:240: __sub-make] Error 2

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/1711340191-69588-2-git-send-email-sugar.zhang@rock-chips.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.


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Re: [PATCH v1 2/2] dt-bindings: clock: rockchip: Add support for clk input / output switch

[kernel test robot]

Hi Sugar,

kernel test robot noticed the following build warnings:

[auto build test WARNING on rockchip/for-next]
[also build test WARNING on linus/master v6.9-rc1 next-20240325]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Sugar-Zhang/clk-rockchip-Add-support-for-clk-input-output-switch/20240325-212211
base:   https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git for-next
patch link:    https://lore.kernel.org/r/1711340191-69588-2-git-send-email-sugar.zhang%40rock-chips.com
patch subject: [PATCH v1 2/2] dt-bindings: clock: rockchip: Add support for clk input / output switch
compiler: loongarch64-linux-gcc (GCC) 13.2.0
reproduce: (https://download.01.org/0day-ci/archive/20240326/202403261442.9P6rk3Wk-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202403261442.9P6rk3Wk-lkp@intel.com/

dtcheck warnings: (new ones prefixed by >>)
>> Documentation/devicetree/bindings/clock/rockchip,clk-out.yaml: title: 'Rockchip Clock Out Control Module Binding' should not be valid under {'pattern': '([Bb]inding| [Ss]chema)'}
   	hint: Everything is a binding/schema, no need to say it. Describe what hardware the binding is for.
   	from schema $id: http://devicetree.org/meta-schemas/base.yaml#

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

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Re: [PATCH v1 2/2] dt-bindings: clock: rockchip: Add support for clk input / output switch

[Krzysztof Kozlowski]

On 25/03/2024 05:16, Sugar Zhang wrote:
> This patch add support switch for clk-bidirection which located

Please do not use "This commit/patch/change", but imperative mood. See
longer explanation here:
https://elixir.bootlin.com/linux/v5.17.1/source/Documentation/process/submitting-patches.rst#L95

> at GRF, such as SAIx_MCLK_{IN OUT} which share the same pin.
> and these config maybe located in many pieces of GRF,
> which hard to addressed in one single clk driver. so, we add
> this simple helper driver to address this situation.
> 
> In order to simplify implement and usage, and also for safety
> clk usage (avoid high freq glitch), we set all clk out as disabled
> (which means Input default for clk-bidrection) in the pre-stage,
> such boot-loader or init by HW default. And then set a safety freq
> before enable clk-out, such as "assign-clock-rates" or clk_set_rate
> in drivers.
> 
> e.g.
> 
> 1. mclk{out,in}_sai0 define:
> 
>   mclkin_sai0: mclkin-sai0 {
>       compatible = "fixed-clock";
>       #clock-cells = <0>;
>       clock-frequency = <12288000>;
>       clock-output-names = "mclk_sai0_from_io";
>   };
> 
>   mclkout_sai0: mclkout-sai0@ff040070 {
>       compatible = "rockchip,clk-out";
>       reg = <0 0xff040070 0 0x4>;
>       clocks = <&cru MCLK_SAI0_OUT2IO>;
>       #clock-cells = <0>;
>       clock-output-names = "mclk_sai0_to_io";
>       rockchip,bit-shift = <4>;
>       //example with PD if reg access needed
>       power-domains = <&power RK3562_PD_VO>;
>   };
> 
> Note:
> 
> clock-output-names of mclkin_sai0 should equal to strings in drivers. such as:
> 
> drivers/clk/rockchip/clk-rk3562.c:
> PNAME(clk_sai0_p) = { "clk_sai0_src", "clk_sai0_frac", "xin_osc0_half", "mclk_sai0_from_io" };
> 
> 2. mclkout_sai0 usage:
> 
>   &ext_codec {
>       clocks = <&mclkout_sai0>;
>       clock-names = "mclk";
>       assigned-clocks = <&mclkout_sai0>;
>       assigned-clock-rates = <12288000>;
>       pinctrl-names = "default";
>       pinctrl-0 = <&i2s0m0_mclk>;
>   };
> 
>   clk_summary on sai0 work:
> 
>   cat /sys/kernel/debug/clk/clk_summary | egrep "pll|sai0"
> 
>   clk_sai0_src                1        1        0  1188000000          0     0  50000
>     clk_sai0_frac             1        1        0    12288000          0     0  50000
>       clk_sai0                1        1        0    12288000          0     0  50000
>         mclk_sai0             1        1        0    12288000          0     0  50000
>           mclk_sai0_out2io    1        1        0    12288000          0     0  50000
>             mclk_sai0_to_io   1        1        0    12288000          0     0  50000
> 
>   example with PD if reg access needed:
> 
>   * PD status when mclk_sai0_to_io on:
> 
>   cat /sys/kernel/debug/pm_genpd/pm_genpd_summary
> 
>   domain                          status          children
>     /device                                                runtime status
>   ----------------------------------------------------------------------
>   ...
> 
>   vo                              on
>     /devices/platform/clocks/ff040070.mclkout-sai0         active
>   ...
> 
>   * PD status when mclk_sai0_to_io off:
> 
>   cat /sys/kernel/debug/pm_genpd/pm_genpd_summary
> 
>   domain                          status          children
>     /device                                                runtime status
>   ----------------------------------------------------------------------
>   ...
> 
>   vo                              off-0
>     /devices/platform/clocks/ff040070.mclkout-sai0         suspended
>   ...
> 
> 3. mclkin_sai0 usage:
> 
>   please override freq of mclkin as the real external clkin, such as:
> 
>   &mclkin_sai0 {
>       clock-frequency = <24576000>;
>   }
> 
>   &ext_codec {
>       clocks = <&mclkin_sai0>;
>       clock-names = "mclk";
>       assigned-clocks = <&cru CLK_SAI0>;
>       assigned-clock-parents = <&mclkin_sai0>;
>       pinctrl-names = "default";
>       pinctrl-0 = <&i2s0m0_mclk>;
>   };
> 
>   clk_summary on sai0 work:
> 
>   cat /sys/kernel/debug/clk/clk_summary | egrep "pll|sai0"
> 
>   mclk_sai0_from_io          1        1        0    12288000          0     0  50000
>     clk_sai0                 1        1        0    12288000          0     0  50000
>       mclk_sai0              1        1        0    12288000          0     0  50000
>         mclk_sai0_out2io     0        0        0    12288000          0     0  50000
>           mclk_sai0_to_io    0        0        0    12288000          0     0  50000

None of this long commit msg is a description of hardware. Please remove
all unnecessary information and instead describe the problem you are
solving or the hardware.

> 
> Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
> ---
> 
>  .../bindings/clock/rockchip,clk-out.yaml           | 107 +++++++++++++++++++++
>  1 file changed, 107 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/rockchip,clk-out.yaml
> 
> diff --git a/Documentation/devicetree/bindings/clock/rockchip,clk-out.yaml b/Documentation/devicetree/bindings/clock/rockchip,clk-out.yaml
> new file mode 100644
> index 0000000..6582605
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/rockchip,clk-out.yaml
> @@ -0,0 +1,107 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/rockchip,clk-out.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip Clock Out Control Module Binding

It does not look like you tested the bindings, at least after quick
look. Please run `make dt_binding_check` (see
Documentation/devicetree/bindings/writing-schema.rst for instructions).
Maybe you need to update your dtschema and yamllint.

> +
> +maintainers:
> +  - Sugar Zhang <sugar.zhang@rock-chips.com>
> +
> +description: |
> +  This add support switch for clk-bidirection which located

No, "this does not add". This is description of hardware, thus describe
hardware.

> +  at GRF, such as SAIx_MCLK_{IN OUT} which share the same pin.
> +  and these config maybe located in many pieces of GRF,
> +  which hard to addressed in one single clk driver. so, we add
> +  this simple helper driver to address this situation.

Bindings are for hardware, not drivers. Rephrase EVERYTHING to focus on
hardware, not driver. Otherwise it looks like you wrote it for drivers,
which is a NAK.

> +
> +  In order to simplify implement and usage, and also for safety
> +  clk usage (avoid high freq glitch), we set all clk out as disabled
> +  (which means Input default for clk-bidrection) in the pre-stage,
> +  such boot-loader or init by HW default. And then set a safety freq
> +  before enable clk-out, such as "assign-clock-rates" or clk_set_rate
> +  in drivers.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - rockchip,clk-out

Missing SoC compatible. See writing bindings.


> +
> +  reg:
> +    maxItems: 1
> +
> +  "#clock-cells":
> +    const: 1
> +
> +  clocks:
> +    maxItems: 1
> +    description: parent clocks.

Drop useless description.

> +
> +  power-domains:
> +    maxItems: 1
> +
> +  clock-output-names:
> +    maxItems: 1
> +
> +  rockchip,bit-shift:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description: Defines the bit shift of clk out enable.

No, this is deduced from compatible.

> +
> +  rockchip,bit-set-to-disable:
> +    type: boolean
> +    description: |
> +      By default this clock sets the bit at bit-shift to enable the clock.
> +      Setting this property does the opposite: setting the bit disable
> +      the clock and clearing it enables the clock.

No, this is deduced from compatible.

Binding looks really poor, like written for some debug driver.


> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - "#clock-cells"
> +  - clock-output-names
> +  - rockchip,bit-shift
> +
> +additionalProperties: false
> +
> +examples:
> +  # Clock Provider node:
> +  - |
> +    mclkin_sai0: mclkin-sai0 {
> +        compatible = "fixed-clock";
> +        #clock-cells = <0>;
> +        clock-frequency = <12288000>;
> +        clock-output-names = "mclk_sai0_from_io";
> +    };

Drop, unrelated.

> +
> +    mclkout_sai0: mclkout-sai0@ff040070 {

Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation


> +        compatible = "rockchip,clk-out";
> +        reg = <0 0xff040070 0 0x4>;
> +        clocks = <&cru MCLK_SAI0_OUT2IO>;
> +        #clock-cells = <0>;
> +        clock-output-names = "mclk_sai0_to_io";
> +        rockchip,bit-shift = <4>;
> +    };
> +
> +  # Clock mclkout Consumer node:
> +  - |
> +    ext_codec {

Drop, not related, incorrect name.

> +        clocks = <&mclkout_sai0>;
> +        clock-names = "mclk";
> +        assigned-clocks = <&mclkout_sai0>;
> +        assigned-clock-rates = <12288000>;
> +        pinctrl-names = "default";
> +        pinctrl-0 = <&i2s0m0_mclk>;
> +    };
> +
> +  # Clock mclkin Consumer node:
> +  - |
> +    ext_codec {

Drop.

Don't upstream poor quality downstream code, but fix it first to match
upstream style. Read carefully writing bindings and DTS coding style.



Best regards,
Krzysztof


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