* [PATCH v6 1/5] arm64: dts: ti: k3-j784s4-evm: Add alias for MCU CPSW2G
2024-03-29 5:31 [PATCH v6 0/5] Add CPSW2G and CPSW9G nodes for J784S4 Chintan Vankar
@ 2024-03-29 5:31 ` Chintan Vankar
2024-03-29 5:31 ` [PATCH v6 2/5] arm64: dts: ti: k3-j784s4-main: Add CPSW2G and CPSW9G nodes Chintan Vankar
` (5 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Chintan Vankar @ 2024-03-29 5:31 UTC (permalink / raw)
To: Conor Dooley, Krzysztof Kozlowski, Rob Herring, Tero Kristo,
Vignesh Raghavendra, Nishanth Menon
Cc: linux-kernel, devicetree, linux-arm-kernel, s-vadapalli,
Chintan Vankar
Add alias for the MCU CPSW2G port to enable Linux to fetch MAC Address
for the port directly from U-Boot.
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---
Link to v5:
https://lore.kernel.org/r/20240314072129.1520475-2-c-vankar@ti.com/
Changes from v5 to v6:
- No changes in v6.
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
index 81fd7afac8c5..1f390c22844e 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
@@ -27,6 +27,7 @@ aliases {
mmc1 = &main_sdhci1;
i2c0 = &wkup_i2c0;
i2c3 = &main_i2c0;
+ ethernet0 = &mcu_cpsw_port1;
};
memory@80000000 {
--
2.34.1
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v6 2/5] arm64: dts: ti: k3-j784s4-main: Add CPSW2G and CPSW9G nodes
2024-03-29 5:31 [PATCH v6 0/5] Add CPSW2G and CPSW9G nodes for J784S4 Chintan Vankar
2024-03-29 5:31 ` [PATCH v6 1/5] arm64: dts: ti: k3-j784s4-evm: Add alias for MCU CPSW2G Chintan Vankar
@ 2024-03-29 5:31 ` Chintan Vankar
2024-03-29 5:31 ` [PATCH v6 3/5] arm64: dts: ti: k3-j784s4-evm: Enable Main CPSW2G node and add aliases for it Chintan Vankar
` (4 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Chintan Vankar @ 2024-03-29 5:31 UTC (permalink / raw)
To: Conor Dooley, Krzysztof Kozlowski, Rob Herring, Tero Kristo,
Vignesh Raghavendra, Nishanth Menon
Cc: linux-kernel, devicetree, linux-arm-kernel, s-vadapalli,
Chintan Vankar
From: Siddharth Vadapalli <s-vadapalli@ti.com>
J784S4 SoC has MAIN CPSW2G and CPSW9G instances of the CPSW
Ethernet Switch. CPSW2G has 1 external port and 1 host port
while CPSW9G has 8 external ports and 1 host port.
Add device-tree nodes for MAIN CPSW2G and CPSW9G and disable
them by default. MAIN CPSW2G will be enabled in the board file
while device-tree overlays will be used to enable CPSW9G.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---
Link to v5:
https://lore.kernel.org/r/20240314072129.1520475-3-c-vankar@ti.com/
Changes from v5 to v6:
- Updated order of properties in Device Nodes based on
https://docs.kernel.org/devicetree/bindings/dts-coding-style.html#order-of-properties-in-device-node
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 187 +++++++++++++++++++++
1 file changed, 187 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index b67c37460a73..7dfa43d25d38 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -48,6 +48,19 @@ scm_conf: bus@100000 {
#size-cells = <1>;
ranges = <0x00 0x00 0x00100000 0x1c000>;
+ cpsw1_phy_gmii_sel: phy@4034 {
+ compatible = "ti,am654-phy-gmii-sel";
+ reg = <0x4034 0x4>;
+ #phy-cells = <1>;
+ };
+
+ cpsw0_phy_gmii_sel: phy@4044 {
+ compatible = "ti,j784s4-cpsw9g-phy-gmii-sel";
+ reg = <0x4044 0x20>;
+ #phy-cells = <1>;
+ ti,qsgmii-main-ports = <7>, <7>;
+ };
+
serdes_ln_ctrl: mux-controller@4080 {
compatible = "reg-mux";
reg = <0x00004080 0x30>;
@@ -1439,6 +1452,180 @@ cpts@310d0000 {
};
};
+ main_cpsw0: ethernet@c000000 {
+ compatible = "ti,j784s4-cpswxg-nuss";
+ reg = <0x00 0xc000000 0x00 0x200000>;
+ reg-names = "cpsw_nuss";
+ ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-coherent;
+ clocks = <&k3_clks 64 0>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
+
+ dmas = <&main_udmap 0xca00>,
+ <&main_udmap 0xca01>,
+ <&main_udmap 0xca02>,
+ <&main_udmap 0xca03>,
+ <&main_udmap 0xca04>,
+ <&main_udmap 0xca05>,
+ <&main_udmap 0xca06>,
+ <&main_udmap 0xca07>,
+ <&main_udmap 0x4a00>;
+ dma-names = "tx0", "tx1", "tx2", "tx3",
+ "tx4", "tx5", "tx6", "tx7",
+ "rx";
+
+ status = "disabled";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ main_cpsw0_port1: port@1 {
+ reg = <1>;
+ label = "port1";
+ ti,mac-only;
+ status = "disabled";
+ };
+
+ main_cpsw0_port2: port@2 {
+ reg = <2>;
+ label = "port2";
+ ti,mac-only;
+ status = "disabled";
+ };
+
+ main_cpsw0_port3: port@3 {
+ reg = <3>;
+ label = "port3";
+ ti,mac-only;
+ status = "disabled";
+ };
+
+ main_cpsw0_port4: port@4 {
+ reg = <4>;
+ label = "port4";
+ ti,mac-only;
+ status = "disabled";
+ };
+
+ main_cpsw0_port5: port@5 {
+ reg = <5>;
+ label = "port5";
+ ti,mac-only;
+ status = "disabled";
+ };
+
+ main_cpsw0_port6: port@6 {
+ reg = <6>;
+ label = "port6";
+ ti,mac-only;
+ status = "disabled";
+ };
+
+ main_cpsw0_port7: port@7 {
+ reg = <7>;
+ label = "port7";
+ ti,mac-only;
+ status = "disabled";
+ };
+
+ main_cpsw0_port8: port@8 {
+ reg = <8>;
+ label = "port8";
+ ti,mac-only;
+ status = "disabled";
+ };
+ };
+
+ main_cpsw0_mdio: mdio@f00 {
+ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+ reg = <0x00 0xf00 0x00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 64 0>;
+ clock-names = "fck";
+ bus_freq = <1000000>;
+ status = "disabled";
+ };
+
+ cpts@3d000 {
+ compatible = "ti,am65-cpts";
+ reg = <0x00 0x3d000 0x00 0x400>;
+ clocks = <&k3_clks 64 3>;
+ clock-names = "cpts";
+ interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cpts";
+ ti,cpts-ext-ts-inputs = <4>;
+ ti,cpts-periodic-outputs = <2>;
+ };
+ };
+
+ main_cpsw1: ethernet@c200000 {
+ compatible = "ti,j721e-cpsw-nuss";
+ reg = <0x00 0xc200000 0x00 0x200000>;
+ reg-names = "cpsw_nuss";
+ ranges = <0x00 0x00 0x00 0xc200000 0x00 0x200000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-coherent;
+ clocks = <&k3_clks 62 0>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
+
+ dmas = <&main_udmap 0xc640>,
+ <&main_udmap 0xc641>,
+ <&main_udmap 0xc642>,
+ <&main_udmap 0xc643>,
+ <&main_udmap 0xc644>,
+ <&main_udmap 0xc645>,
+ <&main_udmap 0xc646>,
+ <&main_udmap 0xc647>,
+ <&main_udmap 0x4640>;
+ dma-names = "tx0", "tx1", "tx2", "tx3",
+ "tx4", "tx5", "tx6", "tx7",
+ "rx";
+
+ status = "disabled";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ main_cpsw1_port1: port@1 {
+ reg = <1>;
+ label = "port1";
+ phys = <&cpsw1_phy_gmii_sel 1>;
+ ti,mac-only;
+ status = "disabled";
+ };
+ };
+
+ main_cpsw1_mdio: mdio@f00 {
+ compatible = "ti,cpsw-mdio", "ti,davinci_mdio";
+ reg = <0x00 0xf00 0x00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 62 0>;
+ clock-names = "fck";
+ bus_freq = <1000000>;
+ status = "disabled";
+ };
+
+ cpts@3d000 {
+ compatible = "ti,am65-cpts";
+ reg = <0x00 0x3d000 0x00 0x400>;
+ clocks = <&k3_clks 62 3>;
+ clock-names = "cpts";
+ interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cpts";
+ ti,cpts-ext-ts-inputs = <4>;
+ ti,cpts-periodic-outputs = <2>;
+ };
+ };
+
main_mcan0: can@2701000 {
compatible = "bosch,m_can";
reg = <0x00 0x02701000 0x00 0x200>,
--
2.34.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v6 3/5] arm64: dts: ti: k3-j784s4-evm: Enable Main CPSW2G node and add aliases for it
2024-03-29 5:31 [PATCH v6 0/5] Add CPSW2G and CPSW9G nodes for J784S4 Chintan Vankar
2024-03-29 5:31 ` [PATCH v6 1/5] arm64: dts: ti: k3-j784s4-evm: Add alias for MCU CPSW2G Chintan Vankar
2024-03-29 5:31 ` [PATCH v6 2/5] arm64: dts: ti: k3-j784s4-main: Add CPSW2G and CPSW9G nodes Chintan Vankar
@ 2024-03-29 5:31 ` Chintan Vankar
2024-03-29 5:31 ` [PATCH v6 4/5] arm64: dts: ti: k3-j784s4: Add overlay to enable QSGMII mode with CPSW9G Chintan Vankar
` (3 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Chintan Vankar @ 2024-03-29 5:31 UTC (permalink / raw)
To: Conor Dooley, Krzysztof Kozlowski, Rob Herring, Tero Kristo,
Vignesh Raghavendra, Nishanth Menon
Cc: linux-kernel, devicetree, linux-arm-kernel, s-vadapalli,
Jayesh Choudhary, Chintan Vankar
From: Siddharth Vadapalli <s-vadapalli@ti.com>
Enable MAIN CPSW2G and add alias for it to enable Linux to fetch
MAC Address for the port directly from U-Boot.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---
Link to v5:
https://lore.kernel.org/r/20240314072129.1520475-4-c-vankar@ti.com/
Changes from v5 to v6:
- Updated order of properties in Device Nodes based on
https://docs.kernel.org/devicetree/bindings/dts-coding-style.html#order-of-properties-in-device-node
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 50 ++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
index 1f390c22844e..637c8223b561 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
@@ -28,6 +28,7 @@ aliases {
i2c0 = &wkup_i2c0;
i2c3 = &main_i2c0;
ethernet0 = &mcu_cpsw_port1;
+ ethernet1 = &main_cpsw1_port1;
};
memory@80000000 {
@@ -281,6 +282,30 @@ &wkup_gpio0 {
&main_pmx0 {
bootph-all;
+ main_cpsw2g_default_pins: main-cpsw2g-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x0b8, PIN_INPUT, 6) /* (AC34) MCASP1_ACLKX.RGMII1_RD0 */
+ J784S4_IOPAD(0x0a0, PIN_INPUT, 6) /* (AD34) MCASP0_AXR12.RGMII1_RD1 */
+ J784S4_IOPAD(0x0a4, PIN_INPUT, 6) /* (AJ36) MCASP0_AXR13.RGMII1_RD2 */
+ J784S4_IOPAD(0x0a8, PIN_INPUT, 6) /* (AF34) MCASP0_AXR14.RGMII1_RD3 */
+ J784S4_IOPAD(0x0b0, PIN_INPUT, 6) /* (AL33) MCASP1_AXR3.RGMII1_RXC */
+ J784S4_IOPAD(0x0ac, PIN_INPUT, 6) /* (AE34) MCASP0_AXR15.RGMII1_RX_CTL */
+ J784S4_IOPAD(0x08c, PIN_INPUT, 6) /* (AE35) MCASP0_AXR7.RGMII1_TD0 */
+ J784S4_IOPAD(0x090, PIN_INPUT, 6) /* (AC35) MCASP0_AXR8.RGMII1_TD1 */
+ J784S4_IOPAD(0x094, PIN_INPUT, 6) /* (AG35) MCASP0_AXR9.RGMII1_TD2 */
+ J784S4_IOPAD(0x098, PIN_INPUT, 6) /* (AH36) MCASP0_AXR10.RGMII1_TD3 */
+ J784S4_IOPAD(0x0b4, PIN_INPUT, 6) /* (AL34) MCASP1_AXR4.RGMII1_TXC */
+ J784S4_IOPAD(0x09c, PIN_INPUT, 6) /* (AF35) MCASP0_AXR11.RGMII1_TX_CTL */
+ >;
+ };
+
+ main_cpsw2g_mdio_default_pins: main-cpsw2g-mdio-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x0c0, PIN_INPUT, 6) /* (AD38) MCASP1_AXR0.MDIO0_MDC */
+ J784S4_IOPAD(0x0bc, PIN_INPUT, 6) /* (AD33) MCASP1_AFSX.MDIO0_MDIO */
+ >;
+ };
+
main_uart8_pins_default: main-uart8-default-pins {
bootph-all;
pinctrl-single,pins = <
@@ -833,6 +858,31 @@ &mcu_cpsw_port1 {
phy-handle = <&mcu_phy0>;
};
+&main_cpsw1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_cpsw2g_default_pins>;
+ status = "okay";
+};
+
+&main_cpsw1_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_cpsw2g_mdio_default_pins>;
+ status = "okay";
+
+ main_cpsw1_phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,min-output-impedance;
+ };
+};
+
+&main_cpsw1_port1 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&main_cpsw1_phy0>;
+ status = "okay";
+};
+
&mailbox0_cluster0 {
status = "okay";
interrupts = <436>;
--
2.34.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v6 4/5] arm64: dts: ti: k3-j784s4: Add overlay to enable QSGMII mode with CPSW9G
2024-03-29 5:31 [PATCH v6 0/5] Add CPSW2G and CPSW9G nodes for J784S4 Chintan Vankar
` (2 preceding siblings ...)
2024-03-29 5:31 ` [PATCH v6 3/5] arm64: dts: ti: k3-j784s4-evm: Enable Main CPSW2G node and add aliases for it Chintan Vankar
@ 2024-03-29 5:31 ` Chintan Vankar
2024-03-29 5:31 ` [PATCH v6 5/5] arm64: dts: ti: k3-j784s4: Add overlay for dual port USXGMII mode Chintan Vankar
` (2 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Chintan Vankar @ 2024-03-29 5:31 UTC (permalink / raw)
To: Conor Dooley, Krzysztof Kozlowski, Rob Herring, Tero Kristo,
Vignesh Raghavendra, Nishanth Menon
Cc: linux-kernel, devicetree, linux-arm-kernel, s-vadapalli,
Chintan Vankar
From: Siddharth Vadapalli <s-vadapalli@ti.com>
The J7 Quad Port Add-On Ethernet Card for J784S4 EVM supports
QSGMII mode. Use the overlay to configure CPSW9G ports in QSGMII
mode with the Add-On Ethernet Card connected to the ENET Expansion
1 slot on the EVM.
Add support to reset the PHY from kernel by using gpio-hog and
gpio-reset.
Add aliases for CPSW9G ports to enable kernel to fetch MAC Addresses
directly from U-Boot.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---
Link to v5:
https://lore.kernel.org/r/20240314072129.1520475-5-c-vankar@ti.com/
Changes from v5 to v6:
- Updated order of properties in Device Nodes based on
https://docs.kernel.org/devicetree/bindings/dts-coding-style.html#order-of-properties-in-device-node
arch/arm64/boot/dts/ti/Makefile | 7 +-
.../ti/k3-j784s4-evm-quad-port-eth-exp1.dtso | 147 ++++++++++++++++++
2 files changed, 153 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 9a722c2473fb..f8e47278df43 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -100,6 +100,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb
# Boards with J784s4 SoC
dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-quad-port-eth-exp1.dtbo
# Build time test only, enabled by CONFIG_OF_ALL_DTBS
k3-am625-beagleplay-csi2-ov5640-dtbs := k3-am625-beagleplay.dtb \
@@ -145,6 +146,8 @@ k3-j721e-sk-csi2-dual-imx219-dtbs := k3-j721e-sk.dtb \
k3-j721e-sk-csi2-dual-imx219.dtbo
k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \
k3-j721s2-evm-pcie1-ep.dtbo
+k3-j784s4-evm-quad-port-eth-exp1-dtbs := k3-j784s4-evm.dtb \
+ k3-j784s4-evm-quad-port-eth-exp1.dtbo
dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
k3-am625-beagleplay-csi2-tevi-ov5640.dtb \
k3-am625-sk-csi2-imx219.dtb \
@@ -165,7 +168,8 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
k3-am69-sk-csi2-dual-imx219-dtbs \
k3-j721e-evm-pcie0-ep.dtb \
k3-j721e-sk-csi2-dual-imx219-dtbs \
- k3-j721s2-evm-pcie1-ep.dtb
+ k3-j721s2-evm-pcie1-ep.dtb \
+ k3-j784s4-evm-quad-port-eth-exp1.dtb
# Enable support for device-tree overlays
DTC_FLAGS_k3-am625-beagleplay += -@
@@ -181,3 +185,4 @@ DTC_FLAGS_k3-am69-sk += -@
DTC_FLAGS_k3-j721e-common-proc-board += -@
DTC_FLAGS_k3-j721e-sk += -@
DTC_FLAGS_k3-j721s2-common-proc-board += -@
+DTC_FLAGS_k3-j784s4-evm += -@
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso b/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso
new file mode 100644
index 000000000000..dcd2c7c39ec3
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+/**
+ * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
+ * J784S4 EVM. The Add-On Ethernet Card has to be connected to ENET Expansion 1 slot on the
+ * board.
+ *
+ * Product Datasheet: https://www.ti.com/lit/ug/spruj74/spruj74.pdf
+ *
+ * Link to QSGMII Daughtercard: https://www.ti.com/tool/J721EXENETXPANEVM
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/phy/phy.h>
+
+#include "k3-pinctrl.h"
+#include "k3-serdes.h"
+
+&{/} {
+ aliases {
+ ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@5";
+ ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@6";
+ ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@7";
+ ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@8";
+ ethernet5 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1";
+ };
+};
+
+&main_cpsw0 {
+ status = "okay";
+};
+
+&main_cpsw0_port5 {
+ phy-handle = <&cpsw9g_phy1>;
+ phy-mode = "qsgmii";
+ mac-address = [00 00 00 00 00 00];
+ phys = <&cpsw0_phy_gmii_sel 5>, <&serdes2_qsgmii_link>;
+ phy-names = "mac", "serdes";
+ status = "okay";
+};
+
+&main_cpsw0_port6 {
+ phy-handle = <&cpsw9g_phy2>;
+ phy-mode = "qsgmii";
+ mac-address = [00 00 00 00 00 00];
+ phys = <&cpsw0_phy_gmii_sel 6>, <&serdes2_qsgmii_link>;
+ phy-names = "mac", "serdes";
+ status = "okay";
+};
+
+&main_cpsw0_port7 {
+ phy-handle = <&cpsw9g_phy0>;
+ phy-mode = "qsgmii";
+ mac-address = [00 00 00 00 00 00];
+ phys = <&cpsw0_phy_gmii_sel 7>, <&serdes2_qsgmii_link>;
+ phy-names = "mac", "serdes";
+ status = "okay";
+};
+
+&main_cpsw0_port8 {
+ phy-handle = <&cpsw9g_phy3>;
+ phy-mode = "qsgmii";
+ mac-address = [00 00 00 00 00 00];
+ phys = <&cpsw0_phy_gmii_sel 8>, <&serdes2_qsgmii_link>;
+ phy-names = "mac", "serdes";
+ status = "okay";
+};
+
+&main_cpsw0_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio0_default_pins>;
+ bus_freq = <1000000>;
+ reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>;
+ reset-post-delay-us = <120000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ cpsw9g_phy0: ethernet-phy@16 {
+ reg = <16>;
+ };
+ cpsw9g_phy1: ethernet-phy@17 {
+ reg = <17>;
+ };
+ cpsw9g_phy2: ethernet-phy@18 {
+ reg = <18>;
+ };
+ cpsw9g_phy3: ethernet-phy@19 {
+ reg = <19>;
+ };
+};
+
+&exp2 {
+ /* Power-up ENET1 EXPANDER PHY. */
+ qsgmii-line-hog {
+ gpio-hog;
+ gpios = <16 GPIO_ACTIVE_HIGH>;
+ output-low;
+ };
+
+ /* Toggle MUX2 for MDIO lines */
+ mux-sel-hog {
+ gpio-hog;
+ gpios = <13 GPIO_ACTIVE_HIGH>, <14 GPIO_ACTIVE_HIGH>, <15 GPIO_ACTIVE_HIGH>;
+ output-high;
+ };
+};
+
+&main_pmx0 {
+ mdio0_default_pins: mdio0-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x05c, PIN_INPUT, 4) /* (AC36) MCASP2_AXR0.MDIO1_MDIO */
+ J784S4_IOPAD(0x058, PIN_INPUT, 4) /* (AE37) MCASP2_AFSX.MDIO1_MDC */
+ >;
+ };
+};
+
+&serdes_ln_ctrl {
+ idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
+ <J784S4_SERDES0_LANE2_IP3_UNUSED>, <J784S4_SERDES0_LANE3_USB>,
+ <J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
+ <J784S4_SERDES1_LANE2_PCIE0_LANE2>, <J784S4_SERDES1_LANE3_PCIE0_LANE3>,
+ <J784S4_SERDES2_LANE0_QSGMII_LANE5>, <J784S4_SERDES2_LANE1_QSGMII_LANE6>,
+ <J784S4_SERDES2_LANE2_QSGMII_LANE7>, <J784S4_SERDES2_LANE3_QSGMII_LANE8>;
+};
+
+&serdes_wiz2 {
+ status = "okay";
+};
+
+&serdes2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ serdes2_qsgmii_link: phy@0 {
+ reg = <2>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_QSGMII>;
+ resets = <&serdes_wiz2 3>;
+ };
+};
--
2.34.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v6 5/5] arm64: dts: ti: k3-j784s4: Add overlay for dual port USXGMII mode
2024-03-29 5:31 [PATCH v6 0/5] Add CPSW2G and CPSW9G nodes for J784S4 Chintan Vankar
` (3 preceding siblings ...)
2024-03-29 5:31 ` [PATCH v6 4/5] arm64: dts: ti: k3-j784s4: Add overlay to enable QSGMII mode with CPSW9G Chintan Vankar
@ 2024-03-29 5:31 ` Chintan Vankar
2024-04-29 10:31 ` Krzysztof Kozlowski
2024-04-17 11:57 ` [PATCH v6 0/5] Add CPSW2G and CPSW9G nodes for J784S4 MD Danish Anwar
2024-04-26 22:37 ` Nishanth Menon
6 siblings, 1 reply; 11+ messages in thread
From: Chintan Vankar @ 2024-03-29 5:31 UTC (permalink / raw)
To: Conor Dooley, Krzysztof Kozlowski, Rob Herring, Tero Kristo,
Vignesh Raghavendra, Nishanth Menon
Cc: linux-kernel, devicetree, linux-arm-kernel, s-vadapalli,
Chintan Vankar
From: Siddharth Vadapalli <s-vadapalli@ti.com>
The CPSW9G instance of the CPSW Ethernet Switch supports USXGMII mode
with MAC Ports 1 and 2 of the instance, which are connected to ENET
Expansion 1 and ENET Expansion 2 slots on the EVM respectively, through
the Serdes2 instance of the SERDES.
Enable CPSW9G MAC Ports 1 and 2 in fixed-link configuration USXGMII mode
at 5 Gbps each.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---
Link to v5:
https://lore.kernel.org/r/20240314072129.1520475-6-c-vankar@ti.com/
Changes from v5 to v6:
- Updated order of properties in Device Nodes based on
https://docs.kernel.org/devicetree/bindings/dts-coding-style.html#order-of-properties-in-device-node
arch/arm64/boot/dts/ti/Makefile | 6 +-
.../ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso | 81 +++++++++++++++++++
2 files changed, 86 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index f8e47278df43..2d798ef415e4 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -101,6 +101,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-quad-port-eth-exp1.dtbo
+dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-usxgmii-exp1-exp2.dtbo
# Build time test only, enabled by CONFIG_OF_ALL_DTBS
k3-am625-beagleplay-csi2-ov5640-dtbs := k3-am625-beagleplay.dtb \
@@ -148,6 +149,8 @@ k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \
k3-j721s2-evm-pcie1-ep.dtbo
k3-j784s4-evm-quad-port-eth-exp1-dtbs := k3-j784s4-evm.dtb \
k3-j784s4-evm-quad-port-eth-exp1.dtbo
+k3-j784s4-evm-usxgmii-exp1-exp2.dtbs := k3-j784s4-evm.dtb \
+ k3-j784s4-evm-usxgmii-exp1-exp2.dtbo
dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
k3-am625-beagleplay-csi2-tevi-ov5640.dtb \
k3-am625-sk-csi2-imx219.dtb \
@@ -169,7 +172,8 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
k3-j721e-evm-pcie0-ep.dtb \
k3-j721e-sk-csi2-dual-imx219-dtbs \
k3-j721s2-evm-pcie1-ep.dtb \
- k3-j784s4-evm-quad-port-eth-exp1.dtb
+ k3-j784s4-evm-quad-port-eth-exp1.dtb \
+ k3-j784s4-evm-usxgmii-exp1-exp2.dtb
# Enable support for device-tree overlays
DTC_FLAGS_k3-am625-beagleplay += -@
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso b/arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso
new file mode 100644
index 000000000000..d5f8c8531923
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+/**
+ * DT Overlay for CPSW9G in dual port fixed-link USXGMII mode using ENET-1
+ * and ENET-2 Expansion slots of J784S4 EVM.
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/phy/phy.h>
+
+#include "k3-serdes.h"
+
+&{/} {
+ aliases {
+ ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
+ ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
+ ethernet3 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1";
+ };
+};
+
+&main_cpsw0 {
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&main_cpsw0_port1 {
+ phy-mode = "usxgmii";
+ mac-address = [00 00 00 00 00 00];
+ phys = <&cpsw0_phy_gmii_sel 1>, <&serdes2_usxgmii_link>;
+ phy-names = "mac", "serdes";
+ status = "okay";
+ fixed-link {
+ speed = <5000>;
+ full-duplex;
+ };
+};
+
+&main_cpsw0_port2 {
+ phy-mode = "usxgmii";
+ mac-address = [00 00 00 00 00 00];
+ phys = <&cpsw0_phy_gmii_sel 2>, <&serdes2_usxgmii_link>;
+ phy-names = "mac", "serdes";
+ status = "okay";
+ fixed-link {
+ speed = <5000>;
+ full-duplex;
+ };
+};
+
+&serdes_wiz2 {
+ assigned-clock-parents = <&k3_clks 406 9>; /* Use 156.25 MHz clock for USXGMII */
+ status = "okay";
+};
+
+&serdes2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ serdes2_usxgmii_link: phy@2 {
+ reg = <2>;
+ cdns,num-lanes = <2>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USXGMII>;
+ resets = <&serdes_wiz2 3>, <&serdes_wiz2 4>;
+ };
+};
+
+&serdes_ln_ctrl {
+ idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
+ <J784S4_SERDES0_LANE2_IP3_UNUSED>, <J784S4_SERDES0_LANE3_USB>,
+ <J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
+ <J784S4_SERDES1_LANE2_PCIE0_LANE2>, <J784S4_SERDES1_LANE3_PCIE0_LANE3>,
+ <J784S4_SERDES2_LANE0_IP2_UNUSED>, <J784S4_SERDES2_LANE1_IP2_UNUSED>,
+ <J784S4_SERDES2_LANE2_QSGMII_LANE1>, <J784S4_SERDES2_LANE3_QSGMII_LANE2>;
+};
--
2.34.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v6 5/5] arm64: dts: ti: k3-j784s4: Add overlay for dual port USXGMII mode
2024-03-29 5:31 ` [PATCH v6 5/5] arm64: dts: ti: k3-j784s4: Add overlay for dual port USXGMII mode Chintan Vankar
@ 2024-04-29 10:31 ` Krzysztof Kozlowski
2024-04-29 11:46 ` Chintan Vankar
0 siblings, 1 reply; 11+ messages in thread
From: Krzysztof Kozlowski @ 2024-04-29 10:31 UTC (permalink / raw)
To: Chintan Vankar, Conor Dooley, Krzysztof Kozlowski, Rob Herring,
Tero Kristo, Vignesh Raghavendra, Nishanth Menon
Cc: linux-kernel, devicetree, linux-arm-kernel, s-vadapalli
On 29/03/2024 06:31, Chintan Vankar wrote:
> From: Siddharth Vadapalli <s-vadapalli@ti.com>
>
> The CPSW9G instance of the CPSW Ethernet Switch supports USXGMII mode
> with MAC Ports 1 and 2 of the instance, which are connected to ENET
> Expansion 1 and ENET Expansion 2 slots on the EVM respectively, through
> the Serdes2 instance of the SERDES.
>
> Enable CPSW9G MAC Ports 1 and 2 in fixed-link configuration USXGMII mode
> at 5 Gbps each.
>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> Signed-off-by: Chintan Vankar <c-vankar@ti.com>
> ---
>
> Link to v5:
> https://lore.kernel.org/r/20240314072129.1520475-6-c-vankar@ti.com/
>
> Changes from v5 to v6:
> - Updated order of properties in Device Nodes based on
> https://docs.kernel.org/devicetree/bindings/dts-coding-style.html#order-of-properties-in-device-node
>
> arch/arm64/boot/dts/ti/Makefile | 6 +-
> .../ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso | 81 +++++++++++++++++++
> 2 files changed, 86 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso
>
> diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
> index f8e47278df43..2d798ef415e4 100644
> --- a/arch/arm64/boot/dts/ti/Makefile
> +++ b/arch/arm64/boot/dts/ti/Makefile
> @@ -101,6 +101,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb
> dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb
> dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb
> dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-quad-port-eth-exp1.dtbo
> +dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-usxgmii-exp1-exp2.dtbo
>
> # Build time test only, enabled by CONFIG_OF_ALL_DTBS
> k3-am625-beagleplay-csi2-ov5640-dtbs := k3-am625-beagleplay.dtb \
> @@ -148,6 +149,8 @@ k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \
> k3-j721s2-evm-pcie1-ep.dtbo
> k3-j784s4-evm-quad-port-eth-exp1-dtbs := k3-j784s4-evm.dtb \
> k3-j784s4-evm-quad-port-eth-exp1.dtbo
> +k3-j784s4-evm-usxgmii-exp1-exp2.dtbs := k3-j784s4-evm.dtb \
> + k3-j784s4-evm-usxgmii-exp1-exp2.dtbo\
I have doubts this commit was ever built. It clearly fails, just like
now linux-next fails.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v6 5/5] arm64: dts: ti: k3-j784s4: Add overlay for dual port USXGMII mode
2024-04-29 10:31 ` Krzysztof Kozlowski
@ 2024-04-29 11:46 ` Chintan Vankar
2024-04-29 19:39 ` Nishanth Menon
0 siblings, 1 reply; 11+ messages in thread
From: Chintan Vankar @ 2024-04-29 11:46 UTC (permalink / raw)
To: Krzysztof Kozlowski, Conor Dooley, Krzysztof Kozlowski,
Rob Herring, Tero Kristo, Vignesh Raghavendra, Nishanth Menon
Cc: linux-kernel, devicetree, linux-arm-kernel, s-vadapalli
On 29/04/24 16:01, Krzysztof Kozlowski wrote:
> On 29/03/2024 06:31, Chintan Vankar wrote:
>> From: Siddharth Vadapalli <s-vadapalli@ti.com>
>>
>> The CPSW9G instance of the CPSW Ethernet Switch supports USXGMII mode
>> with MAC Ports 1 and 2 of the instance, which are connected to ENET
>> Expansion 1 and ENET Expansion 2 slots on the EVM respectively, through
>> the Serdes2 instance of the SERDES.
>>
>> Enable CPSW9G MAC Ports 1 and 2 in fixed-link configuration USXGMII mode
>> at 5 Gbps each.
>>
>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
>> Signed-off-by: Chintan Vankar <c-vankar@ti.com>
>> ---
>>
>> Link to v5:
>> https://lore.kernel.org/r/20240314072129.1520475-6-c-vankar@ti.com/
>>
>> Changes from v5 to v6:
>> - Updated order of properties in Device Nodes based on
>> https://docs.kernel.org/devicetree/bindings/dts-coding-style.html#order-of-properties-in-device-node
>>
>> arch/arm64/boot/dts/ti/Makefile | 6 +-
>> .../ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso | 81 +++++++++++++++++++
>> 2 files changed, 86 insertions(+), 1 deletion(-)
>> create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso
>>
>> diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
>> index f8e47278df43..2d798ef415e4 100644
>> --- a/arch/arm64/boot/dts/ti/Makefile
>> +++ b/arch/arm64/boot/dts/ti/Makefile
>> @@ -101,6 +101,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb
>> dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb
>> dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb
>> dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-quad-port-eth-exp1.dtbo
>> +dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-usxgmii-exp1-exp2.dtbo
>>
>> # Build time test only, enabled by CONFIG_OF_ALL_DTBS
>> k3-am625-beagleplay-csi2-ov5640-dtbs := k3-am625-beagleplay.dtb \
>> @@ -148,6 +149,8 @@ k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \
>> k3-j721s2-evm-pcie1-ep.dtbo
>> k3-j784s4-evm-quad-port-eth-exp1-dtbs := k3-j784s4-evm.dtb \
>> k3-j784s4-evm-quad-port-eth-exp1.dtbo
>> +k3-j784s4-evm-usxgmii-exp1-exp2.dtbs := k3-j784s4-evm.dtb \
>> + k3-j784s4-evm-usxgmii-exp1-exp2.dtbo\
>
> I have doubts this commit was ever built. It clearly fails, just like
> now linux-next fails.
>
Apologies for the syntax error here, I will fix it and post next
version.
> Best regards,
> Krzysztof
>
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v6 5/5] arm64: dts: ti: k3-j784s4: Add overlay for dual port USXGMII mode
2024-04-29 11:46 ` Chintan Vankar
@ 2024-04-29 19:39 ` Nishanth Menon
0 siblings, 0 replies; 11+ messages in thread
From: Nishanth Menon @ 2024-04-29 19:39 UTC (permalink / raw)
To: Chintan Vankar
Cc: Krzysztof Kozlowski, Conor Dooley, Krzysztof Kozlowski,
Rob Herring, Tero Kristo, Vignesh Raghavendra, linux-kernel,
devicetree, linux-arm-kernel, s-vadapalli
On 17:16-20240429, Chintan Vankar wrote:
>
>
> On 29/04/24 16:01, Krzysztof Kozlowski wrote:
> > On 29/03/2024 06:31, Chintan Vankar wrote:
> > > From: Siddharth Vadapalli <s-vadapalli@ti.com>
> > >
> > > The CPSW9G instance of the CPSW Ethernet Switch supports USXGMII mode
> > > with MAC Ports 1 and 2 of the instance, which are connected to ENET
> > > Expansion 1 and ENET Expansion 2 slots on the EVM respectively, through
> > > the Serdes2 instance of the SERDES.
> > >
> > > Enable CPSW9G MAC Ports 1 and 2 in fixed-link configuration USXGMII mode
> > > at 5 Gbps each.
> > >
> > > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> > > Signed-off-by: Chintan Vankar <c-vankar@ti.com>
> > > ---
> > >
> > > Link to v5:
> > > https://lore.kernel.org/r/20240314072129.1520475-6-c-vankar@ti.com/
> > >
> > > Changes from v5 to v6:
> > > - Updated order of properties in Device Nodes based on
> > > https://docs.kernel.org/devicetree/bindings/dts-coding-style.html#order-of-properties-in-device-node
> > >
> > > arch/arm64/boot/dts/ti/Makefile | 6 +-
> > > .../ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso | 81 +++++++++++++++++++
> > > 2 files changed, 86 insertions(+), 1 deletion(-)
> > > create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso
> > >
> > > diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
> > > index f8e47278df43..2d798ef415e4 100644
> > > --- a/arch/arm64/boot/dts/ti/Makefile
> > > +++ b/arch/arm64/boot/dts/ti/Makefile
> > > @@ -101,6 +101,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb
> > > dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb
> > > dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb
> > > dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-quad-port-eth-exp1.dtbo
> > > +dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-usxgmii-exp1-exp2.dtbo
> > > # Build time test only, enabled by CONFIG_OF_ALL_DTBS
> > > k3-am625-beagleplay-csi2-ov5640-dtbs := k3-am625-beagleplay.dtb \
> > > @@ -148,6 +149,8 @@ k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \
> > > k3-j721s2-evm-pcie1-ep.dtbo
> > > k3-j784s4-evm-quad-port-eth-exp1-dtbs := k3-j784s4-evm.dtb \
> > > k3-j784s4-evm-quad-port-eth-exp1.dtbo
> > > +k3-j784s4-evm-usxgmii-exp1-exp2.dtbs := k3-j784s4-evm.dtb \
> > > + k3-j784s4-evm-usxgmii-exp1-exp2.dtbo\
> >
> > I have doubts this commit was ever built. It clearly fails, just like
> > now linux-next fails.
> >
>
> Apologies for the syntax error here, I will fix it and post next
> version.
Series dropped. Looks like it slipped my checker as well :(
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v6 0/5] Add CPSW2G and CPSW9G nodes for J784S4
2024-03-29 5:31 [PATCH v6 0/5] Add CPSW2G and CPSW9G nodes for J784S4 Chintan Vankar
` (4 preceding siblings ...)
2024-03-29 5:31 ` [PATCH v6 5/5] arm64: dts: ti: k3-j784s4: Add overlay for dual port USXGMII mode Chintan Vankar
@ 2024-04-17 11:57 ` MD Danish Anwar
2024-04-26 22:37 ` Nishanth Menon
6 siblings, 0 replies; 11+ messages in thread
From: MD Danish Anwar @ 2024-04-17 11:57 UTC (permalink / raw)
To: Chintan Vankar, Conor Dooley, Krzysztof Kozlowski, Rob Herring,
Tero Kristo, Vignesh Raghavendra, Nishanth Menon
Cc: linux-kernel, devicetree, linux-arm-kernel, s-vadapalli
Hi Chintan,
On 29/03/24 11:01 am, Chintan Vankar wrote:
> This series adds device-tree nodes for CPSW2G and CPSW9G instance
> of the CPSW Ethernet Switch on TI's J784S4 SoC. Additionally,
> two device-tree overlays are also added:
> 1. QSGMII mode with the CPSW9G instance via the ENET EXPANSION 1
> connector.
> 2. USXGMII mode with MAC Ports 1 and 2 of the CPSW9G instance via
> ENET EXPANSION 1 and 2 connectors, configured in fixed-link
> mode of operation at 5Gbps link speed.
>
> Link to v5:
> https://lore.kernel.org/r/20240314072129.1520475-1-c-vankar@ti.com/
>
> Changes from v5 to v6:
> - Updated order of properties in Device Nodes based on
> https://docs.kernel.org/devicetree/bindings/dts-coding-style.html#order-of-properties-in-device-node
>
> Chintan Vankar (1):
> arm64: dts: ti: k3-j784s4-evm: Add alias for MCU CPSW2G
>
> Siddharth Vadapalli (4):
> arm64: dts: ti: k3-j784s4-main: Add CPSW2G and CPSW9G nodes
> arm64: dts: ti: k3-j784s4-evm: Enable Main CPSW2G node and add aliases
> for it
> arm64: dts: ti: k3-j784s4: Add overlay to enable QSGMII mode with
> CPSW9G
> arm64: dts: ti: k3-j784s4: Add overlay for dual port USXGMII mode
>
> arch/arm64/boot/dts/ti/Makefile | 11 +-
> .../ti/k3-j784s4-evm-quad-port-eth-exp1.dtso | 147 ++++++++++++++
> .../ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso | 81 ++++++++
> arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 51 +++++
> arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 187 ++++++++++++++++++
> 5 files changed, 476 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso
> create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso
>
For this series,
Reviewed-by: MD Danish Anwar <danishanwar@ti.com>
--
Thanks and Regards,
Danish
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^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v6 0/5] Add CPSW2G and CPSW9G nodes for J784S4
2024-03-29 5:31 [PATCH v6 0/5] Add CPSW2G and CPSW9G nodes for J784S4 Chintan Vankar
` (5 preceding siblings ...)
2024-04-17 11:57 ` [PATCH v6 0/5] Add CPSW2G and CPSW9G nodes for J784S4 MD Danish Anwar
@ 2024-04-26 22:37 ` Nishanth Menon
6 siblings, 0 replies; 11+ messages in thread
From: Nishanth Menon @ 2024-04-26 22:37 UTC (permalink / raw)
To: Conor Dooley, Krzysztof Kozlowski, Rob Herring, Tero Kristo,
Vignesh Raghavendra, Chintan Vankar
Cc: Nishanth Menon, linux-kernel, devicetree, linux-arm-kernel,
s-vadapalli
Hi Chintan Vankar,
On Fri, 29 Mar 2024 11:01:25 +0530, Chintan Vankar wrote:
> This series adds device-tree nodes for CPSW2G and CPSW9G instance
> of the CPSW Ethernet Switch on TI's J784S4 SoC. Additionally,
> two device-tree overlays are also added:
> 1. QSGMII mode with the CPSW9G instance via the ENET EXPANSION 1
> connector.
> 2. USXGMII mode with MAC Ports 1 and 2 of the CPSW9G instance via
> ENET EXPANSION 1 and 2 connectors, configured in fixed-link
> mode of operation at 5Gbps link speed.
>
> [...]
I have applied the following to branch ti-k3-dts-next on [1].
Thank you!
[1/5] arm64: dts: ti: k3-j784s4-evm: Add alias for MCU CPSW2G
commit: 4670135ec39545e47f2602853dd321bc5f2bc4b7
[2/5] arm64: dts: ti: k3-j784s4-main: Add CPSW2G and CPSW9G nodes
commit: 290b341499fc5c40839141c12d1b4d9cfe4484a6
[3/5] arm64: dts: ti: k3-j784s4-evm: Enable Main CPSW2G node and add aliases for it
commit: 6f2133e6b46b8b499fc23a890756a44c6c434423
[4/5] arm64: dts: ti: k3-j784s4: Add overlay to enable QSGMII mode with CPSW9G
commit: fb55df5a6b69702f79023b93d0c38cc6d749eba3
[5/5] arm64: dts: ti: k3-j784s4: Add overlay for dual port USXGMII mode
commit: 385afb85589e354853234ed68a0600276dcd77ad
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
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^ permalink raw reply [flat|nested] 11+ messages in thread