[PATCH 0/1] arm64/tools/sysreg: Add Sysreg128/SysregFields128

[Anshuman Khandual <anshuman.khandual@arm.com>]

FEAT_SYSREG128 enables 128 bit wide system registers which also need to be
defined in (arch/arm64/toos/sysreg) for auto mask generation. This adds two
new field types i.e Sysreg128 and SysregFields128 for that same purpose. It
utilizes recently added macro GENMASK_U128() while also adding some helpers
such as define_field_128() and parse_bitdef_128().

This patch applies after the following series which adds GENMASK_U128()

https://lore.kernel.org/all/20240725054808.286708-1-anshuman.khandual@arm.com/

A. Example for SysregFields128

------------------------------
SysregFields128 TTBRx_D128_EL1
Res0   127:88
Field  87:80   BADDR_HIGH
Res0   79:64
Field  63:48   ASID
Field  47:5    BADDR_LOW
Res0   4:3
Field  2:1     SKL
Field  0       CnP
EndSysregFields128
------------------------------

The above input generates the following macros

#define TTBRx_D128_EL1_BADDR_HIGH                       GENMASK_U128(87, 80)
#define TTBRx_D128_EL1_BADDR_HIGH_MASK                  GENMASK_U128(87, 80)
#define TTBRx_D128_EL1_BADDR_HIGH_SHIFT                 80
#define TTBRx_D128_EL1_BADDR_HIGH_WIDTH                 8

#define TTBRx_D128_EL1_ASID                             GENMASK_U128(63, 48)
#define TTBRx_D128_EL1_ASID_MASK                        GENMASK_U128(63, 48)
#define TTBRx_D128_EL1_ASID_SHIFT                       48
#define TTBRx_D128_EL1_ASID_WIDTH                       16

#define TTBRx_D128_EL1_BADDR_LOW                        GENMASK_U128(47, 5)
#define TTBRx_D128_EL1_BADDR_LOW_MASK                   GENMASK_U128(47, 5)
#define TTBRx_D128_EL1_BADDR_LOW_SHIFT                  5
#define TTBRx_D128_EL1_BADDR_LOW_WIDTH                  43

#define TTBRx_D128_EL1_SKL                              GENMASK_U128(2, 1)
#define TTBRx_D128_EL1_SKL_MASK                         GENMASK_U128(2, 1)
#define TTBRx_D128_EL1_SKL_SHIFT                        1
#define TTBRx_D128_EL1_SKL_WIDTH                        2

#define TTBRx_D128_EL1_CnP                              GENMASK_U128(0, 0)
#define TTBRx_D128_EL1_CnP_MASK                         GENMASK_U128(0, 0)
#define TTBRx_D128_EL1_CnP_SHIFT                        0
#define TTBRx_D128_EL1_CnP_WIDTH                        1

#define TTBRx_D128_EL1_RES0                             (UL(0) | GENMASK_U128(127, 88) | GENMASK_U128(79, 64) | GENMASK_U128(4, 3))
#define TTBRx_D128_EL1_RES1                             (UL(0))
#define TTBRx_D128_EL1_UNKN                             (UL(0))

B. Example Sysreg128

------------------------------
Sysreg128      TTBR1_D128_EL1  3       0       2       0       1
Res0   127:88
Field  87:80   BADDR_HIGH
Res0   79:64
Field  63:48   ASID
Field  47:5    BADDR_LOW
Res0   4:3
Field  2:1     SKL
Field  0       CnP
EndSysreg128
------------------------------

The above input generates the following macros

#define REG_TTBR1_D128_EL1                              S3_0_C2_C0_1
#define SYS_TTBR1_D128_EL1                              sys_reg(3, 0, 2, 0, 1)
#define SYS_TTBR1_D128_EL1_Op0                          3
#define SYS_TTBR1_D128_EL1_Op1                          0
#define SYS_TTBR1_D128_EL1_CRn                          2
#define SYS_TTBR1_D128_EL1_CRm                          0
#define SYS_TTBR1_D128_EL1_Op2                          1

#define TTBR1_D128_EL1_BADDR_HIGH                       GENMASK_U128(87, 80)
#define TTBR1_D128_EL1_BADDR_HIGH_MASK                  GENMASK_U128(87, 80)
#define TTBR1_D128_EL1_BADDR_HIGH_SHIFT                 80
#define TTBR1_D128_EL1_BADDR_HIGH_WIDTH                 8

#define TTBR1_D128_EL1_ASID                             GENMASK_U128(63, 48)
#define TTBR1_D128_EL1_ASID_MASK                        GENMASK_U128(63, 48)
#define TTBR1_D128_EL1_ASID_SHIFT                       48
#define TTBR1_D128_EL1_ASID_WIDTH                       16

#define TTBR1_D128_EL1_BADDR_LOW                        GENMASK_U128(47, 5)
#define TTBR1_D128_EL1_BADDR_LOW_MASK                   GENMASK_U128(47, 5)
#define TTBR1_D128_EL1_BADDR_LOW_SHIFT                  5
#define TTBR1_D128_EL1_BADDR_LOW_WIDTH                  43

#define TTBR1_D128_EL1_SKL                              GENMASK_U128(2, 1)
#define TTBR1_D128_EL1_SKL_MASK                         GENMASK_U128(2, 1)
#define TTBR1_D128_EL1_SKL_SHIFT                        1
#define TTBR1_D128_EL1_SKL_WIDTH                        2

#define TTBR1_D128_EL1_CnP                              GENMASK_U128(0, 0)
#define TTBR1_D128_EL1_CnP_MASK                         GENMASK_U128(0, 0)
#define TTBR1_D128_EL1_CnP_SHIFT                        0
#define TTBR1_D128_EL1_CnP_WIDTH                        1

#define TTBR1_D128_EL1_RES0                             (UL(0) | GENMASK_U128(127, 88) | GENMASK_U128(79, 64) | GENMASK_U128(4, 3))
#define TTBR1_D128_EL1_RES1                             (UL(0))
#define TTBR1_D128_EL1_UNKN                             (UL(0))

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org

Anshuman Khandual (1):
  arm64/tools/sysreg: Add Sysreg128/SysregFields128

 arch/arm64/tools/gen-sysreg.awk | 231 ++++++++++++++++++++++++++++++++
 1 file changed, 231 insertions(+)

-- 
2.30.2