* [PATCH 2/3] dt-bindings: PCI: renesas,pci-rcar-gen2: add top-level constraints
2024-08-18 17:28 [PATCH 1/3] dt-bindings: PCI: hisilicon,kirin-pcie: add top-level constraints Krzysztof Kozlowski
@ 2024-08-18 17:28 ` Krzysztof Kozlowski
2024-08-19 17:14 ` Rob Herring (Arm)
2024-08-18 17:28 ` [PATCH 3/3] dt-bindings: PCI: socionext,uniphier-pcie-ep: " Krzysztof Kozlowski
` (2 subsequent siblings)
3 siblings, 1 reply; 8+ messages in thread
From: Krzysztof Kozlowski @ 2024-08-18 17:28 UTC (permalink / raw)
To: Xiaowei Song, Binghui Wang, Bjorn Helgaas, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Marek Vasut, Yoshihiro Shimoda,
Kunihiko Hayashi, Masami Hiramatsu, Geert Uytterhoeven,
Magnus Damm, linux-pci, devicetree, linux-kernel,
linux-renesas-soc, linux-arm-kernel
Cc: Krzysztof Kozlowski
Properties with variable number of items per each device are expected to
have widest constraints in top-level "properties:" block and further
customized (narrowed) in "if:then:". Add missing top-level constraints
for clocks and clock-names.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
index b288cdb1ec70..065b7508d288 100644
--- a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
+++ b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
@@ -42,9 +42,13 @@ properties:
interrupts:
maxItems: 1
- clocks: true
+ clocks:
+ minItems: 1
+ maxItems: 3
- clock-names: true
+ clock-names:
+ minItems: 1
+ maxItems: 3
resets:
maxItems: 1
--
2.43.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 2/3] dt-bindings: PCI: renesas,pci-rcar-gen2: add top-level constraints
2024-08-18 17:28 ` [PATCH 2/3] dt-bindings: PCI: renesas,pci-rcar-gen2: " Krzysztof Kozlowski
@ 2024-08-19 17:14 ` Rob Herring (Arm)
0 siblings, 0 replies; 8+ messages in thread
From: Rob Herring (Arm) @ 2024-08-19 17:14 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Krzysztof Wilczyński, Marek Vasut, Yoshihiro Shimoda,
linux-pci, Lorenzo Pieralisi, Conor Dooley, linux-arm-kernel,
Masami Hiramatsu, Xiaowei Song, linux-kernel, Bjorn Helgaas,
Geert Uytterhoeven, linux-renesas-soc, Binghui Wang, devicetree,
Krzysztof Kozlowski, Magnus Damm, Kunihiko Hayashi,
Manivannan Sadhasivam
On Sun, 18 Aug 2024 19:28:42 +0200, Krzysztof Kozlowski wrote:
> Properties with variable number of items per each device are expected to
> have widest constraints in top-level "properties:" block and further
> customized (narrowed) in "if:then:". Add missing top-level constraints
> for clocks and clock-names.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> .../devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 3/3] dt-bindings: PCI: socionext,uniphier-pcie-ep: add top-level constraints
2024-08-18 17:28 [PATCH 1/3] dt-bindings: PCI: hisilicon,kirin-pcie: add top-level constraints Krzysztof Kozlowski
2024-08-18 17:28 ` [PATCH 2/3] dt-bindings: PCI: renesas,pci-rcar-gen2: " Krzysztof Kozlowski
@ 2024-08-18 17:28 ` Krzysztof Kozlowski
2024-08-19 17:14 ` Rob Herring (Arm)
2024-08-21 10:31 ` Kunihiko Hayashi
2024-08-19 17:14 ` [PATCH 1/3] dt-bindings: PCI: hisilicon,kirin-pcie: " Rob Herring (Arm)
2024-09-04 14:37 ` Krzysztof Wilczyński
3 siblings, 2 replies; 8+ messages in thread
From: Krzysztof Kozlowski @ 2024-08-18 17:28 UTC (permalink / raw)
To: Xiaowei Song, Binghui Wang, Bjorn Helgaas, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Marek Vasut, Yoshihiro Shimoda,
Kunihiko Hayashi, Masami Hiramatsu, Geert Uytterhoeven,
Magnus Damm, linux-pci, devicetree, linux-kernel,
linux-renesas-soc, linux-arm-kernel
Cc: Krzysztof Kozlowski
Properties with variable number of items per each device are expected to
have widest constraints in top-level "properties:" block and further
customized (narrowed) in "if:then:". Add missing top-level constraints
for clock-names and reset-names.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../bindings/pci/socionext,uniphier-pcie-ep.yaml | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml
index f0d8e486a07d..93f3d0f4bb94 100644
--- a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml
@@ -38,13 +38,17 @@ properties:
minItems: 1
maxItems: 2
- clock-names: true
+ clock-names:
+ minItems: 1
+ maxItems: 2
resets:
minItems: 1
maxItems: 2
- reset-names: true
+ reset-names:
+ minItems: 1
+ maxItems: 2
num-ib-windows:
const: 16
--
2.43.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 3/3] dt-bindings: PCI: socionext,uniphier-pcie-ep: add top-level constraints
2024-08-18 17:28 ` [PATCH 3/3] dt-bindings: PCI: socionext,uniphier-pcie-ep: " Krzysztof Kozlowski
@ 2024-08-19 17:14 ` Rob Herring (Arm)
2024-08-21 10:31 ` Kunihiko Hayashi
1 sibling, 0 replies; 8+ messages in thread
From: Rob Herring (Arm) @ 2024-08-19 17:14 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Krzysztof Kozlowski, linux-renesas-soc, Lorenzo Pieralisi,
linux-pci, linux-kernel, Marek Vasut, Krzysztof Wilczyński,
Masami Hiramatsu, Binghui Wang, Conor Dooley, Geert Uytterhoeven,
Yoshihiro Shimoda, linux-arm-kernel, Kunihiko Hayashi,
Xiaowei Song, Bjorn Helgaas, Magnus Damm, Manivannan Sadhasivam,
devicetree
On Sun, 18 Aug 2024 19:28:43 +0200, Krzysztof Kozlowski wrote:
> Properties with variable number of items per each device are expected to
> have widest constraints in top-level "properties:" block and further
> customized (narrowed) in "if:then:". Add missing top-level constraints
> for clock-names and reset-names.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> .../bindings/pci/socionext,uniphier-pcie-ep.yaml | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 3/3] dt-bindings: PCI: socionext,uniphier-pcie-ep: add top-level constraints
2024-08-18 17:28 ` [PATCH 3/3] dt-bindings: PCI: socionext,uniphier-pcie-ep: " Krzysztof Kozlowski
2024-08-19 17:14 ` Rob Herring (Arm)
@ 2024-08-21 10:31 ` Kunihiko Hayashi
1 sibling, 0 replies; 8+ messages in thread
From: Kunihiko Hayashi @ 2024-08-21 10:31 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Xiaowei Song, Binghui Wang, Bjorn Helgaas, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Marek Vasut, Yoshihiro Shimoda,
Masami Hiramatsu, Geert Uytterhoeven, Magnus Damm, linux-pci,
devicetree, linux-kernel, linux-renesas-soc, linux-arm-kernel
Hi Krzysztof,
On 2024/08/19 2:28, Krzysztof Kozlowski wrote:
> Properties with variable number of items per each device are expected to
> have widest constraints in top-level "properties:" block and further
> customized (narrowed) in "if:then:". Add missing top-level constraints
> for clock-names and reset-names.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> .../bindings/pci/socionext,uniphier-pcie-ep.yaml | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git
> a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml
> b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml
> index f0d8e486a07d..93f3d0f4bb94 100644
> ---
> a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml
> +++
> b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml
> @@ -38,13 +38,17 @@ properties:
> minItems: 1
> maxItems: 2
>
> - clock-names: true
> + clock-names:
> + minItems: 1
> + maxItems: 2
>
> resets:
> minItems: 1
> maxItems: 2
>
> - reset-names: true
> + reset-names:
> + minItems: 1
> + maxItems: 2
>
> num-ib-windows:
> const: 16
Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
I'd appreciate if it could be applied in devicetree or pci.
Thank you,
---
Best Regards
Kunihiko Hayashi
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/3] dt-bindings: PCI: hisilicon,kirin-pcie: add top-level constraints
2024-08-18 17:28 [PATCH 1/3] dt-bindings: PCI: hisilicon,kirin-pcie: add top-level constraints Krzysztof Kozlowski
2024-08-18 17:28 ` [PATCH 2/3] dt-bindings: PCI: renesas,pci-rcar-gen2: " Krzysztof Kozlowski
2024-08-18 17:28 ` [PATCH 3/3] dt-bindings: PCI: socionext,uniphier-pcie-ep: " Krzysztof Kozlowski
@ 2024-08-19 17:14 ` Rob Herring (Arm)
2024-09-04 14:37 ` Krzysztof Wilczyński
3 siblings, 0 replies; 8+ messages in thread
From: Rob Herring (Arm) @ 2024-08-19 17:14 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Bjorn Helgaas, devicetree, Kunihiko Hayashi, Masami Hiramatsu,
Lorenzo Pieralisi, Xiaowei Song, Manivannan Sadhasivam,
Krzysztof Wilczyński, linux-kernel, Geert Uytterhoeven,
linux-renesas-soc, Krzysztof Kozlowski, Yoshihiro Shimoda,
linux-pci, Marek Vasut, Magnus Damm, Binghui Wang,
linux-arm-kernel, Conor Dooley
On Sun, 18 Aug 2024 19:28:41 +0200, Krzysztof Kozlowski wrote:
> Properties with variable number of items per each device are expected to
> have widest constraints in top-level "properties:" block and further
> customized (narrowed) in "if:then:". Add missing top-level constraints
> for clock-names and reset-names.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> .../devicetree/bindings/pci/hisilicon,kirin-pcie.yaml | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/3] dt-bindings: PCI: hisilicon,kirin-pcie: add top-level constraints
2024-08-18 17:28 [PATCH 1/3] dt-bindings: PCI: hisilicon,kirin-pcie: add top-level constraints Krzysztof Kozlowski
` (2 preceding siblings ...)
2024-08-19 17:14 ` [PATCH 1/3] dt-bindings: PCI: hisilicon,kirin-pcie: " Rob Herring (Arm)
@ 2024-09-04 14:37 ` Krzysztof Wilczyński
3 siblings, 0 replies; 8+ messages in thread
From: Krzysztof Wilczyński @ 2024-09-04 14:37 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Xiaowei Song, Binghui Wang, Bjorn Helgaas, Lorenzo Pieralisi,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Marek Vasut, Yoshihiro Shimoda, Kunihiko Hayashi,
Masami Hiramatsu, Geert Uytterhoeven, Magnus Damm, linux-pci,
devicetree, linux-kernel, linux-renesas-soc, linux-arm-kernel
Hello,
> Properties with variable number of items per each device are expected to
> have widest constraints in top-level "properties:" block and further
> customized (narrowed) in "if:then:". Add missing top-level constraints
> for clock-names and reset-names.
Applied to dt-bindings, thank you!
[01/03] dt-bindings: PCI: hisilicon,kirin-pcie: Add top-level constraints
https://git.kernel.org/pci/pci/c/ac44be2155cd
[02/03] dt-bindings: PCI: renesas,pci-rcar-gen2: Add top-level constraints
https://git.kernel.org/pci/pci/c/c62a0b8fe8bf
[03/03] dt-bindings: PCI: socionext,uniphier-pcie-ep: Add top-level constraints
https://git.kernel.org/pci/pci/c/a5c1bf7e9a46
Krzysztof
^ permalink raw reply [flat|nested] 8+ messages in thread