* [PATCH 1/6] dt-bindings: PCI: dwc: rockchip: Add rk3576 support
2024-12-05 10:36 [PATCH 0/6] Rockchip: add Rockchip rk3576 EVB1 board Kever Yang
@ 2024-12-05 10:36 ` Kever Yang
2024-12-05 11:30 ` Heiko Stübner
2024-12-05 17:05 ` Conor Dooley
2024-12-05 10:36 ` [PATCH 2/6] dts: arm64: rockchip: Add rk3576 naneng combphy nodes Kever Yang
` (4 subsequent siblings)
5 siblings, 2 replies; 11+ messages in thread
From: Kever Yang @ 2024-12-05 10:36 UTC (permalink / raw)
To: heiko
Cc: linux-rockchip, Kever Yang, Bjorn Helgaas, Conor Dooley,
Krzysztof Kozlowski, Krzysztof Wilczyński, Lorenzo Pieralisi,
Manivannan Sadhasivam, Rob Herring, Shawn Lin, Simon Xue,
devicetree, linux-arm-kernel, linux-kernel, linux-pci
rk3576 is using the same controller as rk3568.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
index 550d8a684af3..5328ccad7130 100644
--- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
@@ -26,6 +26,7 @@ properties:
- const: rockchip,rk3568-pcie
- items:
- enum:
+ - rockchip,rk3576-pcie
- rockchip,rk3588-pcie
- const: rockchip,rk3568-pcie
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH 1/6] dt-bindings: PCI: dwc: rockchip: Add rk3576 support
2024-12-05 10:36 ` [PATCH 1/6] dt-bindings: PCI: dwc: rockchip: Add rk3576 support Kever Yang
@ 2024-12-05 11:30 ` Heiko Stübner
2024-12-05 17:05 ` Conor Dooley
1 sibling, 0 replies; 11+ messages in thread
From: Heiko Stübner @ 2024-12-05 11:30 UTC (permalink / raw)
To: Kever Yang
Cc: linux-rockchip, Kever Yang, Bjorn Helgaas, Conor Dooley,
Krzysztof Kozlowski, Krzysztof Wilczyński, Lorenzo Pieralisi,
Manivannan Sadhasivam, Rob Herring, Shawn Lin, Simon Xue,
devicetree, linux-arm-kernel, linux-kernel, linux-pci
Am Donnerstag, 5. Dezember 2024, 11:36:18 CET schrieb Kever Yang:
> rk3576 is using the same controller as rk3568.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> ---
>
> Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
> index 550d8a684af3..5328ccad7130 100644
> --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
> @@ -26,6 +26,7 @@ properties:
> - const: rockchip,rk3568-pcie
> - items:
> - enum:
> + - rockchip,rk3576-pcie
> - rockchip,rk3588-pcie
> - const: rockchip,rk3568-pcie
>
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/6] dt-bindings: PCI: dwc: rockchip: Add rk3576 support
2024-12-05 10:36 ` [PATCH 1/6] dt-bindings: PCI: dwc: rockchip: Add rk3576 support Kever Yang
2024-12-05 11:30 ` Heiko Stübner
@ 2024-12-05 17:05 ` Conor Dooley
1 sibling, 0 replies; 11+ messages in thread
From: Conor Dooley @ 2024-12-05 17:05 UTC (permalink / raw)
To: Kever Yang
Cc: heiko, linux-rockchip, Bjorn Helgaas, Conor Dooley,
Krzysztof Kozlowski, Krzysztof Wilczyński, Lorenzo Pieralisi,
Manivannan Sadhasivam, Rob Herring, Shawn Lin, Simon Xue,
devicetree, linux-arm-kernel, linux-kernel, linux-pci
[-- Attachment #1: Type: text/plain, Size: 227 bytes --]
On Thu, Dec 05, 2024 at 06:36:18PM +0800, Kever Yang wrote:
> rk3576 is using the same controller as rk3568.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 2/6] dts: arm64: rockchip: Add rk3576 naneng combphy nodes
2024-12-05 10:36 [PATCH 0/6] Rockchip: add Rockchip rk3576 EVB1 board Kever Yang
2024-12-05 10:36 ` [PATCH 1/6] dt-bindings: PCI: dwc: rockchip: Add rk3576 support Kever Yang
@ 2024-12-05 10:36 ` Kever Yang
2024-12-05 10:36 ` [PATCH 3/6] dts: arm64: rockchip: Add rk3576 pcie nodes Kever Yang
` (3 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Kever Yang @ 2024-12-05 10:36 UTC (permalink / raw)
To: heiko
Cc: linux-rockchip, Kever Yang, Conor Dooley, Detlev Casanova,
Elaine Zhang, Finley Xiao, Krzysztof Kozlowski, Liang Chen,
Rob Herring, Yifeng Zhao, devicetree, linux-arm-kernel,
linux-kernel
rk3576 has two naneng combo phy,
- combophy0 is used for one of pcie and sata;
- combophy is used for one of pcie, sata and usb3;
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 36 ++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
index 436232ffe4d1..8938ec7c3bb4 100644
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -1587,6 +1587,42 @@ uart11: serial@2afd0000 {
status = "disabled";
};
+ combphy0_ps: phy@2b050000 {
+ compatible = "rockchip,rk3576-naneng-combphy";
+ reg = <0x0 0x2b050000 0x0 0x100>;
+ #phy-cells = <1>;
+ clocks = <&cru CLK_REF_PCIE0_PHY>,
+ <&cru PCLK_PCIE2_COMBOPHY0>,
+ <&cru PCLK_PCIE0>;
+ clock-names = "refclk", "apbclk", "pipe_clk";
+ assigned-clocks = <&cru CLK_REF_PCIE0_PHY>;
+ assigned-clock-rates = <100000000>;
+ resets = <&cru SRST_P_PCIE2_COMBOPHY0>,
+ <&cru SRST_PCIE0_PIPE_PHY>;
+ reset-names = "combphy-apb", "combphy";
+ rockchip,pipe-grf = <&php_grf>;
+ rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
+ status = "disabled";
+ };
+
+ combphy1_psu: phy@2b060000 {
+ compatible = "rockchip,rk3576-naneng-combphy";
+ reg = <0x0 0x2b060000 0x0 0x100>;
+ #phy-cells = <1>;
+ clocks = <&cru CLK_REF_PCIE1_PHY>,
+ <&cru PCLK_PCIE2_COMBOPHY1>,
+ <&cru PCLK_PCIE1>;
+ clock-names = "refclk", "apbclk", "pipe_clk";
+ assigned-clocks = <&cru CLK_REF_PCIE1_PHY>;
+ assigned-clock-rates = <100000000>;
+ resets = <&cru SRST_P_PCIE2_COMBOPHY1>,
+ <&cru SRST_PCIE1_PIPE_PHY>;
+ reset-names = "combphy-apb", "combphy";
+ rockchip,pipe-grf = <&php_grf>;
+ rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
+ status = "disabled";
+ };
+
sram: sram@3ff88000 {
compatible = "mmio-sram";
reg = <0x0 0x3ff88000 0x0 0x78000>;
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 3/6] dts: arm64: rockchip: Add rk3576 pcie nodes
2024-12-05 10:36 [PATCH 0/6] Rockchip: add Rockchip rk3576 EVB1 board Kever Yang
2024-12-05 10:36 ` [PATCH 1/6] dt-bindings: PCI: dwc: rockchip: Add rk3576 support Kever Yang
2024-12-05 10:36 ` [PATCH 2/6] dts: arm64: rockchip: Add rk3576 naneng combphy nodes Kever Yang
@ 2024-12-05 10:36 ` Kever Yang
2024-12-05 10:36 ` [PATCH 4/6] dt-bindings: arm: rockchip: Sort for rk3568 evb Kever Yang
` (2 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Kever Yang @ 2024-12-05 10:36 UTC (permalink / raw)
To: heiko
Cc: linux-rockchip, Kever Yang, Conor Dooley, Detlev Casanova,
Elaine Zhang, Finley Xiao, Krzysztof Kozlowski, Liang Chen,
Rob Herring, devicetree, linux-arm-kernel, linux-kernel
rk3576 has two pcie controller, both are pcie2x1 used with
naneng-combphy.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 111 +++++++++++++++++++++++
1 file changed, 111 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
index 8938ec7c3bb4..888af56530e8 100644
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -1016,6 +1016,117 @@ qos_npu_m1ro: qos@27f22100 {
reg = <0x0 0x27f22100 0x0 0x20>;
};
+ pcie0: pcie@2a200000 {
+ compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
+ bus-range = <0x0 0xf>;
+ clocks = <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>,
+ <&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>,
+ <&cru CLK_PCIE0_AUX>;
+
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux";
+ device_type = "pci";
+ interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "msi", "sys", "pmc", "msg", "legacy", "err";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie0_intc 0>,
+ <0 0 0 2 &pcie0_intc 1>,
+ <0 0 0 3 &pcie0_intc 2>,
+ <0 0 0 4 &pcie0_intc 3>;
+ linux,pci-domain = <0>;
+ num-ib-windows = <8>;
+ num-viewport = <8>;
+ num-ob-windows = <2>;
+ max-link-speed = <2>;
+ num-lanes = <1>;
+ phys = <&combphy0_ps PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+ power-domains = <&power RK3576_PD_PHP>;
+ ranges = <0x00000800 0x0 0x20000000 0x0 0x20000000 0x0 0x00100000
+ 0x81000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00100000
+ 0x82000000 0x0 0x20200000 0x0 0x20200000 0x0 0x00e00000
+ 0x83000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>;
+ reg = <0x0 0x2a200000 0x0 0x00010000>,
+ <0x0 0x22000000 0x0 0x00400000>,
+ <0x0 0x20000000 0x0 0x00100000>;
+ reg-names = "apb", "dbi", "config";
+ resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
+ reset-names = "pipe", "p_pcie0";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ status = "disabled";
+
+ pcie0_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+
+ pcie1: pcie@2a210000 {
+ compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x20 0x2f>;
+ clocks = <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>,
+ <&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>,
+ <&cru CLK_PCIE1_AUX>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux";
+ device_type = "pci";
+ interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "msi", "sys", "pmc", "msg", "legacy", "err";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie1_intc 0>,
+ <0 0 0 2 &pcie1_intc 1>,
+ <0 0 0 3 &pcie1_intc 2>,
+ <0 0 0 4 &pcie1_intc 3>;
+ linux,pci-domain = <0>;
+ num-ib-windows = <8>;
+ num-viewport = <8>;
+ num-ob-windows = <2>;
+ max-link-speed = <2>;
+ num-lanes = <1>;
+ phys = <&combphy1_psu PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+ power-domains = <&power RK3576_PD_SUBPHP>;
+ ranges = <0x00000800 0x0 0x21000000 0x0 0x21000000 0x0 0x00100000
+ 0x81000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00100000
+ 0x82000000 0x0 0x21200000 0x0 0x21200000 0x0 0x00e00000
+ 0x83000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>;
+ reg = <0x0 0x2a210000 0x0 0x00010000>,
+ <0x0 0x22400000 0x0 0x00400000>,
+ <0x0 0x21000000 0x0 0x00100000>;
+ reg-names = "apb", "dbi", "config";
+ resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
+ reset-names = "pipe", "p_pcie1";
+ status = "disabled";
+
+ pcie1_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+
gmac0: ethernet@2a220000 {
compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a";
reg = <0x0 0x2a220000 0x0 0x10000>;
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 4/6] dt-bindings: arm: rockchip: Sort for rk3568 evb
2024-12-05 10:36 [PATCH 0/6] Rockchip: add Rockchip rk3576 EVB1 board Kever Yang
` (2 preceding siblings ...)
2024-12-05 10:36 ` [PATCH 3/6] dts: arm64: rockchip: Add rk3576 pcie nodes Kever Yang
@ 2024-12-05 10:36 ` Kever Yang
2024-12-05 17:14 ` Conor Dooley
2024-12-05 10:36 ` [PATCH 5/6] dt-bindings: arm: rockchip: Add rk3576 evb1 board Kever Yang
2024-12-05 10:36 ` [PATCH 6/6] arm64: dts: " Kever Yang
5 siblings, 1 reply; 11+ messages in thread
From: Kever Yang @ 2024-12-05 10:36 UTC (permalink / raw)
To: heiko
Cc: linux-rockchip, Kever Yang, Andy Yan, Chris Morgan, Conor Dooley,
Dragan Simic, Jonas Karlman, Krzysztof Kozlowski, Rob Herring,
Tim Lunn, devicetree, linux-arm-kernel, linux-kernel
The info for rk3568 should before rk3588.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
.../devicetree/bindings/arm/rockchip.yaml | 20 +++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index 753199a12923..45ee4bf7c80c 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -1006,6 +1006,16 @@ properties:
- const: rockchip,rk3399-sapphire-excavator
- const: rockchip,rk3399
+ - description: Rockchip RK3566 BOX Evaluation Demo board
+ items:
+ - const: rockchip,rk3566-box-demo
+ - const: rockchip,rk3566
+
+ - description: Rockchip RK3568 Evaluation board
+ items:
+ - const: rockchip,rk3568-evb1-v10
+ - const: rockchip,rk3568
+
- description: Rockchip RK3588 Evaluation board
items:
- const: rockchip,rk3588-evb1-v10
@@ -1099,16 +1109,6 @@ properties:
- const: zkmagic,a95x-z2
- const: rockchip,rk3318
- - description: Rockchip RK3566 BOX Evaluation Demo board
- items:
- - const: rockchip,rk3566-box-demo
- - const: rockchip,rk3566
-
- - description: Rockchip RK3568 Evaluation board
- items:
- - const: rockchip,rk3568-evb1-v10
- - const: rockchip,rk3568
-
- description: Sinovoip RK3308 Banana Pi P2 Pro
items:
- const: sinovoip,rk3308-bpi-p2pro
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH 4/6] dt-bindings: arm: rockchip: Sort for rk3568 evb
2024-12-05 10:36 ` [PATCH 4/6] dt-bindings: arm: rockchip: Sort for rk3568 evb Kever Yang
@ 2024-12-05 17:14 ` Conor Dooley
0 siblings, 0 replies; 11+ messages in thread
From: Conor Dooley @ 2024-12-05 17:14 UTC (permalink / raw)
To: Kever Yang
Cc: heiko, linux-rockchip, Andy Yan, Chris Morgan, Conor Dooley,
Dragan Simic, Jonas Karlman, Krzysztof Kozlowski, Rob Herring,
Tim Lunn, devicetree, linux-arm-kernel, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 222 bytes --]
On Thu, Dec 05, 2024 at 06:36:21PM +0800, Kever Yang wrote:
> The info for rk3568 should before rk3588.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 5/6] dt-bindings: arm: rockchip: Add rk3576 evb1 board
2024-12-05 10:36 [PATCH 0/6] Rockchip: add Rockchip rk3576 EVB1 board Kever Yang
` (3 preceding siblings ...)
2024-12-05 10:36 ` [PATCH 4/6] dt-bindings: arm: rockchip: Sort for rk3568 evb Kever Yang
@ 2024-12-05 10:36 ` Kever Yang
2024-12-05 17:14 ` Conor Dooley
2024-12-05 10:36 ` [PATCH 6/6] arm64: dts: " Kever Yang
5 siblings, 1 reply; 11+ messages in thread
From: Kever Yang @ 2024-12-05 10:36 UTC (permalink / raw)
To: heiko
Cc: linux-rockchip, Kever Yang, Andy Yan, Chris Morgan, Conor Dooley,
Dragan Simic, Jonas Karlman, Krzysztof Kozlowski, Rob Herring,
Tim Lunn, devicetree, linux-arm-kernel, linux-kernel
Add device tree documentation for rk3576-evb1-v10.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index 45ee4bf7c80c..b2681a45867b 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -1016,6 +1016,11 @@ properties:
- const: rockchip,rk3568-evb1-v10
- const: rockchip,rk3568
+ - description: Rockchip RK3576 Evaluation board
+ items:
+ - const: rockchip,rk3576-evb1-v10
+ - const: rockchip,rk3576
+
- description: Rockchip RK3588 Evaluation board
items:
- const: rockchip,rk3588-evb1-v10
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH 5/6] dt-bindings: arm: rockchip: Add rk3576 evb1 board
2024-12-05 10:36 ` [PATCH 5/6] dt-bindings: arm: rockchip: Add rk3576 evb1 board Kever Yang
@ 2024-12-05 17:14 ` Conor Dooley
0 siblings, 0 replies; 11+ messages in thread
From: Conor Dooley @ 2024-12-05 17:14 UTC (permalink / raw)
To: Kever Yang
Cc: heiko, linux-rockchip, Andy Yan, Chris Morgan, Conor Dooley,
Dragan Simic, Jonas Karlman, Krzysztof Kozlowski, Rob Herring,
Tim Lunn, devicetree, linux-arm-kernel, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 229 bytes --]
On Thu, Dec 05, 2024 at 06:36:22PM +0800, Kever Yang wrote:
> Add device tree documentation for rk3576-evb1-v10.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 6/6] arm64: dts: rockchip: Add rk3576 evb1 board
2024-12-05 10:36 [PATCH 0/6] Rockchip: add Rockchip rk3576 EVB1 board Kever Yang
` (4 preceding siblings ...)
2024-12-05 10:36 ` [PATCH 5/6] dt-bindings: arm: rockchip: Add rk3576 evb1 board Kever Yang
@ 2024-12-05 10:36 ` Kever Yang
5 siblings, 0 replies; 11+ messages in thread
From: Kever Yang @ 2024-12-05 10:36 UTC (permalink / raw)
To: heiko
Cc: linux-rockchip, Kever Yang, Liang Chen, Alexey Charkov, Andy Yan,
Chris Morgan, Conor Dooley, Detlev Casanova, Dragan Simic,
FUKAUMI Naoki, Jonas Karlman, Krzysztof Kozlowski, Michael Riesch,
Rob Herring, devicetree, linux-arm-kernel, linux-kernel
RK3576 EVB1 board features:
- Rockchip RK3576
- PMIC: RK806-2x2pcs+DiscretePower
- RAM: LPDDR4/4x 2pcsx 32bit
- ROM: eMMC5.1 + UFS
- LAN x 2
- HDMI TX
- SD card slot
- PCIe2 slot
Add support for pmic, eMMC, SD-card, ADC-KEY, PCIE and GMAC.
NOTE: The board has a mux design for PCIe slot and USB3 host, and
default state is switch to USB3, need to switch to PCIe side to enable
the PCIe slot.
Signed-off-by: Liang Chen <cl@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
arch/arm64/boot/dts/rockchip/Makefile | 1 +
.../boot/dts/rockchip/rk3576-evb1-v10.dts | 699 ++++++++++++++++++
2 files changed, 700 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 86cc418a2255..2e683d7eab58 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -129,6 +129,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-display-vz.dtbo
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-io-expander.dtbo
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-armsom-sige5.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-sige7.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-w3.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-coolpi-cm5-evb.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts
new file mode 100644
index 000000000000..2b18bc1a4b72
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts
@@ -0,0 +1,699 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3576.dtsi"
+
+/ {
+ model = "Rockchip RK3576 EVB V10 Board";
+ compatible = "rockchip,rk3576-evb1-v10", "rockchip,rk3576";
+
+ aliases {
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ };
+
+ chosen: chosen {
+ stdout-path = "serial0:1500000n8";
+ };
+
+ adc_keys: adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <100>;
+
+ vol-up-key {
+ label = "volume up";
+ linux,code = <KEY_VOLUMEUP>;
+ press-threshold-microvolt = <17000>;
+ };
+
+ vol-down-key {
+ label = "volume down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ press-threshold-microvolt = <417000>;
+ };
+
+ menu-key {
+ label = "menu";
+ linux,code = <KEY_MENU>;
+ press-threshold-microvolt = <890000>;
+ };
+
+ back-key {
+ label = "back";
+ linux,code = <KEY_BACK>;
+ press-threshold-microvolt = <1235000>;
+ };
+ };
+
+ leds: leds {
+ compatible = "gpio-leds";
+ work_led: work {
+ gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ vcc12v_dcin: regulator-vcc12v-dcin {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc_sys: regulator-vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc5v0_device: regulator-vcc5v0-device {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_device";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_2v0_pldo_s3";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ vin-supply = <&vcc_sys>;
+ };
+
+ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v1_nldo_s3";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&vcc_sys>;
+ };
+
+ vcc3v3_rtc_s5: regulator-vcc3v3-rtc-s5 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_rtc_s5";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_sys>;
+ };
+
+ vcc_1v8_s0: regulator-vcc-1v8-s0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v8_s0";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_1v8_s3>;
+ };
+
+ vcc_3v3_s0: regulator-vcc-3v3-s0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3_s0";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_3v3_s3>;
+ };
+
+ vcc_ufs_s0: regulator-vcc-ufs-s0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_ufs_s0";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_sys>;
+ };
+
+ vcc1v8_ufs_vccq2_s0: regulator-vcc1v8-ufs-vccq2-s0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v8_ufs_vccq2_s0";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_1v8_s3>;
+ };
+
+ vcc1v2_ufs_vccq_s0: regulator-vcc1v2-ufs-vccq-s0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v2_ufs_vccq_s0";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ vin-supply = <&vcc_sys>;
+ };
+
+ vcc3v3_lcd_n: regulator-vcc3v3-lcd0-n {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_lcd0_n";
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&vcc_3v3_s0>;
+ };
+
+ vcc3v3_pcie0: regulator-vcc3v3-pcie0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pcie1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <5000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc5v0_host: regulator-vcc5v0-host {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_host";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&vcc5v0_device>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_host_pwren>;
+ };
+
+ vbus5v0_typec: regulator-vbus5v0-typec {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus5v0_typec";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio0 RK_PD1 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&vcc5v0_device>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_otg0_pwren>;
+ };
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_big_s0>;
+};
+
+&combphy1_psu {
+ status = "okay";
+};
+
+&gmac0 {
+ phy-mode = "rgmii-rxid";
+ clock_in_out = "output";
+
+ snps,reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 20000 100000>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <ð0m0_miim
+ ð0m0_tx_bus2
+ ð0m0_rx_bus2
+ ð0m0_rgmii_clk
+ ð0m0_rgmii_bus
+ ðm0_clk0_25m_out>;
+
+ tx_delay = <0x21>;
+
+ phy-handle = <&rgmii_phy0>;
+ status = "okay";
+};
+
+&gmac1 {
+ phy-mode = "rgmii-rxid";
+ clock_in_out = "output";
+
+ snps,reset-gpio = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 20000 100000>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <ð1m0_miim
+ ð1m0_tx_bus2
+ ð1m0_rx_bus2
+ ð1m0_rgmii_clk
+ ð1m0_rgmii_bus
+ ðm0_clk1_25m_out>;
+
+ tx_delay = <0x20>;
+
+ phy-handle = <&rgmii_phy1>;
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+
+ rk806: pmic@23 {
+ compatible = "rockchip,rk806";
+ reg = <0x23>;
+
+ interrupt-parent = <&gpio0>;
+ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+
+ system-power-controller;
+
+
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc5-supply = <&vcc_sys>;
+ vcc6-supply = <&vcc_sys>;
+ vcc7-supply = <&vcc_sys>;
+ vcc8-supply = <&vcc_sys>;
+ vcc9-supply = <&vcc_sys>;
+ vcc10-supply = <&vcc_sys>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc_sys>;
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
+ vcc14-supply = <&vcc_1v1_nldo_s3>;
+ vcca-supply = <&vcc_sys>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ rk806_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs1_slp: dvs1-slp-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun1";
+ };
+
+ rk806_dvs1_pwrdn: dvs1-pwrdn-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun2";
+ };
+
+ rk806_dvs1_rst: dvs1-rst-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun3";
+ };
+
+ rk806_dvs2_slp: dvs2-slp-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun1";
+ };
+
+ rk806_dvs2_pwrdn: dvs2-pwrdn-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun2";
+ };
+
+ rk806_dvs2_rst: dvs2-rst-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun3";
+ };
+
+ rk806_dvs2_dvs: dvs2-dvs-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun4";
+ };
+
+ rk806_dvs2_gpio: dvs2-gpio-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun5";
+ };
+
+ rk806_dvs3_slp: dvs3-slp-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun1";
+ };
+
+ rk806_dvs3_pwrdn: dvs3-pwrdn-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun2";
+ };
+
+ rk806_dvs3_rst: dvs3-rst-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun3";
+ };
+
+ rk806_dvs3_dvs: dvs3-dvs-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun4";
+ };
+
+ rk806_dvs3_gpio: dvs3-gpio-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun5";
+ };
+
+ regulators {
+ vdd_cpu_big_s0: dcdc-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-init-microvolt = <850000>;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_cpu_big_s0";
+ regulator-enable-ramp-delay = <400>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_npu_s0: dcdc-reg2 {
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_npu_s0";
+ regulator-enable-ramp-delay = <400>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_s0: dcdc-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-init-microvolt = <850000>;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_cpu_lit_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vcc_3v3_s3: dcdc-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_3v3_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vdd_gpu_s0: dcdc-reg5 {
+ regulator-boot-on;
+ regulator-init-microvolt = <750000>;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <900000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_gpu_s0";
+ regulator-enable-ramp-delay = <400>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ vddq_ddr_s0: dcdc-reg6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vddq_ddr_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_logic_s0: dcdc-reg7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-init-microvolt = <750000>;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <800000>;
+ regulator-name = "vdd_logic_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s3: dcdc-reg8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd2_ddr_s3: dcdc-reg9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vdd2_ddr_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_ddr_s0: dcdc-reg10 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vdd_ddr_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca_1v8_s0: pldo-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcca_1v8_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pldo2_s0: pldo-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcca1v8_pldo2_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_1v2_s0: pldo-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vdda_1v2_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca_3v3_s0: pldo-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcca_3v3_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd_s0: pldo-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_sd_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pldo6_s3: pldo-reg6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcca1v8_pldo6_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_s3: nldo-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "vdd_0v75_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdda_ddr_pll_s0: nldo-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-name = "vdda_ddr_pll_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v75_hdmi_s0: nldo-reg3 {
+ regulator-boot-on;
+ regulator-min-microvolt = <837500>;
+ regulator-max-microvolt = <837500>;
+ regulator-name = "vdda0v75_hdmi_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v85_s0: nldo-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-name = "vdda_0v85_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v75_s0: nldo-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "vdda_0v75_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&mdio0 {
+ rgmii_phy0: phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x1>;
+ clocks = <&cru REFCLKO25M_GMAC0_OUT>;
+ };
+};
+
+&mdio1 {
+ rgmii_phy1: phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x1>;
+ clocks = <&cru REFCLKO25M_GMAC1_OUT>;
+ };
+};
+
+&pinctrl {
+ usb {
+ usb_host_pwren: usb-host-pwren {
+ rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ usb_otg0_pwren: usb-otg0-pwren {
+ rockchip,pins = <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ usbc0_int: usbc0-int {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&sdmmc {
+ max-frequency = <200000000>;
+ no-sdio;
+ no-mmc;
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ sd-uhs-sdr104;
+ vqmmc-supply = <&vccio_sd_s0>;
+ status = "okay";
+};
+
+&pcie1 {
+ reset-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie0>;
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vcca_1v8_s0>;
+};
+
+&uart0 {
+ status = "okay";
+};
--
2.25.1
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