[PATCH v18 0/5] iommu/arm-smmu: introduction of ACTLR implementation for Qualcomm SoCs

[PATCH v18 0/5] iommu/arm-smmu: introduction of ACTLR implementation for Qualcomm SoCs

[Bibek Kumar Patro]

This patch series consist of six parts and covers the following:

1. Provide option to re-enable context caching to retain prefetcher
   settings during reset and runtime suspend.

2. Remove cfg inside qcom_smmu structure and replace it with single
   pointer to qcom_smmu_match_data avoiding replication of multiple
   members from same.

3. Add support for ACTLR PRR bit setup via adreno-smmu-priv interface.

4. Introduce intital set of driver changes to implement ACTLR register
   for custom prefetcher settings in Qualcomm SoCs.

5. Add ACTLR data and support for qcom_smmu_500.

Changes in v18 from v17_RESEND:
 - 1/5 : No changes
 - 2/5 : No changes - reviewed-by tags collected
 - 3/5 : Addition of
   pm_runtime_resume_and_get()/pm_runtime_put_autosuspend()
   around register access of PRR related private interfaces
   as discussed in v17_RESEND.
 - 4/5, 5/5 : No changes - reviewed-by tags collected
 Link to v17_RESEND:
 https://lore.kernel.org/all/20241114160721.1527934-1-quic_bibekkum@quicinc.com/

Resend of v17:
 Addition of minor fix of the build warning reported by kernel test robot [1] by powerpc_random config [2].
 [1]:https://lore.kernel.org/all/202411140748.6mcFdJdO-lkp@intel.com/#t
 [2]:https://download.01.org/0day-ci/archive/20241114/202411140748.6mcFdJdO-lkp@intel.com/config

Changes in v17 from v16:
 Tags provided earlier not collected yet on patch 1/5, 3/5, 4/5, 5/5
 due to the following revisions:
 - 1/5 : Move the CPRE workaround out of qualcomm specific logic and gate with config
         , update the silicon-errata.rst file
 - 2/5 : No changes - reviewed-by tags collected
 - 3/5 : Move the compatible check before assignment of callback as suggested.
 - 4/5 : Add the actlr setting for *adreno variant* of MMU-500 as well.
 - 5/5 : Due to changes in 1/5, minor refactoring had to be done before adding table.
 Link to v16:
 https://lore.kernel.org/all/20241008125410.3422512-1-quic_bibekkum@quicinc.com/

Changes in v16 from v15:
 - Incorporate Dimitry's suggestion on patch 4/5 to use dev_dbg instead of dev_notice.
 - Fix kernel test robot warning [1] coming for 32bit architecture configuration.
 - Updatingthe tags
 [1]: https://lore.kernel.org/all/202409230343.Q8KnYl2w-lkp@intel.com/
 Link to v15:
 https://lore.kernel.org/all/20240920155813.3434021-1-quic_bibekkum@quicinc.com/

Changes in v15 from v14:
 - As discussed with Robin and Dmitry modify the actlr table and logic to use
   compatible string instead of sid, mask for device matching which is
   similar to qcom_smmu_client_of_match mechanism.
 - Expand the comment in qcom_smmu500_reset to document reason why CPRE bit is re-enabled again
   after arm_mmu500_reset resets the bit.
 - Rearrange the series in order to keep prefetch setting patches in the end.
 Link to v14:
 https://lore.kernel.org/all/20240816174259.2056829-1-quic_bibekkum@quicinc.com/

Changes in v14 from v13:
 Patch 6/6:
 - As discussed incorprate changes to carry out PRR implementation only for
   targets based on MMU-500 by using compat string based SMMU version detection.
 - Split the set_actlr interface into two separate interface namely set_prr_bit
   and set_prr_addr to set the prr enable bit and prr page address resepectively.
 Patch 3/6:
  - Fix a bug in gfx actlr_config which is uncovered while testing the gfx actlr setting in sc7280
    during PRR experiment which prevented clients on certain sids of gfx smmmu to be skipped during
    setting up of the ACTLR values : Fix involves swapping the arguments passed in smr_is_subset to make
     device smr <from devicetree> a subset of actlr_config table entries < defined in the driver>.
 Patch 4/6, 5/6:
  - Sort the actlr table values in increasing order of the SIDs.
 Link to v13:
 https://lore.kernel.org/all/20240628140435.1652374-1-quic_bibekkum@quicinc.com/

Changes in v13 from v12:
 - Fix the compilation issues reported by kernel test robot [1].
 [1]: https://lore.kernel.org/all/202406281241.xEX0TWjt-lkp@intel.com/#t
 Link to v12:
 https://lore.kernel.org/all/20240626143020.3682243-1-quic_bibekkum@quicinc.com/

Changes in v12 from v11:
 Changes to incorporate suggestion from Rob:
 - Fix the set and reset logic for prr bit as pointed out in v11-6/6.
 - Rename set_actlr_bit function name to set_prr.
 - Add extension for PRR name as Partially-Resident-Region in comments
   for set_prr function.
 - Add few missing sids for sc7280 in patch-5/6.
 Link to v11:
 https://lore.kernel.org/all/20240605121713.3596499-1-quic_bibekkum@quicinc.com/

Changes in v11 from v10:
 - Include a new patch 6/6 to add support for ACTLR PRR bit
   through adreno-smmu-priv interface as suggested by Rob and Dmitry.
 Link to v10:
 https://lore.kernel.org/all/20240524131800.2288259-1-quic_bibekkum@quicinc.com/

Changes in v10 from v9:
 - Added reviewed-by tags 1/5,2/5,3/5.
 Changes incorporated:
 - Remove redundant PRR bit setting from gfx actlr table(patch 4/5,5/5)
   as this bit needs special handling in the gfx driver along with
   the associated register settings.
 Link to discussion on PRR bit:
 https://lore.kernel.org/all/f2222714-1e00-424e-946d-c314d55541b8@quicinc.com/
 Link to v9:
 https://lore.kernel.org/all/20240123144543.9405-1-quic_bibekkum@quicinc.com/

Changes in v9 from v8:
 Changes to incorporate suggestions from Konrad as follows:
 - Re-wrap struct members of actlr_variant in patch 4/5,5/5
   in a cleaner way.
 - Move actlr_config members to the header.
 Link to v8:
 https://lore.kernel.org/all/20240116150411.23876-1-quic_bibekkum@quicinc.com/

Changes in v8 from v7:
 - Added reviewed-by tags on patch 1/5, 2/5.
 Changes to incorporate suggestions from Pavan and Konrad:
 - Remove non necessary extra lines.
 - Use num_smmu and num_actlrcfg to store the array size and use the
   same to traverse the table and save on sentinel space along with
   indentation levels.
 - Refactor blocks containing qcom_smmu_set_actlr to remove block
   repetition in patch 3/5.
 - Change copyright year from 2023 to 2022-2023 in patch 3/5.
 - Modify qcom_smmu_match_data.actlrvar and actlr_variant.actlrcfg to
   const pointer to a const resource.
 - use C99 designated initializers and put the address first.
 Link to v7:
 https://lore.kernel.org/all/20240109114220.30243-1-quic_bibekkum@quicinc.com/

Changes in v7 from v6:
 Changes to incorporate suggestions from Dmitry as follows:
 - Use io_start address instead of compatible string to identify the
   correct instance by comparing with smmu start address and check for
   which smmu the corresponding actlr table is to be picked.
Link to v6:
https://lore.kernel.org/all/20231220133808.5654-1-quic_bibekkum@quicinc.com/

Changes in v6 from v5:
 - Remove extra Suggested-by tags.
 - Add return check for arm_mmu500_reset in 1/5 as discussed.
Link to v5:
https://lore.kernel.org/all/20231219135947.1623-1-quic_bibekkum@quicinc.com/

Changes in v5 from v4:
 New addition:
 - Modify copyright year in arm-smmu-qcom.h to 2023 from 2022.
 Changes to incorporate suggestions from Dmitry as follows:
 - Modify the defines for prefetch in (foo << bar) format
   as suggested.(FIELD_PREP could not be used in defines
   is not inside any block/function)
 Changes to incorporate suggestions from Konrad as follows:
 - Shift context caching enablement patch as 1/5 instead of 5/5 to
   be picked up as independent patch.
 - Fix the codestyle to orient variables in reverse xmas tree format
   for patch 1/5.
 - Fix variable name in patch 1/5 as suggested.
 Link to v4:
https://lore.kernel.org/all/20231215101827.30549-1-quic_bibekkum@quicinc.com/

Changes in v4 from v3:
 New addition:
 - Remove actlrcfg_size and use NULL end element instead to traverse
   the actlr table, as this would be a cleaner approach by removing
   redundancy of actlrcfg_size.
 - Renaming of actlr set function to arm_smmu_qcom based proprietary
   convention.
 - break from loop once sid is found and ACTLR value is initialized
   in qcom_smmu_set_actlr.
 - Modify the GFX prefetch value separating into 2 sensible defines.
 - Modify comments for prefetch defines as per SMMU-500 TRM.
 Changes to incorporate suggestions from Konrad as follows:
 - Use Reverse-Christmas-tree sorting wherever applicable.
 - Pass arguments directly to arm_smmu_set_actlr instead of creating
   duplicate variables.
 - Use array indexing instead of direct pointer addressed by new
   addition of eliminating actlrcfg_size.
 - Switch the HEX value's case from upper to lower case in SC7280
   actlrcfg table.
 Changes to incorporate suggestions from Dmitry as follows:
 - Separate changes not related to ACTLR support to different commit
   with patch 5/5.
 - Using pointer to struct for arguments in smr_is_subset().
 Changes to incorporate suggestions from Bjorn as follows:
 - fix the commit message for patch 2/5 to properly document the
   value space to avoid confusion.
 Fixed build issues reported by kernel test robot [1] for
 arm64-allyesconfig [2].
 [1]: https://lore.kernel.org/all/202312011750.Pwca3TWE-lkp@intel.com/
 [2]:
https://download.01.org/0day-ci/archive/20231201/202312011750.Pwca3TWE-lkp@intel.com/config
 Link to v3:
https://lore.kernel.org/all/20231127145412.3981-1-quic_bibekkum@quicinc.com/

Changes in v3 from v2:
 New addition:
 - Include patch 3/4 for adding ACTLR support and data for SC7280.
 - Add driver changes for actlr support in gpu smmu.
 - Add target wise actlr data and implementation ops for gpu smmu.
 Changes to incorporate suggestions from Robin as follows:
 - Match the ACTLR values with individual corresponding SID instead
   of assuming that any SMR will be programmed to match a superset of
   the data.
 - Instead of replicating each elements from qcom_smmu_match_data to
   qcom_smmu structre during smmu device creation, replace the
   replicated members with qcom_smmu_match_data structure inside
   qcom_smmu structre and handle the dereference in places that
   requires them.
 Changes to incorporate suggestions from Dmitry and Konrad as follows:
 - Maintain actlr table inside a single structure instead of
   nested structure.
 - Rename prefetch defines to more appropriately describe their
   behavior.
 - Remove SM8550 specific implementation ops and roll back to default
   qcom_smmu_500_impl implementation ops.
 - Add back the removed comments which are NAK.
 - Fix commit description for patch 4/4.
 Link to v2:
https://lore.kernel.org/all/20231114135654.30475-1-quic_bibekkum@quicinc.com/

Changes in v2 from v1:
 - Incorporated suggestions on v1 from Dmitry,Konrad,Pratyush.
 - Added defines for ACTLR values.
 - Linked sm8550 implementation structure to corresponding
   compatible string.
 - Repackaged actlr value set implementation to separate function.
 - Fixed indentation errors.
 - Link to v1:
https://lore.kernel.org/all/20231103215124.1095-1-quic_bibekkum@quicinc.com/

Changes in v1 from RFC:
 - Incorporated suggestion form Robin on RFC
 - Moved the actlr data table into driver, instead of maintaining
   it inside soc specific DT and piggybacking on exisiting iommus
   property (iommu = <SID, MASK, ACTLR>) to set this value during
   smmu probe.
 - Link to RFC:
https://lore.kernel.org/all/a01e7e60-6ead-4a9e-ba90-22a8a6bbd03f@quicinc.com/

Bibek Kumar Patro (5):
  iommu/arm-smmu: re-enable context caching in smmu reset operation
  iommu/arm-smmu: refactor qcom_smmu structure to include single pointer
  iommu/arm-smmu: add support for PRR bit setup
  iommu/arm-smmu: introduction of ACTLR for custom prefetcher settings
  iommu/arm-smmu: add ACTLR data and support for qcom_smmu_500

 Documentation/arch/arm64/silicon-errata.rst   |   3 +-
 drivers/iommu/Kconfig                         |  12 ++
 drivers/iommu/arm/arm-smmu/arm-smmu-impl.c    |   5 +-
 .../iommu/arm/arm-smmu/arm-smmu-qcom-debug.c  |   2 +-
 drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c    | 120 +++++++++++++++++-
 drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h    |   3 +-
 drivers/iommu/arm/arm-smmu/arm-smmu.h         |   2 +
 include/linux/adreno-smmu-priv.h              |  14 ++
 8 files changed, 155 insertions(+), 6 deletions(-)

--
2.34.1

[PATCH v18 1/5] iommu/arm-smmu: re-enable context caching in smmu reset operation

[Bibek Kumar Patro]

Default MMU-500 reset operation disables context caching in
prefetch buffer. It is however expected for context banks using
the ACTLR register to retain their prefetch value during reset
and runtime suspend.

Add config 'ARM_SMMU_MMU_500_CPRE_ERRATA' to gate this errata
workaround in default MMU-500 reset operation which defaults to
'Y' and provide option to disable workaround for context caching
in prefetch buffer as and when needed.

Suggested-by: Will Deacon <will@kernel.org>
Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
---
 Documentation/arch/arm64/silicon-errata.rst |  3 ++-
 drivers/iommu/Kconfig                       | 12 ++++++++++++
 drivers/iommu/arm/arm-smmu/arm-smmu-impl.c  |  5 +++--
 3 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst
index 65bfab1b1861..92207d55fd1c 100644
--- a/Documentation/arch/arm64/silicon-errata.rst
+++ b/Documentation/arch/arm64/silicon-errata.rst
@@ -198,7 +198,8 @@ stable kernels.
 +----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Neoverse-V3     | #3312417        | ARM64_ERRATUM_3194386       |
 +----------------+-----------------+-----------------+-----------------------------+
-| ARM            | MMU-500         | #841119,826419  | N/A                         |
+| ARM            | MMU-500         | #841119,826419  | ARM_SMMU_MMU_500_CPRE_ERRATA|
+|                |                 | #562869,1047329 |                             |
 +----------------+-----------------+-----------------+-----------------------------+
 | ARM            | MMU-600         | #1076982,1209401| N/A                         |
 +----------------+-----------------+-----------------+-----------------------------+
diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
index ade4e8cf2a3e..90ba5818af81 100644
--- a/drivers/iommu/Kconfig
+++ b/drivers/iommu/Kconfig
@@ -367,6 +367,18 @@ config ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT
 	  'arm-smmu.disable_bypass' will continue to override this
 	  config.

+config ARM_SMMU_MMU_500_CPRE_ERRATA
+	bool "Enable errata workaround for CPRE in SMMU reset path"
+	depends on ARM_SMMU
+	default y
+	help
+	  Say Y here (by default) to apply workaround to disable
+	  MMU-500's next-page prefetcher for sake of 4 known errata.
+
+	  Say N here only when it is sure that any errata related to
+	  prefetch enablement are not applicable on the platform.
+	  Refer silicon-errata.rst for info on errata IDs.
+
 config ARM_SMMU_QCOM
 	def_tristate y
 	depends on ARM_SMMU && ARCH_QCOM
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
index 99030e6b16e7..db9b9a8e139c 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
@@ -110,7 +110,6 @@ static struct arm_smmu_device *cavium_smmu_impl_init(struct arm_smmu_device *smm
 int arm_mmu500_reset(struct arm_smmu_device *smmu)
 {
 	u32 reg, major;
-	int i;
 	/*
 	 * On MMU-500 r2p0 onwards we need to clear ACR.CACHE_LOCK before
 	 * writes to the context bank ACTLRs will stick. And we just hope that
@@ -128,11 +127,12 @@ int arm_mmu500_reset(struct arm_smmu_device *smmu)
 	reg |= ARM_MMU500_ACR_SMTNMB_TLBEN | ARM_MMU500_ACR_S2CRB_TLBEN;
 	arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sACR, reg);

+#ifdef CONFIG_ARM_SMMU_MMU_500_CPRE_ERRATA
 	/*
 	 * Disable MMU-500's not-particularly-beneficial next-page
 	 * prefetcher for the sake of at least 5 known errata.
 	 */
-	for (i = 0; i < smmu->num_context_banks; ++i) {
+	for (int i = 0; i < smmu->num_context_banks; ++i) {
 		reg = arm_smmu_cb_read(smmu, i, ARM_SMMU_CB_ACTLR);
 		reg &= ~ARM_MMU500_ACTLR_CPRE;
 		arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_ACTLR, reg);
@@ -140,6 +140,7 @@ int arm_mmu500_reset(struct arm_smmu_device *smmu)
 		if (reg & ARM_MMU500_ACTLR_CPRE)
 			dev_warn_once(smmu->dev, "Failed to disable prefetcher for errata workarounds, check SACR.CACHE_LOCK\n");
 	}
+#endif

 	return 0;
 }
--
2.34.1

[PATCH v18 2/5] iommu/arm-smmu: refactor qcom_smmu structure to include single pointer

[Bibek Kumar Patro]

qcom_smmu_match_data is static and constant so refactor qcom_smmu
to store single pointer to qcom_smmu_match_data instead of
replicating multiple child members of the same and handle the further
dereferences in the places that want them.

Suggested-by: Robin Murphy <robin.murphy@arm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
---
 drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c | 2 +-
 drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c       | 2 +-
 drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h       | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
index 548783f3f8e8..d03b2239baad 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
@@ -73,7 +73,7 @@ void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu)
 	if (__ratelimit(&rs)) {
 		dev_err(smmu->dev, "TLB sync timed out -- SMMU may be deadlocked\n");

-		cfg = qsmmu->cfg;
+		cfg = qsmmu->data->cfg;
 		if (!cfg)
 			return;

diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 6372f3e25c4b..d26f5aea248e 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -507,7 +507,7 @@ static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu,
 		return ERR_PTR(-ENOMEM);

 	qsmmu->smmu.impl = impl;
-	qsmmu->cfg = data->cfg;
+	qsmmu->data = data;

 	return &qsmmu->smmu;
 }
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
index 3c134d1a6277..b55cd3e3ae48 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
@@ -8,7 +8,7 @@

 struct qcom_smmu {
 	struct arm_smmu_device smmu;
-	const struct qcom_smmu_config *cfg;
+	const struct qcom_smmu_match_data *data;
 	bool bypass_quirk;
 	u8 bypass_cbndx;
 	u32 stall_enabled;
--
2.34.1

[PATCH v18 3/5] iommu/arm-smmu: add support for PRR bit setup

[Bibek Kumar Patro]

Add an adreno-smmu-priv interface for drm/msm to call
into arm-smmu-qcom and initiate the PRR bit setup or reset
sequence as per request.

This will be used by GPU to setup the PRR bit and related
configuration registers through adreno-smmu private
interface instead of directly poking the smmu hardware.

Suggested-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
---
 drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 52 ++++++++++++++++++++++
 drivers/iommu/arm/arm-smmu/arm-smmu.h      |  2 +
 include/linux/adreno-smmu-priv.h           | 14 ++++++
 3 files changed, 68 insertions(+)

diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index d26f5aea248e..818fdbd706da 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -16,6 +16,8 @@

 #define QCOM_DUMMY_VAL	-1

+#define GFX_ACTLR_PRR          (1 << 5)
+
 static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu)
 {
 	return container_of(smmu, struct qcom_smmu, smmu);
@@ -99,6 +101,47 @@ static void qcom_adreno_smmu_resume_translation(const void *cookie, bool termina
 	arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_RESUME, reg);
 }

+static void qcom_adreno_smmu_set_prr_bit(const void *cookie, bool set)
+{
+	struct arm_smmu_domain *smmu_domain = (void *)cookie;
+	struct arm_smmu_device *smmu = smmu_domain->smmu;
+	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
+	u32 reg = 0;
+	int ret;
+
+	ret = pm_runtime_resume_and_get(smmu->dev);
+	if (ret < 0) {
+		dev_err(smmu->dev, "failed to get runtime PM: %d\n", ret);
+		return;
+	}
+
+	reg =  arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_ACTLR);
+	reg &= ~GFX_ACTLR_PRR;
+	if (set)
+		reg |= FIELD_PREP(GFX_ACTLR_PRR, 1);
+	arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_ACTLR, reg);
+	pm_runtime_put_autosuspend(smmu->dev);
+}
+
+static void qcom_adreno_smmu_set_prr_addr(const void *cookie, phys_addr_t page_addr)
+{
+	struct arm_smmu_domain *smmu_domain = (void *)cookie;
+	struct arm_smmu_device *smmu = smmu_domain->smmu;
+	int ret;
+
+	ret = pm_runtime_resume_and_get(smmu->dev);
+	if (ret < 0) {
+		dev_err(smmu->dev, "failed to get runtime PM: %d\n", ret);
+		return;
+	}
+
+	writel_relaxed(lower_32_bits(page_addr),
+				smmu->base + ARM_SMMU_GFX_PRR_CFG_LADDR);
+	writel_relaxed(upper_32_bits(page_addr),
+				smmu->base + ARM_SMMU_GFX_PRR_CFG_UADDR);
+	pm_runtime_put_autosuspend(smmu->dev);
+}
+
 #define QCOM_ADRENO_SMMU_GPU_SID 0

 static bool qcom_adreno_smmu_is_gpu_device(struct device *dev)
@@ -210,6 +253,7 @@ static bool qcom_adreno_can_do_ttbr1(struct arm_smmu_device *smmu)
 static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
 		struct io_pgtable_cfg *pgtbl_cfg, struct device *dev)
 {
+	const struct device_node *np = smmu_domain->smmu->dev->of_node;
 	struct adreno_smmu_priv *priv;

 	smmu_domain->cfg.flush_walk_prefer_tlbiasid = true;
@@ -239,6 +283,14 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
 	priv->get_fault_info = qcom_adreno_smmu_get_fault_info;
 	priv->set_stall = qcom_adreno_smmu_set_stall;
 	priv->resume_translation = qcom_adreno_smmu_resume_translation;
+	priv->set_prr_bit = NULL;
+	priv->set_prr_addr = NULL;
+
+	if (of_device_is_compatible(np, "qcom,smmu-500") &&
+			of_device_is_compatible(np, "qcom,adreno-smmu")) {
+		priv->set_prr_bit = qcom_adreno_smmu_set_prr_bit;
+		priv->set_prr_addr = qcom_adreno_smmu_set_prr_addr;
+	}

 	return 0;
 }
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h
index e2aeb511ae90..2dbf3243b5ad 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu.h
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h
@@ -154,6 +154,8 @@ enum arm_smmu_cbar_type {
 #define ARM_SMMU_SCTLR_M		BIT(0)

 #define ARM_SMMU_CB_ACTLR		0x4
+#define ARM_SMMU_GFX_PRR_CFG_LADDR	0x6008
+#define ARM_SMMU_GFX_PRR_CFG_UADDR	0x600C

 #define ARM_SMMU_CB_RESUME		0x8
 #define ARM_SMMU_RESUME_TERMINATE	BIT(0)
diff --git a/include/linux/adreno-smmu-priv.h b/include/linux/adreno-smmu-priv.h
index c637e0997f6d..614665153b3e 100644
--- a/include/linux/adreno-smmu-priv.h
+++ b/include/linux/adreno-smmu-priv.h
@@ -50,6 +50,18 @@ struct adreno_smmu_fault_info {
  *                 the GPU driver must call resume_translation()
  * @resume_translation: Resume translation after a fault
  *
+ * *CAUTION* : PRR callbacks (set_prr_bit/set_prr_addr) are NULL terminated for
+ *             targets without PRR support. Exercise caution and verify target
+ *             capabilities before invoking these callbacks to prevent potential
+ *             runtime errors or unexpected behavior.
+ *
+ * @set_prr_bit:   Extendible interface to be used by GPU to modify the
+ *		   ACTLR register bits, currently used to configure
+ *		   Partially-Resident-Region (PRR) bit for feature's
+ *		   setup and reset sequence as requested.
+ * @set_prr_addr:  Configure the PRR_CFG_*ADDR register with the
+ *		   physical address of PRR page passed from
+ *		   GPU driver.
  *
  * The GPU driver (drm/msm) and adreno-smmu work together for controlling
  * the GPU's SMMU instance.  This is by necessity, as the GPU is directly
@@ -67,6 +79,8 @@ struct adreno_smmu_priv {
     void (*get_fault_info)(const void *cookie, struct adreno_smmu_fault_info *info);
     void (*set_stall)(const void *cookie, bool enabled);
     void (*resume_translation)(const void *cookie, bool terminate);
+    void (*set_prr_bit)(const void *cookie, bool set);
+    void (*set_prr_addr)(const void *cookie, phys_addr_t page_addr);
 };

 #endif /* __ADRENO_SMMU_PRIV_H */
--
2.34.1

[PATCH v18 4/5] iommu/arm-smmu: introduction of ACTLR for custom prefetcher settings

[Bibek Kumar Patro]

Currently in Qualcomm  SoCs the default prefetch is set to 1 which allows
the TLB to fetch just the next page table. MMU-500 features ACTLR
register which is implementation defined and is used for Qualcomm SoCs
to have a custom prefetch setting enabling TLB to prefetch the next set
of page tables accordingly allowing for faster translations.

ACTLR value is unique for each SMR (Stream matching register) and stored
in a pre-populated table. This value is set to the register during
context bank initialisation.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
---
 drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 33 ++++++++++++++++++++++
 drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h |  1 +
 2 files changed, 34 insertions(+)

diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 818fdbd706da..c6614be01d77 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -250,14 +250,37 @@ static bool qcom_adreno_can_do_ttbr1(struct arm_smmu_device *smmu)
 	return true;
 }

+static void qcom_smmu_set_actlr_dev(struct device *dev, struct arm_smmu_device *smmu, int cbndx,
+		const struct of_device_id *client_match)
+{
+	const struct of_device_id *match =
+			of_match_device(client_match, dev);
+
+	if (!match) {
+		dev_dbg(dev, "no ACTLR settings present\n");
+		return;
+	}
+
+	arm_smmu_cb_write(smmu, cbndx, ARM_SMMU_CB_ACTLR, (unsigned long)match->data);
+}
+
 static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
 		struct io_pgtable_cfg *pgtbl_cfg, struct device *dev)
 {
 	const struct device_node *np = smmu_domain->smmu->dev->of_node;
+	struct arm_smmu_device *smmu = smmu_domain->smmu;
+	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
+	const struct of_device_id *client_match;
+	int cbndx = smmu_domain->cfg.cbndx;
 	struct adreno_smmu_priv *priv;

 	smmu_domain->cfg.flush_walk_prefer_tlbiasid = true;

+	client_match = qsmmu->data->client_match;
+
+	if (client_match)
+		qcom_smmu_set_actlr_dev(dev, smmu, cbndx, client_match);
+
 	/* Only enable split pagetables for the GPU device (SID 0) */
 	if (!qcom_adreno_smmu_is_gpu_device(dev))
 		return 0;
@@ -321,8 +344,18 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
 static int qcom_smmu_init_context(struct arm_smmu_domain *smmu_domain,
 		struct io_pgtable_cfg *pgtbl_cfg, struct device *dev)
 {
+	struct arm_smmu_device *smmu = smmu_domain->smmu;
+	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
+	const struct of_device_id *client_match;
+	int cbndx = smmu_domain->cfg.cbndx;
+
 	smmu_domain->cfg.flush_walk_prefer_tlbiasid = true;

+	client_match = qsmmu->data->client_match;
+
+	if (client_match)
+		qcom_smmu_set_actlr_dev(dev, smmu, cbndx, client_match);
+
 	return 0;
 }

diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
index b55cd3e3ae48..8addd453f5f1 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
@@ -28,6 +28,7 @@ struct qcom_smmu_match_data {
 	const struct qcom_smmu_config *cfg;
 	const struct arm_smmu_impl *impl;
 	const struct arm_smmu_impl *adreno_impl;
+	const struct of_device_id * const client_match;
 };

 irqreturn_t qcom_smmu_context_fault(int irq, void *dev);
--
2.34.1

[PATCH v18 5/5] iommu/arm-smmu: add ACTLR data and support for qcom_smmu_500

[Bibek Kumar Patro]

Add ACTLR data table for qcom_smmu_500 including
corresponding data entry and set prefetch value by
way of a list of compatible strings.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
---
 drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 33 ++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index c6614be01d77..40f3a5a9f605 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -16,8 +16,40 @@

 #define QCOM_DUMMY_VAL	-1

+/*
+ * SMMU-500 TRM defines BIT(0) as CMTLB (Enable context caching in the
+ * macro TLB) and BIT(1) as CPRE (Enable context caching in the prefetch
+ * buffer). The remaining bits are implementation defined and vary across
+ * SoCs.
+ */
+
+#define CPRE			(1 << 1)
+#define CMTLB			(1 << 0)
+#define PREFETCH_SHIFT		8
+#define PREFETCH_DEFAULT	0
+#define PREFETCH_SHALLOW	(1 << PREFETCH_SHIFT)
+#define PREFETCH_MODERATE	(2 << PREFETCH_SHIFT)
+#define PREFETCH_DEEP		(3 << PREFETCH_SHIFT)
 #define GFX_ACTLR_PRR          (1 << 5)

+static const struct of_device_id qcom_smmu_actlr_client_of_match[] = {
+	{ .compatible = "qcom,adreno",
+			.data = (const void *) (PREFETCH_DEEP | CPRE | CMTLB) },
+	{ .compatible = "qcom,adreno-gmu",
+			.data = (const void *) (PREFETCH_DEEP | CPRE | CMTLB) },
+	{ .compatible = "qcom,adreno-smmu",
+			.data = (const void *) (PREFETCH_DEEP | CPRE | CMTLB) },
+	{ .compatible = "qcom,fastrpc",
+			.data = (const void *) (PREFETCH_DEEP | CPRE | CMTLB) },
+	{ .compatible = "qcom,sc7280-mdss",
+			.data = (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) },
+	{ .compatible = "qcom,sc7280-venus",
+			.data = (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) },
+	{ .compatible = "qcom,sm8550-mdss",
+			.data = (const void *) (PREFETCH_DEFAULT | CMTLB) },
+	{ }
+};
+
 static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu)
 {
 	return container_of(smmu, struct qcom_smmu, smmu);
@@ -635,6 +667,7 @@ static const struct qcom_smmu_match_data qcom_smmu_500_impl0_data = {
 	.impl = &qcom_smmu_500_impl,
 	.adreno_impl = &qcom_adreno_smmu_500_impl,
 	.cfg = &qcom_smmu_impl0_cfg,
+	.client_match = qcom_smmu_actlr_client_of_match,
 };

 /*
--
2.34.1

Re: [PATCH v18 0/5] iommu/arm-smmu: introduction of ACTLR implementation for Qualcomm SoCs

[Bibek Kumar Patro]

Hi,

Thought to follow up on this thread to highlight the latest version 
(v18) of this series, in case it was missed during the vacation period.

Thanks & regards,
Bibek

On 12/12/2024 8:43 PM, Bibek Kumar Patro wrote:
> This patch series consist of six parts and covers the following:
> 
> 1. Provide option to re-enable context caching to retain prefetcher
>     settings during reset and runtime suspend.
> 
> 2. Remove cfg inside qcom_smmu structure and replace it with single
>     pointer to qcom_smmu_match_data avoiding replication of multiple
>     members from same.
> 
> 3. Add support for ACTLR PRR bit setup via adreno-smmu-priv interface.
> 
> 4. Introduce intital set of driver changes to implement ACTLR register
>     for custom prefetcher settings in Qualcomm SoCs.
> 
> 5. Add ACTLR data and support for qcom_smmu_500.
> 
> Changes in v18 from v17_RESEND:
>   - 1/5 : No changes
>   - 2/5 : No changes - reviewed-by tags collected
>   - 3/5 : Addition of
>     pm_runtime_resume_and_get()/pm_runtime_put_autosuspend()
>     around register access of PRR related private interfaces
>     as discussed in v17_RESEND.
>   - 4/5, 5/5 : No changes - reviewed-by tags collected
>   Link to v17_RESEND:
>   https://lore.kernel.org/all/20241114160721.1527934-1-quic_bibekkum@quicinc.com/
> 
> Resend of v17:
>   Addition of minor fix of the build warning reported by kernel test robot [1] by powerpc_random config [2].
>   [1]:https://lore.kernel.org/all/202411140748.6mcFdJdO-lkp@intel.com/#t
>   [2]:https://download.01.org/0day-ci/archive/20241114/202411140748.6mcFdJdO-lkp@intel.com/config
> 
> Changes in v17 from v16:
>   Tags provided earlier not collected yet on patch 1/5, 3/5, 4/5, 5/5
>   due to the following revisions:
>   - 1/5 : Move the CPRE workaround out of qualcomm specific logic and gate with config
>           , update the silicon-errata.rst file
>   - 2/5 : No changes - reviewed-by tags collected
>   - 3/5 : Move the compatible check before assignment of callback as suggested.
>   - 4/5 : Add the actlr setting for *adreno variant* of MMU-500 as well.
>   - 5/5 : Due to changes in 1/5, minor refactoring had to be done before adding table.
>   Link to v16:
>   https://lore.kernel.org/all/20241008125410.3422512-1-quic_bibekkum@quicinc.com/
> 
> Changes in v16 from v15:
>   - Incorporate Dimitry's suggestion on patch 4/5 to use dev_dbg instead of dev_notice.
>   - Fix kernel test robot warning [1] coming for 32bit architecture configuration.
>   - Updatingthe tags
>   [1]: https://lore.kernel.org/all/202409230343.Q8KnYl2w-lkp@intel.com/
>   Link to v15:
>   https://lore.kernel.org/all/20240920155813.3434021-1-quic_bibekkum@quicinc.com/
> 
> Changes in v15 from v14:
>   - As discussed with Robin and Dmitry modify the actlr table and logic to use
>     compatible string instead of sid, mask for device matching which is
>     similar to qcom_smmu_client_of_match mechanism.
>   - Expand the comment in qcom_smmu500_reset to document reason why CPRE bit is re-enabled again
>     after arm_mmu500_reset resets the bit.
>   - Rearrange the series in order to keep prefetch setting patches in the end.
>   Link to v14:
>   https://lore.kernel.org/all/20240816174259.2056829-1-quic_bibekkum@quicinc.com/
> 
> Changes in v14 from v13:
>   Patch 6/6:
>   - As discussed incorprate changes to carry out PRR implementation only for
>     targets based on MMU-500 by using compat string based SMMU version detection.
>   - Split the set_actlr interface into two separate interface namely set_prr_bit
>     and set_prr_addr to set the prr enable bit and prr page address resepectively.
>   Patch 3/6:
>    - Fix a bug in gfx actlr_config which is uncovered while testing the gfx actlr setting in sc7280
>      during PRR experiment which prevented clients on certain sids of gfx smmmu to be skipped during
>      setting up of the ACTLR values : Fix involves swapping the arguments passed in smr_is_subset to make
>       device smr <from devicetree> a subset of actlr_config table entries < defined in the driver>.
>   Patch 4/6, 5/6:
>    - Sort the actlr table values in increasing order of the SIDs.
>   Link to v13:
>   https://lore.kernel.org/all/20240628140435.1652374-1-quic_bibekkum@quicinc.com/
> 
> Changes in v13 from v12:
>   - Fix the compilation issues reported by kernel test robot [1].
>   [1]: https://lore.kernel.org/all/202406281241.xEX0TWjt-lkp@intel.com/#t
>   Link to v12:
>   https://lore.kernel.org/all/20240626143020.3682243-1-quic_bibekkum@quicinc.com/
> 
> Changes in v12 from v11:
>   Changes to incorporate suggestion from Rob:
>   - Fix the set and reset logic for prr bit as pointed out in v11-6/6.
>   - Rename set_actlr_bit function name to set_prr.
>   - Add extension for PRR name as Partially-Resident-Region in comments
>     for set_prr function.
>   - Add few missing sids for sc7280 in patch-5/6.
>   Link to v11:
>   https://lore.kernel.org/all/20240605121713.3596499-1-quic_bibekkum@quicinc.com/
> 
> Changes in v11 from v10:
>   - Include a new patch 6/6 to add support for ACTLR PRR bit
>     through adreno-smmu-priv interface as suggested by Rob and Dmitry.
>   Link to v10:
>   https://lore.kernel.org/all/20240524131800.2288259-1-quic_bibekkum@quicinc.com/
> 
> Changes in v10 from v9:
>   - Added reviewed-by tags 1/5,2/5,3/5.
>   Changes incorporated:
>   - Remove redundant PRR bit setting from gfx actlr table(patch 4/5,5/5)
>     as this bit needs special handling in the gfx driver along with
>     the associated register settings.
>   Link to discussion on PRR bit:
>   https://lore.kernel.org/all/f2222714-1e00-424e-946d-c314d55541b8@quicinc.com/
>   Link to v9:
>   https://lore.kernel.org/all/20240123144543.9405-1-quic_bibekkum@quicinc.com/
> 
> Changes in v9 from v8:
>   Changes to incorporate suggestions from Konrad as follows:
>   - Re-wrap struct members of actlr_variant in patch 4/5,5/5
>     in a cleaner way.
>   - Move actlr_config members to the header.
>   Link to v8:
>   https://lore.kernel.org/all/20240116150411.23876-1-quic_bibekkum@quicinc.com/
> 
> Changes in v8 from v7:
>   - Added reviewed-by tags on patch 1/5, 2/5.
>   Changes to incorporate suggestions from Pavan and Konrad:
>   - Remove non necessary extra lines.
>   - Use num_smmu and num_actlrcfg to store the array size and use the
>     same to traverse the table and save on sentinel space along with
>     indentation levels.
>   - Refactor blocks containing qcom_smmu_set_actlr to remove block
>     repetition in patch 3/5.
>   - Change copyright year from 2023 to 2022-2023 in patch 3/5.
>   - Modify qcom_smmu_match_data.actlrvar and actlr_variant.actlrcfg to
>     const pointer to a const resource.
>   - use C99 designated initializers and put the address first.
>   Link to v7:
>   https://lore.kernel.org/all/20240109114220.30243-1-quic_bibekkum@quicinc.com/
> 
> Changes in v7 from v6:
>   Changes to incorporate suggestions from Dmitry as follows:
>   - Use io_start address instead of compatible string to identify the
>     correct instance by comparing with smmu start address and check for
>     which smmu the corresponding actlr table is to be picked.
> Link to v6:
> https://lore.kernel.org/all/20231220133808.5654-1-quic_bibekkum@quicinc.com/
> 
> Changes in v6 from v5:
>   - Remove extra Suggested-by tags.
>   - Add return check for arm_mmu500_reset in 1/5 as discussed.
> Link to v5:
> https://lore.kernel.org/all/20231219135947.1623-1-quic_bibekkum@quicinc.com/
> 
> Changes in v5 from v4:
>   New addition:
>   - Modify copyright year in arm-smmu-qcom.h to 2023 from 2022.
>   Changes to incorporate suggestions from Dmitry as follows:
>   - Modify the defines for prefetch in (foo << bar) format
>     as suggested.(FIELD_PREP could not be used in defines
>     is not inside any block/function)
>   Changes to incorporate suggestions from Konrad as follows:
>   - Shift context caching enablement patch as 1/5 instead of 5/5 to
>     be picked up as independent patch.
>   - Fix the codestyle to orient variables in reverse xmas tree format
>     for patch 1/5.
>   - Fix variable name in patch 1/5 as suggested.
>   Link to v4:
> https://lore.kernel.org/all/20231215101827.30549-1-quic_bibekkum@quicinc.com/
> 
> Changes in v4 from v3:
>   New addition:
>   - Remove actlrcfg_size and use NULL end element instead to traverse
>     the actlr table, as this would be a cleaner approach by removing
>     redundancy of actlrcfg_size.
>   - Renaming of actlr set function to arm_smmu_qcom based proprietary
>     convention.
>   - break from loop once sid is found and ACTLR value is initialized
>     in qcom_smmu_set_actlr.
>   - Modify the GFX prefetch value separating into 2 sensible defines.
>   - Modify comments for prefetch defines as per SMMU-500 TRM.
>   Changes to incorporate suggestions from Konrad as follows:
>   - Use Reverse-Christmas-tree sorting wherever applicable.
>   - Pass arguments directly to arm_smmu_set_actlr instead of creating
>     duplicate variables.
>   - Use array indexing instead of direct pointer addressed by new
>     addition of eliminating actlrcfg_size.
>   - Switch the HEX value's case from upper to lower case in SC7280
>     actlrcfg table.
>   Changes to incorporate suggestions from Dmitry as follows:
>   - Separate changes not related to ACTLR support to different commit
>     with patch 5/5.
>   - Using pointer to struct for arguments in smr_is_subset().
>   Changes to incorporate suggestions from Bjorn as follows:
>   - fix the commit message for patch 2/5 to properly document the
>     value space to avoid confusion.
>   Fixed build issues reported by kernel test robot [1] for
>   arm64-allyesconfig [2].
>   [1]: https://lore.kernel.org/all/202312011750.Pwca3TWE-lkp@intel.com/
>   [2]:
> https://download.01.org/0day-ci/archive/20231201/202312011750.Pwca3TWE-lkp@intel.com/config
>   Link to v3:
> https://lore.kernel.org/all/20231127145412.3981-1-quic_bibekkum@quicinc.com/
> 
> Changes in v3 from v2:
>   New addition:
>   - Include patch 3/4 for adding ACTLR support and data for SC7280.
>   - Add driver changes for actlr support in gpu smmu.
>   - Add target wise actlr data and implementation ops for gpu smmu.
>   Changes to incorporate suggestions from Robin as follows:
>   - Match the ACTLR values with individual corresponding SID instead
>     of assuming that any SMR will be programmed to match a superset of
>     the data.
>   - Instead of replicating each elements from qcom_smmu_match_data to
>     qcom_smmu structre during smmu device creation, replace the
>     replicated members with qcom_smmu_match_data structure inside
>     qcom_smmu structre and handle the dereference in places that
>     requires them.
>   Changes to incorporate suggestions from Dmitry and Konrad as follows:
>   - Maintain actlr table inside a single structure instead of
>     nested structure.
>   - Rename prefetch defines to more appropriately describe their
>     behavior.
>   - Remove SM8550 specific implementation ops and roll back to default
>     qcom_smmu_500_impl implementation ops.
>   - Add back the removed comments which are NAK.
>   - Fix commit description for patch 4/4.
>   Link to v2:
> https://lore.kernel.org/all/20231114135654.30475-1-quic_bibekkum@quicinc.com/
> 
> Changes in v2 from v1:
>   - Incorporated suggestions on v1 from Dmitry,Konrad,Pratyush.
>   - Added defines for ACTLR values.
>   - Linked sm8550 implementation structure to corresponding
>     compatible string.
>   - Repackaged actlr value set implementation to separate function.
>   - Fixed indentation errors.
>   - Link to v1:
> https://lore.kernel.org/all/20231103215124.1095-1-quic_bibekkum@quicinc.com/
> 
> Changes in v1 from RFC:
>   - Incorporated suggestion form Robin on RFC
>   - Moved the actlr data table into driver, instead of maintaining
>     it inside soc specific DT and piggybacking on exisiting iommus
>     property (iommu = <SID, MASK, ACTLR>) to set this value during
>     smmu probe.
>   - Link to RFC:
> https://lore.kernel.org/all/a01e7e60-6ead-4a9e-ba90-22a8a6bbd03f@quicinc.com/
> 
> Bibek Kumar Patro (5):
>    iommu/arm-smmu: re-enable context caching in smmu reset operation
>    iommu/arm-smmu: refactor qcom_smmu structure to include single pointer
>    iommu/arm-smmu: add support for PRR bit setup
>    iommu/arm-smmu: introduction of ACTLR for custom prefetcher settings
>    iommu/arm-smmu: add ACTLR data and support for qcom_smmu_500
> 
>   Documentation/arch/arm64/silicon-errata.rst   |   3 +-
>   drivers/iommu/Kconfig                         |  12 ++
>   drivers/iommu/arm/arm-smmu/arm-smmu-impl.c    |   5 +-
>   .../iommu/arm/arm-smmu/arm-smmu-qcom-debug.c  |   2 +-
>   drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c    | 120 +++++++++++++++++-
>   drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h    |   3 +-
>   drivers/iommu/arm/arm-smmu/arm-smmu.h         |   2 +
>   include/linux/adreno-smmu-priv.h              |  14 ++
>   8 files changed, 155 insertions(+), 6 deletions(-)
> 
> --
> 2.34.1
> 

Re: [PATCH v18 0/5] iommu/arm-smmu: introduction of ACTLR implementation for Qualcomm SoCs

[Will Deacon]

(please don't top-post...)

On Mon, Dec 30, 2024 at 06:45:29PM +0530, Bibek Kumar Patro wrote:
> On 12/12/2024 8:43 PM, Bibek Kumar Patro wrote:
> > This patch series consist of six parts and covers the following:
> > 
> > 1. Provide option to re-enable context caching to retain prefetcher
> >     settings during reset and runtime suspend.
> > 
> > 2. Remove cfg inside qcom_smmu structure and replace it with single
> >     pointer to qcom_smmu_match_data avoiding replication of multiple
> >     members from same.
> > 
> > 3. Add support for ACTLR PRR bit setup via adreno-smmu-priv interface.
> > 
> > 4. Introduce intital set of driver changes to implement ACTLR register
> >     for custom prefetcher settings in Qualcomm SoCs.
> > 
> > 5. Add ACTLR data and support for qcom_smmu_500.
> > 
> > Changes in v18 from v17_RESEND:
> >   - 1/5 : No changes
> >   - 2/5 : No changes - reviewed-by tags collected
> >   - 3/5 : Addition of
> >     pm_runtime_resume_and_get()/pm_runtime_put_autosuspend()
> >     around register access of PRR related private interfaces
> >     as discussed in v17_RESEND.
> >   - 4/5, 5/5 : No changes - reviewed-by tags collected
> >   Link to v17_RESEND:
> >   https://lore.kernel.org/all/20241114160721.1527934-1-quic_bibekkum@quicinc.com/
>
> Thought to follow up on this thread to highlight the latest version (v18) of
> this series, in case it was missed during the vacation period.


I'm waiting for Rob (Clark) to ack the last patch, as he had comments on
the previous version.

Will

Re: [PATCH v18 0/5] iommu/arm-smmu: introduction of ACTLR implementation for Qualcomm SoCs

[Rob Clark]

On Fri, Jan 3, 2025 at 7:37 AM Will Deacon <will@kernel.org> wrote:
>
> (please don't top-post...)
>
> On Mon, Dec 30, 2024 at 06:45:29PM +0530, Bibek Kumar Patro wrote:
> > On 12/12/2024 8:43 PM, Bibek Kumar Patro wrote:
> > > This patch series consist of six parts and covers the following:
> > >
> > > 1. Provide option to re-enable context caching to retain prefetcher
> > >     settings during reset and runtime suspend.
> > >
> > > 2. Remove cfg inside qcom_smmu structure and replace it with single
> > >     pointer to qcom_smmu_match_data avoiding replication of multiple
> > >     members from same.
> > >
> > > 3. Add support for ACTLR PRR bit setup via adreno-smmu-priv interface.
> > >
> > > 4. Introduce intital set of driver changes to implement ACTLR register
> > >     for custom prefetcher settings in Qualcomm SoCs.
> > >
> > > 5. Add ACTLR data and support for qcom_smmu_500.
> > >
> > > Changes in v18 from v17_RESEND:
> > >   - 1/5 : No changes
> > >   - 2/5 : No changes - reviewed-by tags collected
> > >   - 3/5 : Addition of
> > >     pm_runtime_resume_and_get()/pm_runtime_put_autosuspend()
> > >     around register access of PRR related private interfaces
> > >     as discussed in v17_RESEND.
> > >   - 4/5, 5/5 : No changes - reviewed-by tags collected
> > >   Link to v17_RESEND:
> > >   https://lore.kernel.org/all/20241114160721.1527934-1-quic_bibekkum@quicinc.com/
> >
> > Thought to follow up on this thread to highlight the latest version (v18) of
> > this series, in case it was missed during the vacation period.
>
>
> I'm waiting for Rob (Clark) to ack the last patch, as he had comments on
> the previous version.

You mean 3/5?  The latest (v18) lgtm, a-b

Re: [PATCH v18 0/5] iommu/arm-smmu: introduction of ACTLR implementation for Qualcomm SoCs

[Will Deacon]

On Fri, Jan 03, 2025 at 10:16:43AM -0800, Rob Clark wrote:
> On Fri, Jan 3, 2025 at 7:37 AM Will Deacon <will@kernel.org> wrote:
> >
> > (please don't top-post...)
> >
> > On Mon, Dec 30, 2024 at 06:45:29PM +0530, Bibek Kumar Patro wrote:
> > > On 12/12/2024 8:43 PM, Bibek Kumar Patro wrote:
> > > > This patch series consist of six parts and covers the following:
> > > >
> > > > 1. Provide option to re-enable context caching to retain prefetcher
> > > >     settings during reset and runtime suspend.
> > > >
> > > > 2. Remove cfg inside qcom_smmu structure and replace it with single
> > > >     pointer to qcom_smmu_match_data avoiding replication of multiple
> > > >     members from same.
> > > >
> > > > 3. Add support for ACTLR PRR bit setup via adreno-smmu-priv interface.
> > > >
> > > > 4. Introduce intital set of driver changes to implement ACTLR register
> > > >     for custom prefetcher settings in Qualcomm SoCs.
> > > >
> > > > 5. Add ACTLR data and support for qcom_smmu_500.
> > > >
> > > > Changes in v18 from v17_RESEND:
> > > >   - 1/5 : No changes
> > > >   - 2/5 : No changes - reviewed-by tags collected
> > > >   - 3/5 : Addition of
> > > >     pm_runtime_resume_and_get()/pm_runtime_put_autosuspend()
> > > >     around register access of PRR related private interfaces
> > > >     as discussed in v17_RESEND.
> > > >   - 4/5, 5/5 : No changes - reviewed-by tags collected
> > > >   Link to v17_RESEND:
> > > >   https://lore.kernel.org/all/20241114160721.1527934-1-quic_bibekkum@quicinc.com/
> > >
> > > Thought to follow up on this thread to highlight the latest version (v18) of
> > > this series, in case it was missed during the vacation period.
> >
> >
> > I'm waiting for Rob (Clark) to ack the last patch, as he had comments on
> > the previous version.
> 
> You mean 3/5?  The latest (v18) lgtm, a-b

Sorry, yes, I meant 3/5. Thanks for having a look!

Will

Re: [PATCH v18 0/5] iommu/arm-smmu: introduction of ACTLR implementation for Qualcomm SoCs

[Will Deacon]

On Thu, 12 Dec 2024 20:43:57 +0530, Bibek Kumar Patro wrote:
> This patch series consist of six parts and covers the following:
> 
> 1. Provide option to re-enable context caching to retain prefetcher
>    settings during reset and runtime suspend.
> 
> 2. Remove cfg inside qcom_smmu structure and replace it with single
>    pointer to qcom_smmu_match_data avoiding replication of multiple
>    members from same.
> 
> [...]

Applied to iommu (arm/smmu/updates), thanks!

[1/5] iommu/arm-smmu: Re-enable context caching in smmu reset operation
      https://git.kernel.org/iommu/c/ef4144b1b47d
[2/5] iommu/arm-smmu: Refactor qcom_smmu structure to include single pointer
      https://git.kernel.org/iommu/c/445d7a8ed90e
[3/5] iommu/arm-smmu: Add support for PRR bit setup
      https://git.kernel.org/iommu/c/7f2ef1bfc758
[4/5] iommu/arm-smmu: Introduce ACTLR custom prefetcher settings
      https://git.kernel.org/iommu/c/9fe18d825a58
[5/5] iommu/arm-smmu: Add ACTLR data and support for qcom_smmu_500
      https://git.kernel.org/iommu/c/3e35c3e725de

Cheers,
-- 
Will

https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev

Re: [PATCH v18 0/5] iommu/arm-smmu: introduction of ACTLR implementation for Qualcomm SoCs

[Will Deacon]

On Tue, Jan 07, 2025 at 04:42:39PM +0000, Will Deacon wrote:
> On Thu, 12 Dec 2024 20:43:57 +0530, Bibek Kumar Patro wrote:
> > This patch series consist of six parts and covers the following:
> > 
> > 1. Provide option to re-enable context caching to retain prefetcher
> >    settings during reset and runtime suspend.
> > 
> > 2. Remove cfg inside qcom_smmu structure and replace it with single
> >    pointer to qcom_smmu_match_data avoiding replication of multiple
> >    members from same.
> > 
> > [...]
> 
> Applied to iommu (arm/smmu/updates), thanks!
> 
> [1/5] iommu/arm-smmu: Re-enable context caching in smmu reset operation
>       https://git.kernel.org/iommu/c/ef4144b1b47d
> [2/5] iommu/arm-smmu: Refactor qcom_smmu structure to include single pointer
>       https://git.kernel.org/iommu/c/445d7a8ed90e
> [3/5] iommu/arm-smmu: Add support for PRR bit setup
>       https://git.kernel.org/iommu/c/7f2ef1bfc758
> [4/5] iommu/arm-smmu: Introduce ACTLR custom prefetcher settings
>       https://git.kernel.org/iommu/c/9fe18d825a58
> [5/5] iommu/arm-smmu: Add ACTLR data and support for qcom_smmu_500
>       https://git.kernel.org/iommu/c/3e35c3e725de

Hrm. I'm not seeing any user of the new ->set_prr*_() functions in
linux-next yet. Is there something under review, or should I revert this
for now?

Will

Re: [PATCH v18 0/5] iommu/arm-smmu: introduction of ACTLR implementation for Qualcomm SoCs

[Rob Clark]

On Tue, Mar 11, 2025 at 10:55 AM Will Deacon <will@kernel.org> wrote:
>
> On Tue, Jan 07, 2025 at 04:42:39PM +0000, Will Deacon wrote:
> > On Thu, 12 Dec 2024 20:43:57 +0530, Bibek Kumar Patro wrote:
> > > This patch series consist of six parts and covers the following:
> > >
> > > 1. Provide option to re-enable context caching to retain prefetcher
> > >    settings during reset and runtime suspend.
> > >
> > > 2. Remove cfg inside qcom_smmu structure and replace it with single
> > >    pointer to qcom_smmu_match_data avoiding replication of multiple
> > >    members from same.
> > >
> > > [...]
> >
> > Applied to iommu (arm/smmu/updates), thanks!
> >
> > [1/5] iommu/arm-smmu: Re-enable context caching in smmu reset operation
> >       https://git.kernel.org/iommu/c/ef4144b1b47d
> > [2/5] iommu/arm-smmu: Refactor qcom_smmu structure to include single pointer
> >       https://git.kernel.org/iommu/c/445d7a8ed90e
> > [3/5] iommu/arm-smmu: Add support for PRR bit setup
> >       https://git.kernel.org/iommu/c/7f2ef1bfc758
> > [4/5] iommu/arm-smmu: Introduce ACTLR custom prefetcher settings
> >       https://git.kernel.org/iommu/c/9fe18d825a58
> > [5/5] iommu/arm-smmu: Add ACTLR data and support for qcom_smmu_500
> >       https://git.kernel.org/iommu/c/3e35c3e725de
>
> Hrm. I'm not seeing any user of the new ->set_prr*_() functions in
> linux-next yet. Is there something under review, or should I revert this
> for now?

It is WIP, part of a larger patchset adding sparse binding support in
drm/msm.  Please do not revert.

BR,
-R

Re: [PATCH v18 0/5] iommu/arm-smmu: introduction of ACTLR implementation for Qualcomm SoCs

[Will Deacon]

On Tue, Mar 11, 2025 at 01:03:29PM -0700, Rob Clark wrote:
> On Tue, Mar 11, 2025 at 10:55 AM Will Deacon <will@kernel.org> wrote:
> >
> > On Tue, Jan 07, 2025 at 04:42:39PM +0000, Will Deacon wrote:
> > > On Thu, 12 Dec 2024 20:43:57 +0530, Bibek Kumar Patro wrote:
> > > > This patch series consist of six parts and covers the following:
> > > >
> > > > 1. Provide option to re-enable context caching to retain prefetcher
> > > >    settings during reset and runtime suspend.
> > > >
> > > > 2. Remove cfg inside qcom_smmu structure and replace it with single
> > > >    pointer to qcom_smmu_match_data avoiding replication of multiple
> > > >    members from same.
> > > >
> > > > [...]
> > >
> > > Applied to iommu (arm/smmu/updates), thanks!
> > >
> > > [1/5] iommu/arm-smmu: Re-enable context caching in smmu reset operation
> > >       https://git.kernel.org/iommu/c/ef4144b1b47d
> > > [2/5] iommu/arm-smmu: Refactor qcom_smmu structure to include single pointer
> > >       https://git.kernel.org/iommu/c/445d7a8ed90e
> > > [3/5] iommu/arm-smmu: Add support for PRR bit setup
> > >       https://git.kernel.org/iommu/c/7f2ef1bfc758
> > > [4/5] iommu/arm-smmu: Introduce ACTLR custom prefetcher settings
> > >       https://git.kernel.org/iommu/c/9fe18d825a58
> > > [5/5] iommu/arm-smmu: Add ACTLR data and support for qcom_smmu_500
> > >       https://git.kernel.org/iommu/c/3e35c3e725de
> >
> > Hrm. I'm not seeing any user of the new ->set_prr*_() functions in
> > linux-next yet. Is there something under review, or should I revert this
> > for now?
> 
> It is WIP, part of a larger patchset adding sparse binding support in
> drm/msm.  Please do not revert.

Sure, if it's actively being worked on then I'll leave the hooks in
place.

Do you have a link to the patchset so that I can follow along, please?

Will

Re: [PATCH v18 0/5] iommu/arm-smmu: introduction of ACTLR implementation for Qualcomm SoCs

[Rob Clark]

On Wed, Mar 12, 2025 at 6:08 AM Will Deacon <will@kernel.org> wrote:
>
> On Tue, Mar 11, 2025 at 01:03:29PM -0700, Rob Clark wrote:
> > On Tue, Mar 11, 2025 at 10:55 AM Will Deacon <will@kernel.org> wrote:
> > >
> > > On Tue, Jan 07, 2025 at 04:42:39PM +0000, Will Deacon wrote:
> > > > On Thu, 12 Dec 2024 20:43:57 +0530, Bibek Kumar Patro wrote:
> > > > > This patch series consist of six parts and covers the following:
> > > > >
> > > > > 1. Provide option to re-enable context caching to retain prefetcher
> > > > >    settings during reset and runtime suspend.
> > > > >
> > > > > 2. Remove cfg inside qcom_smmu structure and replace it with single
> > > > >    pointer to qcom_smmu_match_data avoiding replication of multiple
> > > > >    members from same.
> > > > >
> > > > > [...]
> > > >
> > > > Applied to iommu (arm/smmu/updates), thanks!
> > > >
> > > > [1/5] iommu/arm-smmu: Re-enable context caching in smmu reset operation
> > > >       https://git.kernel.org/iommu/c/ef4144b1b47d
> > > > [2/5] iommu/arm-smmu: Refactor qcom_smmu structure to include single pointer
> > > >       https://git.kernel.org/iommu/c/445d7a8ed90e
> > > > [3/5] iommu/arm-smmu: Add support for PRR bit setup
> > > >       https://git.kernel.org/iommu/c/7f2ef1bfc758
> > > > [4/5] iommu/arm-smmu: Introduce ACTLR custom prefetcher settings
> > > >       https://git.kernel.org/iommu/c/9fe18d825a58
> > > > [5/5] iommu/arm-smmu: Add ACTLR data and support for qcom_smmu_500
> > > >       https://git.kernel.org/iommu/c/3e35c3e725de
> > >
> > > Hrm. I'm not seeing any user of the new ->set_prr*_() functions in
> > > linux-next yet. Is there something under review, or should I revert this
> > > for now?
> >
> > It is WIP, part of a larger patchset adding sparse binding support in
> > drm/msm.  Please do not revert.
>
> Sure, if it's actively being worked on then I'll leave the hooks in
> place.
>
> Do you have a link to the patchset so that I can follow along, please?
>
> Will

https://patchwork.freedesktop.org/series/142263/

I'm currently working on resolving the shrinker hack, which is the
remaining TODO.  So I'll hopefully be able to drop the RFC tag and
post a new version in a couple of weeks.

BR,
-R

Re: [PATCH v18 0/5] iommu/arm-smmu: introduction of ACTLR implementation for Qualcomm SoCs

[Enric Balletbo i Serra]

On Thu, Dec 12, 2024 at 4:14 PM Bibek Kumar Patro
<quic_bibekkum@quicinc.com> wrote:
>
> This patch series consist of six parts and covers the following:
>
> 1. Provide option to re-enable context caching to retain prefetcher
>    settings during reset and runtime suspend.
>
> 2. Remove cfg inside qcom_smmu structure and replace it with single
>    pointer to qcom_smmu_match_data avoiding replication of multiple
>    members from same.
>
> 3. Add support for ACTLR PRR bit setup via adreno-smmu-priv interface.
>
> 4. Introduce intital set of driver changes to implement ACTLR register
>    for custom prefetcher settings in Qualcomm SoCs.
>
> 5. Add ACTLR data and support for qcom_smmu_500.
>
> Changes in v18 from v17_RESEND:
>  - 1/5 : No changes
>  - 2/5 : No changes - reviewed-by tags collected
>  - 3/5 : Addition of
>    pm_runtime_resume_and_get()/pm_runtime_put_autosuspend()
>    around register access of PRR related private interfaces
>    as discussed in v17_RESEND.
>  - 4/5, 5/5 : No changes - reviewed-by tags collected
>  Link to v17_RESEND:
>  https://lore.kernel.org/all/20241114160721.1527934-1-quic_bibekkum@quicinc.com/
>
> Resend of v17:
>  Addition of minor fix of the build warning reported by kernel test robot [1] by powerpc_random config [2].
>  [1]:https://lore.kernel.org/all/202411140748.6mcFdJdO-lkp@intel.com/#t
>  [2]:https://download.01.org/0day-ci/archive/20241114/202411140748.6mcFdJdO-lkp@intel.com/config
>
> Changes in v17 from v16:
>  Tags provided earlier not collected yet on patch 1/5, 3/5, 4/5, 5/5
>  due to the following revisions:
>  - 1/5 : Move the CPRE workaround out of qualcomm specific logic and gate with config
>          , update the silicon-errata.rst file
>  - 2/5 : No changes - reviewed-by tags collected
>  - 3/5 : Move the compatible check before assignment of callback as suggested.
>  - 4/5 : Add the actlr setting for *adreno variant* of MMU-500 as well.
>  - 5/5 : Due to changes in 1/5, minor refactoring had to be done before adding table.
>  Link to v16:
>  https://lore.kernel.org/all/20241008125410.3422512-1-quic_bibekkum@quicinc.com/
>
> Changes in v16 from v15:
>  - Incorporate Dimitry's suggestion on patch 4/5 to use dev_dbg instead of dev_notice.
>  - Fix kernel test robot warning [1] coming for 32bit architecture configuration.
>  - Updatingthe tags
>  [1]: https://lore.kernel.org/all/202409230343.Q8KnYl2w-lkp@intel.com/
>  Link to v15:
>  https://lore.kernel.org/all/20240920155813.3434021-1-quic_bibekkum@quicinc.com/
>
> Changes in v15 from v14:
>  - As discussed with Robin and Dmitry modify the actlr table and logic to use
>    compatible string instead of sid, mask for device matching which is
>    similar to qcom_smmu_client_of_match mechanism.
>  - Expand the comment in qcom_smmu500_reset to document reason why CPRE bit is re-enabled again
>    after arm_mmu500_reset resets the bit.
>  - Rearrange the series in order to keep prefetch setting patches in the end.
>  Link to v14:
>  https://lore.kernel.org/all/20240816174259.2056829-1-quic_bibekkum@quicinc.com/
>

Hi all,

I've been looking at the evolution of the Qualcomm SMMU driver
(arm-smmu-qcom.c) and had a question about the design change for
configuring the SMMU_CB_ACTLR register.

It appears there are two different approaches:

1. The "SID" Approach (Older): In some versions, a driver would use a
large, platform-specific struct (e.g., sa8775p_apps_actlr_cfg) that
maps individual Stream IDs (SIDs) to specific ACTLR values. This
allowed for very granular, per-SID tuning. For example, a device with
10 SIDs could have a specific setting for just one (0x2141), while the
others used a default.

2. The "Compatible String" Approach (Newer/Upstream): The current
upstream driver appears to use a client_match array (an of_device_id
list) in qcom_smmu_init_context. This maps a device's compatible
string to a single ACTLR value, which is then written to the device's
assigned Context Bank.

I want to make sure I understand the implications of this new, simpler
approach, as it seems to introduce a trade-off where granularity is
lost:

Multiple SIDs, One Device: A single device that uses many SIDs in the
device tree (e.g., the video codec, which might list 0x2141, 0x25C1,
0x2161, etc.) will now have one ACTLR setting applied to the Context
Bank that serves all of those SIDs, even if the old SID-based list
only specified a setting for one of them.

Am I correct in this analysis? I'm assuming this was an intentional
design choice to simplify the driver, based on the assumption that all
SIDs for a single device (and all devices with the same compatible)
can share the same ACTLR tuning.

I'm working on porting settings for an sa8775p board and just want to
ensure I'm migrating the logic correctly to this new client_match
method.

Thanks for any clarification you can provide.

Best regards,

   Enric


> Changes in v14 from v13:
>  Patch 6/6:
>  - As discussed incorprate changes to carry out PRR implementation only for
>    targets based on MMU-500 by using compat string based SMMU version detection.
>  - Split the set_actlr interface into two separate interface namely set_prr_bit
>    and set_prr_addr to set the prr enable bit and prr page address resepectively.
>  Patch 3/6:
>   - Fix a bug in gfx actlr_config which is uncovered while testing the gfx actlr setting in sc7280
>     during PRR experiment which prevented clients on certain sids of gfx smmmu to be skipped during
>     setting up of the ACTLR values : Fix involves swapping the arguments passed in smr_is_subset to make
>      device smr <from devicetree> a subset of actlr_config table entries < defined in the driver>.
>  Patch 4/6, 5/6:
>   - Sort the actlr table values in increasing order of the SIDs.
>  Link to v13:
>  https://lore.kernel.org/all/20240628140435.1652374-1-quic_bibekkum@quicinc.com/
>
> Changes in v13 from v12:
>  - Fix the compilation issues reported by kernel test robot [1].
>  [1]: https://lore.kernel.org/all/202406281241.xEX0TWjt-lkp@intel.com/#t
>  Link to v12:
>  https://lore.kernel.org/all/20240626143020.3682243-1-quic_bibekkum@quicinc.com/
>
> Changes in v12 from v11:
>  Changes to incorporate suggestion from Rob:
>  - Fix the set and reset logic for prr bit as pointed out in v11-6/6.
>  - Rename set_actlr_bit function name to set_prr.
>  - Add extension for PRR name as Partially-Resident-Region in comments
>    for set_prr function.
>  - Add few missing sids for sc7280 in patch-5/6.
>  Link to v11:
>  https://lore.kernel.org/all/20240605121713.3596499-1-quic_bibekkum@quicinc.com/
>
> Changes in v11 from v10:
>  - Include a new patch 6/6 to add support for ACTLR PRR bit
>    through adreno-smmu-priv interface as suggested by Rob and Dmitry.
>  Link to v10:
>  https://lore.kernel.org/all/20240524131800.2288259-1-quic_bibekkum@quicinc.com/
>
> Changes in v10 from v9:
>  - Added reviewed-by tags 1/5,2/5,3/5.
>  Changes incorporated:
>  - Remove redundant PRR bit setting from gfx actlr table(patch 4/5,5/5)
>    as this bit needs special handling in the gfx driver along with
>    the associated register settings.
>  Link to discussion on PRR bit:
>  https://lore.kernel.org/all/f2222714-1e00-424e-946d-c314d55541b8@quicinc.com/
>  Link to v9:
>  https://lore.kernel.org/all/20240123144543.9405-1-quic_bibekkum@quicinc.com/
>
> Changes in v9 from v8:
>  Changes to incorporate suggestions from Konrad as follows:
>  - Re-wrap struct members of actlr_variant in patch 4/5,5/5
>    in a cleaner way.
>  - Move actlr_config members to the header.
>  Link to v8:
>  https://lore.kernel.org/all/20240116150411.23876-1-quic_bibekkum@quicinc.com/
>
> Changes in v8 from v7:
>  - Added reviewed-by tags on patch 1/5, 2/5.
>  Changes to incorporate suggestions from Pavan and Konrad:
>  - Remove non necessary extra lines.
>  - Use num_smmu and num_actlrcfg to store the array size and use the
>    same to traverse the table and save on sentinel space along with
>    indentation levels.
>  - Refactor blocks containing qcom_smmu_set_actlr to remove block
>    repetition in patch 3/5.
>  - Change copyright year from 2023 to 2022-2023 in patch 3/5.
>  - Modify qcom_smmu_match_data.actlrvar and actlr_variant.actlrcfg to
>    const pointer to a const resource.
>  - use C99 designated initializers and put the address first.
>  Link to v7:
>  https://lore.kernel.org/all/20240109114220.30243-1-quic_bibekkum@quicinc.com/
>
> Changes in v7 from v6:
>  Changes to incorporate suggestions from Dmitry as follows:
>  - Use io_start address instead of compatible string to identify the
>    correct instance by comparing with smmu start address and check for
>    which smmu the corresponding actlr table is to be picked.
> Link to v6:
> https://lore.kernel.org/all/20231220133808.5654-1-quic_bibekkum@quicinc.com/
>
> Changes in v6 from v5:
>  - Remove extra Suggested-by tags.
>  - Add return check for arm_mmu500_reset in 1/5 as discussed.
> Link to v5:
> https://lore.kernel.org/all/20231219135947.1623-1-quic_bibekkum@quicinc.com/
>
> Changes in v5 from v4:
>  New addition:
>  - Modify copyright year in arm-smmu-qcom.h to 2023 from 2022.
>  Changes to incorporate suggestions from Dmitry as follows:
>  - Modify the defines for prefetch in (foo << bar) format
>    as suggested.(FIELD_PREP could not be used in defines
>    is not inside any block/function)
>  Changes to incorporate suggestions from Konrad as follows:
>  - Shift context caching enablement patch as 1/5 instead of 5/5 to
>    be picked up as independent patch.
>  - Fix the codestyle to orient variables in reverse xmas tree format
>    for patch 1/5.
>  - Fix variable name in patch 1/5 as suggested.
>  Link to v4:
> https://lore.kernel.org/all/20231215101827.30549-1-quic_bibekkum@quicinc.com/
>
> Changes in v4 from v3:
>  New addition:
>  - Remove actlrcfg_size and use NULL end element instead to traverse
>    the actlr table, as this would be a cleaner approach by removing
>    redundancy of actlrcfg_size.
>  - Renaming of actlr set function to arm_smmu_qcom based proprietary
>    convention.
>  - break from loop once sid is found and ACTLR value is initialized
>    in qcom_smmu_set_actlr.
>  - Modify the GFX prefetch value separating into 2 sensible defines.
>  - Modify comments for prefetch defines as per SMMU-500 TRM.
>  Changes to incorporate suggestions from Konrad as follows:
>  - Use Reverse-Christmas-tree sorting wherever applicable.
>  - Pass arguments directly to arm_smmu_set_actlr instead of creating
>    duplicate variables.
>  - Use array indexing instead of direct pointer addressed by new
>    addition of eliminating actlrcfg_size.
>  - Switch the HEX value's case from upper to lower case in SC7280
>    actlrcfg table.
>  Changes to incorporate suggestions from Dmitry as follows:
>  - Separate changes not related to ACTLR support to different commit
>    with patch 5/5.
>  - Using pointer to struct for arguments in smr_is_subset().
>  Changes to incorporate suggestions from Bjorn as follows:
>  - fix the commit message for patch 2/5 to properly document the
>    value space to avoid confusion.
>  Fixed build issues reported by kernel test robot [1] for
>  arm64-allyesconfig [2].
>  [1]: https://lore.kernel.org/all/202312011750.Pwca3TWE-lkp@intel.com/
>  [2]:
> https://download.01.org/0day-ci/archive/20231201/202312011750.Pwca3TWE-lkp@intel.com/config
>  Link to v3:
> https://lore.kernel.org/all/20231127145412.3981-1-quic_bibekkum@quicinc.com/
>
> Changes in v3 from v2:
>  New addition:
>  - Include patch 3/4 for adding ACTLR support and data for SC7280.
>  - Add driver changes for actlr support in gpu smmu.
>  - Add target wise actlr data and implementation ops for gpu smmu.
>  Changes to incorporate suggestions from Robin as follows:
>  - Match the ACTLR values with individual corresponding SID instead
>    of assuming that any SMR will be programmed to match a superset of
>    the data.
>  - Instead of replicating each elements from qcom_smmu_match_data to
>    qcom_smmu structre during smmu device creation, replace the
>    replicated members with qcom_smmu_match_data structure inside
>    qcom_smmu structre and handle the dereference in places that
>    requires them.
>  Changes to incorporate suggestions from Dmitry and Konrad as follows:
>  - Maintain actlr table inside a single structure instead of
>    nested structure.
>  - Rename prefetch defines to more appropriately describe their
>    behavior.
>  - Remove SM8550 specific implementation ops and roll back to default
>    qcom_smmu_500_impl implementation ops.
>  - Add back the removed comments which are NAK.
>  - Fix commit description for patch 4/4.
>  Link to v2:
> https://lore.kernel.org/all/20231114135654.30475-1-quic_bibekkum@quicinc.com/
>
> Changes in v2 from v1:
>  - Incorporated suggestions on v1 from Dmitry,Konrad,Pratyush.
>  - Added defines for ACTLR values.
>  - Linked sm8550 implementation structure to corresponding
>    compatible string.
>  - Repackaged actlr value set implementation to separate function.
>  - Fixed indentation errors.
>  - Link to v1:
> https://lore.kernel.org/all/20231103215124.1095-1-quic_bibekkum@quicinc.com/
>
> Changes in v1 from RFC:
>  - Incorporated suggestion form Robin on RFC
>  - Moved the actlr data table into driver, instead of maintaining
>    it inside soc specific DT and piggybacking on exisiting iommus
>    property (iommu = <SID, MASK, ACTLR>) to set this value during
>    smmu probe.
>  - Link to RFC:
> https://lore.kernel.org/all/a01e7e60-6ead-4a9e-ba90-22a8a6bbd03f@quicinc.com/
>
> Bibek Kumar Patro (5):
>   iommu/arm-smmu: re-enable context caching in smmu reset operation
>   iommu/arm-smmu: refactor qcom_smmu structure to include single pointer
>   iommu/arm-smmu: add support for PRR bit setup
>   iommu/arm-smmu: introduction of ACTLR for custom prefetcher settings
>   iommu/arm-smmu: add ACTLR data and support for qcom_smmu_500
>
>  Documentation/arch/arm64/silicon-errata.rst   |   3 +-
>  drivers/iommu/Kconfig                         |  12 ++
>  drivers/iommu/arm/arm-smmu/arm-smmu-impl.c    |   5 +-
>  .../iommu/arm/arm-smmu/arm-smmu-qcom-debug.c  |   2 +-
>  drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c    | 120 +++++++++++++++++-
>  drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h    |   3 +-
>  drivers/iommu/arm/arm-smmu/arm-smmu.h         |   2 +
>  include/linux/adreno-smmu-priv.h              |  14 ++
>  8 files changed, 155 insertions(+), 6 deletions(-)
>
> --
> 2.34.1
>
>

Re: [PATCH v18 0/5] iommu/arm-smmu: introduction of ACTLR implementation for Qualcomm SoCs

[Bibek Kumar Patro]

On 11/7/2025 2:58 PM, Enric Balletbo i Serra wrote:
> On Thu, Dec 12, 2024 at 4:14 PM Bibek Kumar Patro
> <quic_bibekkum@quicinc.com> wrote:
>>
>> This patch series consist of six parts and covers the following:
>>
>> 1. Provide option to re-enable context caching to retain prefetcher
>>     settings during reset and runtime suspend.
>>
>> 2. Remove cfg inside qcom_smmu structure and replace it with single
>>     pointer to qcom_smmu_match_data avoiding replication of multiple
>>     members from same.
>>
>> 3. Add support for ACTLR PRR bit setup via adreno-smmu-priv interface.
>>
>> 4. Introduce intital set of driver changes to implement ACTLR register
>>     for custom prefetcher settings in Qualcomm SoCs.
>>
>> 5. Add ACTLR data and support for qcom_smmu_500.
>>
>> Changes in v18 from v17_RESEND:
>>   - 1/5 : No changes
>>   - 2/5 : No changes - reviewed-by tags collected
>>   - 3/5 : Addition of
>>     pm_runtime_resume_and_get()/pm_runtime_put_autosuspend()
>>     around register access of PRR related private interfaces
>>     as discussed in v17_RESEND.
>>   - 4/5, 5/5 : No changes - reviewed-by tags collected
>>   Link to v17_RESEND:
>>   https://lore.kernel.org/all/20241114160721.1527934-1-quic_bibekkum@quicinc.com/
>>
>> Resend of v17:
>>   Addition of minor fix of the build warning reported by kernel test robot [1] by powerpc_random config [2].
>>   [1]:https://lore.kernel.org/all/202411140748.6mcFdJdO-lkp@intel.com/#t
>>   [2]:https://download.01.org/0day-ci/archive/20241114/202411140748.6mcFdJdO-lkp@intel.com/config
>>
>> Changes in v17 from v16:
>>   Tags provided earlier not collected yet on patch 1/5, 3/5, 4/5, 5/5
>>   due to the following revisions:
>>   - 1/5 : Move the CPRE workaround out of qualcomm specific logic and gate with config
>>           , update the silicon-errata.rst file
>>   - 2/5 : No changes - reviewed-by tags collected
>>   - 3/5 : Move the compatible check before assignment of callback as suggested.
>>   - 4/5 : Add the actlr setting for *adreno variant* of MMU-500 as well.
>>   - 5/5 : Due to changes in 1/5, minor refactoring had to be done before adding table.
>>   Link to v16:
>>   https://lore.kernel.org/all/20241008125410.3422512-1-quic_bibekkum@quicinc.com/
>>
>> Changes in v16 from v15:
>>   - Incorporate Dimitry's suggestion on patch 4/5 to use dev_dbg instead of dev_notice.
>>   - Fix kernel test robot warning [1] coming for 32bit architecture configuration.
>>   - Updatingthe tags
>>   [1]: https://lore.kernel.org/all/202409230343.Q8KnYl2w-lkp@intel.com/
>>   Link to v15:
>>   https://lore.kernel.org/all/20240920155813.3434021-1-quic_bibekkum@quicinc.com/
>>
>> Changes in v15 from v14:
>>   - As discussed with Robin and Dmitry modify the actlr table and logic to use
>>     compatible string instead of sid, mask for device matching which is
>>     similar to qcom_smmu_client_of_match mechanism.
>>   - Expand the comment in qcom_smmu500_reset to document reason why CPRE bit is re-enabled again
>>     after arm_mmu500_reset resets the bit.
>>   - Rearrange the series in order to keep prefetch setting patches in the end.
>>   Link to v14:
>>   https://lore.kernel.org/all/20240816174259.2056829-1-quic_bibekkum@quicinc.com/
>>
> 
> Hi all,
> 
> I've been looking at the evolution of the Qualcomm SMMU driver
> (arm-smmu-qcom.c) and had a question about the design change for
> configuring the SMMU_CB_ACTLR register.
> 
> It appears there are two different approaches:
> 
> 1. The "SID" Approach (Older): In some versions, a driver would use a
> large, platform-specific struct (e.g., sa8775p_apps_actlr_cfg) that
> maps individual Stream IDs (SIDs) to specific ACTLR values. This
> allowed for very granular, per-SID tuning. For example, a device with
> 10 SIDs could have a specific setting for just one (0x2141), while the
> others used a default.
> 
> 2. The "Compatible String" Approach (Newer/Upstream): The current
> upstream driver appears to use a client_match array (an of_device_id
> list) in qcom_smmu_init_context. This maps a device's compatible
> string to a single ACTLR value, which is then written to the device's
> assigned Context Bank.
> 
> I want to make sure I understand the implications of this new, simpler
> approach, as it seems to introduce a trade-off where granularity is
> lost:
> 
> Multiple SIDs, One Device: A single device that uses many SIDs in the
> device tree (e.g., the video codec, which might list 0x2141, 0x25C1,
> 0x2161, etc.) will now have one ACTLR setting applied to the Context
> Bank that serves all of those SIDs, even if the old SID-based list
> only specified a setting for one of them.
> 
> Am I correct in this analysis? I'm assuming this was an intentional
> design choice to simplify the driver, based on the assumption that all
> SIDs for a single device (and all devices with the same compatible)
> can share the same ACTLR tuning.
> 

Hi Eric,

If a device has multiple SIDs, all serving the same functionality and 
grouped under the same "iommus" field, for example:

iommus = <&apps_smmu, 0x2141, 0x0>,
           <&apps_smmu, 0x25c1, 0x0>,
           <&apps_smmu, 0x2161, 0x0>;

In this case, all the SIDs will be associated with the same context 
bank. Even if the three SIDs have different ACTLR settings, since 
SMMU_CB_ACTLR is per CB setting, all SIDs attached to that bank will 
share the same ACTLR configuration. This is why we designed it to be 
"per device / per compatible".

Thanks & regards,
Bibek

> I'm working on porting settings for an sa8775p board and just want to
> ensure I'm migrating the logic correctly to this new client_match
> method.
> 
> Thanks for any clarification you can provide.
> 
> Best regards,
> 
>     Enric
> 
> 
>> Changes in v14 from v13:
>>   Patch 6/6:
>>   - As discussed incorprate changes to carry out PRR implementation only for
>>     targets based on MMU-500 by using compat string based SMMU version detection.
>>   - Split the set_actlr interface into two separate interface namely set_prr_bit
>>     and set_prr_addr to set the prr enable bit and prr page address resepectively.
>>   Patch 3/6:
>>    - Fix a bug in gfx actlr_config which is uncovered while testing the gfx actlr setting in sc7280
>>      during PRR experiment which prevented clients on certain sids of gfx smmmu to be skipped during
>>      setting up of the ACTLR values : Fix involves swapping the arguments passed in smr_is_subset to make
>>       device smr <from devicetree> a subset of actlr_config table entries < defined in the driver>.
>>   Patch 4/6, 5/6:
>>    - Sort the actlr table values in increasing order of the SIDs.
>>   Link to v13:
>>   https://lore.kernel.org/all/20240628140435.1652374-1-quic_bibekkum@quicinc.com/
>>
>> Changes in v13 from v12:
>>   - Fix the compilation issues reported by kernel test robot [1].
>>   [1]: https://lore.kernel.org/all/202406281241.xEX0TWjt-lkp@intel.com/#t
>>   Link to v12:
>>   https://lore.kernel.org/all/20240626143020.3682243-1-quic_bibekkum@quicinc.com/
>>
>> Changes in v12 from v11:
>>   Changes to incorporate suggestion from Rob:
>>   - Fix the set and reset logic for prr bit as pointed out in v11-6/6.
>>   - Rename set_actlr_bit function name to set_prr.
>>   - Add extension for PRR name as Partially-Resident-Region in comments
>>     for set_prr function.
>>   - Add few missing sids for sc7280 in patch-5/6.
>>   Link to v11:
>>   https://lore.kernel.org/all/20240605121713.3596499-1-quic_bibekkum@quicinc.com/
>>
>> Changes in v11 from v10:
>>   - Include a new patch 6/6 to add support for ACTLR PRR bit
>>     through adreno-smmu-priv interface as suggested by Rob and Dmitry.
>>   Link to v10:
>>   https://lore.kernel.org/all/20240524131800.2288259-1-quic_bibekkum@quicinc.com/
>>
>> Changes in v10 from v9:
>>   - Added reviewed-by tags 1/5,2/5,3/5.
>>   Changes incorporated:
>>   - Remove redundant PRR bit setting from gfx actlr table(patch 4/5,5/5)
>>     as this bit needs special handling in the gfx driver along with
>>     the associated register settings.
>>   Link to discussion on PRR bit:
>>   https://lore.kernel.org/all/f2222714-1e00-424e-946d-c314d55541b8@quicinc.com/
>>   Link to v9:
>>   https://lore.kernel.org/all/20240123144543.9405-1-quic_bibekkum@quicinc.com/
>>
>> Changes in v9 from v8:
>>   Changes to incorporate suggestions from Konrad as follows:
>>   - Re-wrap struct members of actlr_variant in patch 4/5,5/5
>>     in a cleaner way.
>>   - Move actlr_config members to the header.
>>   Link to v8:
>>   https://lore.kernel.org/all/20240116150411.23876-1-quic_bibekkum@quicinc.com/
>>
>> Changes in v8 from v7:
>>   - Added reviewed-by tags on patch 1/5, 2/5.
>>   Changes to incorporate suggestions from Pavan and Konrad:
>>   - Remove non necessary extra lines.
>>   - Use num_smmu and num_actlrcfg to store the array size and use the
>>     same to traverse the table and save on sentinel space along with
>>     indentation levels.
>>   - Refactor blocks containing qcom_smmu_set_actlr to remove block
>>     repetition in patch 3/5.
>>   - Change copyright year from 2023 to 2022-2023 in patch 3/5.
>>   - Modify qcom_smmu_match_data.actlrvar and actlr_variant.actlrcfg to
>>     const pointer to a const resource.
>>   - use C99 designated initializers and put the address first.
>>   Link to v7:
>>   https://lore.kernel.org/all/20240109114220.30243-1-quic_bibekkum@quicinc.com/
>>
>> Changes in v7 from v6:
>>   Changes to incorporate suggestions from Dmitry as follows:
>>   - Use io_start address instead of compatible string to identify the
>>     correct instance by comparing with smmu start address and check for
>>     which smmu the corresponding actlr table is to be picked.
>> Link to v6:
>> https://lore.kernel.org/all/20231220133808.5654-1-quic_bibekkum@quicinc.com/
>>
>> Changes in v6 from v5:
>>   - Remove extra Suggested-by tags.
>>   - Add return check for arm_mmu500_reset in 1/5 as discussed.
>> Link to v5:
>> https://lore.kernel.org/all/20231219135947.1623-1-quic_bibekkum@quicinc.com/
>>
>> Changes in v5 from v4:
>>   New addition:
>>   - Modify copyright year in arm-smmu-qcom.h to 2023 from 2022.
>>   Changes to incorporate suggestions from Dmitry as follows:
>>   - Modify the defines for prefetch in (foo << bar) format
>>     as suggested.(FIELD_PREP could not be used in defines
>>     is not inside any block/function)
>>   Changes to incorporate suggestions from Konrad as follows:
>>   - Shift context caching enablement patch as 1/5 instead of 5/5 to
>>     be picked up as independent patch.
>>   - Fix the codestyle to orient variables in reverse xmas tree format
>>     for patch 1/5.
>>   - Fix variable name in patch 1/5 as suggested.
>>   Link to v4:
>> https://lore.kernel.org/all/20231215101827.30549-1-quic_bibekkum@quicinc.com/
>>
>> Changes in v4 from v3:
>>   New addition:
>>   - Remove actlrcfg_size and use NULL end element instead to traverse
>>     the actlr table, as this would be a cleaner approach by removing
>>     redundancy of actlrcfg_size.
>>   - Renaming of actlr set function to arm_smmu_qcom based proprietary
>>     convention.
>>   - break from loop once sid is found and ACTLR value is initialized
>>     in qcom_smmu_set_actlr.
>>   - Modify the GFX prefetch value separating into 2 sensible defines.
>>   - Modify comments for prefetch defines as per SMMU-500 TRM.
>>   Changes to incorporate suggestions from Konrad as follows:
>>   - Use Reverse-Christmas-tree sorting wherever applicable.
>>   - Pass arguments directly to arm_smmu_set_actlr instead of creating
>>     duplicate variables.
>>   - Use array indexing instead of direct pointer addressed by new
>>     addition of eliminating actlrcfg_size.
>>   - Switch the HEX value's case from upper to lower case in SC7280
>>     actlrcfg table.
>>   Changes to incorporate suggestions from Dmitry as follows:
>>   - Separate changes not related to ACTLR support to different commit
>>     with patch 5/5.
>>   - Using pointer to struct for arguments in smr_is_subset().
>>   Changes to incorporate suggestions from Bjorn as follows:
>>   - fix the commit message for patch 2/5 to properly document the
>>     value space to avoid confusion.
>>   Fixed build issues reported by kernel test robot [1] for
>>   arm64-allyesconfig [2].
>>   [1]: https://lore.kernel.org/all/202312011750.Pwca3TWE-lkp@intel.com/
>>   [2]:
>> https://download.01.org/0day-ci/archive/20231201/202312011750.Pwca3TWE-lkp@intel.com/config
>>   Link to v3:
>> https://lore.kernel.org/all/20231127145412.3981-1-quic_bibekkum@quicinc.com/
>>
>> Changes in v3 from v2:
>>   New addition:
>>   - Include patch 3/4 for adding ACTLR support and data for SC7280.
>>   - Add driver changes for actlr support in gpu smmu.
>>   - Add target wise actlr data and implementation ops for gpu smmu.
>>   Changes to incorporate suggestions from Robin as follows:
>>   - Match the ACTLR values with individual corresponding SID instead
>>     of assuming that any SMR will be programmed to match a superset of
>>     the data.
>>   - Instead of replicating each elements from qcom_smmu_match_data to
>>     qcom_smmu structre during smmu device creation, replace the
>>     replicated members with qcom_smmu_match_data structure inside
>>     qcom_smmu structre and handle the dereference in places that
>>     requires them.
>>   Changes to incorporate suggestions from Dmitry and Konrad as follows:
>>   - Maintain actlr table inside a single structure instead of
>>     nested structure.
>>   - Rename prefetch defines to more appropriately describe their
>>     behavior.
>>   - Remove SM8550 specific implementation ops and roll back to default
>>     qcom_smmu_500_impl implementation ops.
>>   - Add back the removed comments which are NAK.
>>   - Fix commit description for patch 4/4.
>>   Link to v2:
>> https://lore.kernel.org/all/20231114135654.30475-1-quic_bibekkum@quicinc.com/
>>
>> Changes in v2 from v1:
>>   - Incorporated suggestions on v1 from Dmitry,Konrad,Pratyush.
>>   - Added defines for ACTLR values.
>>   - Linked sm8550 implementation structure to corresponding
>>     compatible string.
>>   - Repackaged actlr value set implementation to separate function.
>>   - Fixed indentation errors.
>>   - Link to v1:
>> https://lore.kernel.org/all/20231103215124.1095-1-quic_bibekkum@quicinc.com/
>>
>> Changes in v1 from RFC:
>>   - Incorporated suggestion form Robin on RFC
>>   - Moved the actlr data table into driver, instead of maintaining
>>     it inside soc specific DT and piggybacking on exisiting iommus
>>     property (iommu = <SID, MASK, ACTLR>) to set this value during
>>     smmu probe.
>>   - Link to RFC:
>> https://lore.kernel.org/all/a01e7e60-6ead-4a9e-ba90-22a8a6bbd03f@quicinc.com/
>>
>> Bibek Kumar Patro (5):
>>    iommu/arm-smmu: re-enable context caching in smmu reset operation
>>    iommu/arm-smmu: refactor qcom_smmu structure to include single pointer
>>    iommu/arm-smmu: add support for PRR bit setup
>>    iommu/arm-smmu: introduction of ACTLR for custom prefetcher settings
>>    iommu/arm-smmu: add ACTLR data and support for qcom_smmu_500
>>
>>   Documentation/arch/arm64/silicon-errata.rst   |   3 +-
>>   drivers/iommu/Kconfig                         |  12 ++
>>   drivers/iommu/arm/arm-smmu/arm-smmu-impl.c    |   5 +-
>>   .../iommu/arm/arm-smmu/arm-smmu-qcom-debug.c  |   2 +-
>>   drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c    | 120 +++++++++++++++++-
>>   drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h    |   3 +-
>>   drivers/iommu/arm/arm-smmu/arm-smmu.h         |   2 +
>>   include/linux/adreno-smmu-priv.h              |  14 ++
>>   8 files changed, 155 insertions(+), 6 deletions(-)
>>
>> --
>> 2.34.1
>>
>>
> 

Re: [PATCH v18 0/5] iommu/arm-smmu: introduction of ACTLR implementation for Qualcomm SoCs

[Konrad Dybcio]

On 11/12/25 9:45 AM, Bibek Kumar Patro wrote:
> 
> 
> On 11/7/2025 2:58 PM, Enric Balletbo i Serra wrote:
>> On Thu, Dec 12, 2024 at 4:14 PM Bibek Kumar Patro
>> <quic_bibekkum@quicinc.com> wrote:
>>>
>>> This patch series consist of six parts and covers the following:
>>>
>>> 1. Provide option to re-enable context caching to retain prefetcher
>>>     settings during reset and runtime suspend.
>>>
>>> 2. Remove cfg inside qcom_smmu structure and replace it with single
>>>     pointer to qcom_smmu_match_data avoiding replication of multiple
>>>     members from same.
>>>
>>> 3. Add support for ACTLR PRR bit setup via adreno-smmu-priv interface.
>>>
>>> 4. Introduce intital set of driver changes to implement ACTLR register
>>>     for custom prefetcher settings in Qualcomm SoCs.
>>>
>>> 5. Add ACTLR data and support for qcom_smmu_500.
>>>
>>> Changes in v18 from v17_RESEND:
>>>   - 1/5 : No changes
>>>   - 2/5 : No changes - reviewed-by tags collected
>>>   - 3/5 : Addition of
>>>     pm_runtime_resume_and_get()/pm_runtime_put_autosuspend()
>>>     around register access of PRR related private interfaces
>>>     as discussed in v17_RESEND.
>>>   - 4/5, 5/5 : No changes - reviewed-by tags collected
>>>   Link to v17_RESEND:
>>>   https://lore.kernel.org/all/20241114160721.1527934-1-quic_bibekkum@quicinc.com/
>>>
>>> Resend of v17:
>>>   Addition of minor fix of the build warning reported by kernel test robot [1] by powerpc_random config [2].
>>>   [1]:https://lore.kernel.org/all/202411140748.6mcFdJdO-lkp@intel.com/#t
>>>   [2]:https://download.01.org/0day-ci/archive/20241114/202411140748.6mcFdJdO-lkp@intel.com/config
>>>
>>> Changes in v17 from v16:
>>>   Tags provided earlier not collected yet on patch 1/5, 3/5, 4/5, 5/5
>>>   due to the following revisions:
>>>   - 1/5 : Move the CPRE workaround out of qualcomm specific logic and gate with config
>>>           , update the silicon-errata.rst file
>>>   - 2/5 : No changes - reviewed-by tags collected
>>>   - 3/5 : Move the compatible check before assignment of callback as suggested.
>>>   - 4/5 : Add the actlr setting for *adreno variant* of MMU-500 as well.
>>>   - 5/5 : Due to changes in 1/5, minor refactoring had to be done before adding table.
>>>   Link to v16:
>>>   https://lore.kernel.org/all/20241008125410.3422512-1-quic_bibekkum@quicinc.com/
>>>
>>> Changes in v16 from v15:
>>>   - Incorporate Dimitry's suggestion on patch 4/5 to use dev_dbg instead of dev_notice.
>>>   - Fix kernel test robot warning [1] coming for 32bit architecture configuration.
>>>   - Updatingthe tags
>>>   [1]: https://lore.kernel.org/all/202409230343.Q8KnYl2w-lkp@intel.com/
>>>   Link to v15:
>>>   https://lore.kernel.org/all/20240920155813.3434021-1-quic_bibekkum@quicinc.com/
>>>
>>> Changes in v15 from v14:
>>>   - As discussed with Robin and Dmitry modify the actlr table and logic to use
>>>     compatible string instead of sid, mask for device matching which is
>>>     similar to qcom_smmu_client_of_match mechanism.
>>>   - Expand the comment in qcom_smmu500_reset to document reason why CPRE bit is re-enabled again
>>>     after arm_mmu500_reset resets the bit.
>>>   - Rearrange the series in order to keep prefetch setting patches in the end.
>>>   Link to v14:
>>>   https://lore.kernel.org/all/20240816174259.2056829-1-quic_bibekkum@quicinc.com/
>>>
>>
>> Hi all,
>>
>> I've been looking at the evolution of the Qualcomm SMMU driver
>> (arm-smmu-qcom.c) and had a question about the design change for
>> configuring the SMMU_CB_ACTLR register.
>>
>> It appears there are two different approaches:
>>
>> 1. The "SID" Approach (Older): In some versions, a driver would use a
>> large, platform-specific struct (e.g., sa8775p_apps_actlr_cfg) that
>> maps individual Stream IDs (SIDs) to specific ACTLR values. This
>> allowed for very granular, per-SID tuning. For example, a device with
>> 10 SIDs could have a specific setting for just one (0x2141), while the
>> others used a default.
>>
>> 2. The "Compatible String" Approach (Newer/Upstream): The current
>> upstream driver appears to use a client_match array (an of_device_id
>> list) in qcom_smmu_init_context. This maps a device's compatible
>> string to a single ACTLR value, which is then written to the device's
>> assigned Context Bank.
>>
>> I want to make sure I understand the implications of this new, simpler
>> approach, as it seems to introduce a trade-off where granularity is
>> lost:
>>
>> Multiple SIDs, One Device: A single device that uses many SIDs in the
>> device tree (e.g., the video codec, which might list 0x2141, 0x25C1,
>> 0x2161, etc.) will now have one ACTLR setting applied to the Context
>> Bank that serves all of those SIDs, even if the old SID-based list
>> only specified a setting for one of them.
>>
>> Am I correct in this analysis? I'm assuming this was an intentional
>> design choice to simplify the driver, based on the assumption that all
>> SIDs for a single device (and all devices with the same compatible)
>> can share the same ACTLR tuning.
>>
> 
> Hi Eric,
> 
> If a device has multiple SIDs, all serving the same functionality and grouped under the same "iommus" field, for example:
> 
> iommus = <&apps_smmu, 0x2141, 0x0>,
>           <&apps_smmu, 0x25c1, 0x0>,
>           <&apps_smmu, 0x2161, 0x0>;
> 
> In this case, all the SIDs will be associated with the same context bank. Even if the three SIDs have different ACTLR settings, since SMMU_CB_ACTLR is per CB setting, all SIDs attached to that bank will share the same ACTLR configuration. This is why we designed it to be "per device / per compatible".

Does that suggest the settings may be slightly suboptimal?

There's some work being done to allow more granular association of
the passed SIDs:

https://lore.kernel.org/linux-arm-msm/20250928171718.436440-1-charan.kalla@oss.qualcomm.com/

Konrad

Re: [PATCH v18 0/5] iommu/arm-smmu: introduction of ACTLR implementation for Qualcomm SoCs

[Charan Teja Kalla]

On 11/12/2025 7:04 PM, Konrad Dybcio wrote:
>> Hi Eric,
>>
>> If a device has multiple SIDs, all serving the same functionality and grouped under the same "iommus" field, for example:
>>
>> iommus = <&apps_smmu, 0x2141, 0x0>,
>>           <&apps_smmu, 0x25c1, 0x0>,
>>           <&apps_smmu, 0x2161, 0x0>;
>>
>> In this case, all the SIDs will be associated with the same context bank. Even if the three SIDs have different ACTLR settings, since SMMU_CB_ACTLR is per CB setting, all SIDs attached to that bank will share the same ACTLR configuration. This is why we designed it to be "per device / per compatible".
> Does that suggest the settings may be slightly suboptimal?
> 
Or it is limitation to use the ACTLR?

> There's some work being done to allow more granular association of
> the passed SIDs:
> 
> https://lore.kernel.org/linux-arm-msm/20250928171718.436440-1-
> charan.kalla@oss.qualcomm.com/
Sorry, I am unable to link this limitation for actlr setting with the
work. Can you elaborate please?

IIUC, unless the SIDs are totally separated per actlr settings and
attached to CB(which are limited), this can't be achieved...but may be a
question here to check is it really a __valid__ to associate a different
actlr settings SID to use the same CB?

Re: [PATCH v18 0/5] iommu/arm-smmu: introduction of ACTLR implementation for Qualcomm SoCs

[Konrad Dybcio]

On 11/13/25 2:55 PM, Charan Teja Kalla wrote:
> 
> 
> On 11/12/2025 7:04 PM, Konrad Dybcio wrote:
>>> Hi Eric,
>>>
>>> If a device has multiple SIDs, all serving the same functionality and grouped under the same "iommus" field, for example:
>>>
>>> iommus = <&apps_smmu, 0x2141, 0x0>,
>>>           <&apps_smmu, 0x25c1, 0x0>,
>>>           <&apps_smmu, 0x2161, 0x0>;
>>>
>>> In this case, all the SIDs will be associated with the same context bank. Even if the three SIDs have different ACTLR settings, since SMMU_CB_ACTLR is per CB setting, all SIDs attached to that bank will share the same ACTLR configuration. This is why we designed it to be "per device / per compatible".
>> Does that suggest the settings may be slightly suboptimal?

I don't understand your question

> Or it is limitation to use the ACTLR?
> 
>> There's some work being done to allow more granular association of
>> the passed SIDs:
>>
>> https://lore.kernel.org/linux-arm-msm/20250928171718.436440-1-
>> charan.kalla@oss.qualcomm.com/
> Sorry, I am unable to link this limitation for actlr setting with the
> work. Can you elaborate please?

Because your email client is misconfigured and it broke the line.. If
it's thunderbird, pretty sure we have a "change these configs" type
section on go/upstream, please take a look

> IIUC, unless the SIDs are totally separated per actlr settings and
> attached to CB(which are limited), this can't be achieved...but may be a
> question here to check is it really a __valid__ to associate a different
> actlr settings SID to use the same CB?

The last question you asked is certainly a valid one

But I was wondering if iommu-map could be useful to resolve this, where
we choose an abstract set of function IDs and then handle the IOMMU
configuration manually, based on the func_id-delimited sets:

iommu-map = <FUNC_ID0 &iommu_phandle CELL0 ... CELLN-1>,
	    <FUNC_ID0 &iommu_phandle CELL0 ... CELLN-1>,
	    <FUNC_ID1 &iommu_phandle CELL0 ... CELLN-1>,
	    <FUNC_ID2 &iommu_phandle CELL0 ... CELLN-1>;

But perhaps that's more useful from the driver-that-handles-the-device
perspective

Konrad