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From: Conor Dooley <conor@kernel.org>
To: "Clément Léger" <cleger@rivosinc.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	Himanshu Chauhan <hchauhan@ventanamicro.com>,
	Anup Patel <apatel@ventanamicro.com>,
	Xu Lu <luxu.kernel@bytedance.com>,
	Atish Patra <atishp@atishpatra.org>
Subject: Re: [PATCH v3 3/4] drivers: firmware: add riscv SSE support
Date: Fri, 24 Jan 2025 14:15:43 +0000	[thread overview]
Message-ID: <20250124-banker-unbeaten-aef71ed58867@spud> (raw)
In-Reply-To: <ae912564-60b7-4733-ab46-15fbba16ed94@rivosinc.com>

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On Thu, Jan 23, 2025 at 11:52:35AM +0100, Clément Léger wrote:
> On 16/01/2025 14:58, Conor Dooley wrote:
> >> +static int sse_sbi_event_func(struct sse_event *event, unsigned long func)
> >> +{
> >> +	struct sbiret ret;
> >> +	u32 evt = event->evt;
> >> +
> >> +	ret = sbi_ecall(SBI_EXT_SSE, func, evt, 0, 0, 0, 0, 0);
> >> +	if (ret.error)
> >> +		pr_debug("Failed to execute func %lx, event %x, error %ld\n",
> >> +			 func, evt, ret.error);
> > 
> > Why's this only at a debug level?
> 
> That's only really meaningful for debugging, this error is often
> reported to the upper level and ends up to the final caller. I don't
> think we should be too verbose for such drivers, but rather propagate
> the error. If one wants to debug, then, just enable DEBUG.
> 
> But that's only my opinion, if you'd prefer all pr_debug to be either
> removed or changed to pr_err(), I'll do it.

Nah, you can leave it as is, you know better than I about how helpful it
would be as an error.

> >> +int sse_event_enable(struct sse_event *event)
> >> +{
> >> +	int ret = 0;
> >> +	struct sse_per_cpu_evt cpu_evt;
> >> +
> >> +	scoped_guard(mutex, &sse_mutex) {
> >> +		cpus_read_lock();
> >> +		if (sse_event_is_global(event->evt)) {
> >> +			ret = sse_sbi_enable_event(event);
> >> +		} else {
> >> +			cpu_evt.event = event;
> >> +			atomic_set(&cpu_evt.error, 0);
> >> +			cpu_evt.func = SBI_SSE_EVENT_ENABLE;
> >> +			on_each_cpu(sse_event_per_cpu_func, &cpu_evt, 1);
> >> +			ret = atomic_read(&cpu_evt.error);
> >> +			if (ret) {
> >> +				cpu_evt.func = SBI_SSE_EVENT_DISABLE;
> >> +				on_each_cpu(sse_event_per_cpu_func, &cpu_evt,
> >> +					    1);
> > 
> > nit: this should fit on one line, no?
> 
> the trailing ; is above 80 characters. But if you are ok with 100 char,
> I can go for it.

The slight improvement in readability trumps the slight increase over 80
characters every time for me.

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  reply	other threads:[~2025-01-24 14:17 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-12-06 16:30 [PATCH v3 0/4] riscv: add support for SBI Supervisor Software Events Clément Léger
2024-12-06 16:30 ` [PATCH v3 1/4] riscv: add SBI SSE extension definitions Clément Léger
2024-12-06 16:30 ` [PATCH v3 2/4] riscv: add support for SBI Supervisor Software Events extension Clément Léger
2024-12-10  4:51   ` Himanshu Chauhan
2025-01-22 12:15   ` Alexandre Ghiti
2025-01-22 12:23     ` Alexandre Ghiti
2025-01-23  8:41       ` Clément Léger
2025-01-23  8:39     ` Clément Léger
2025-01-27  8:09       ` Alexandre Ghiti
2025-01-28  8:10         ` Clément Léger
2025-01-30 10:01           ` Alexandre Ghiti
2025-03-19 17:08   ` Andrew Jones
2025-03-20  8:16     ` Clément Léger
2025-03-20 11:52       ` Andrew Jones
2025-03-20 12:26         ` Clément Léger
2024-12-06 16:30 ` [PATCH v3 3/4] drivers: firmware: add riscv SSE support Clément Léger
2024-12-13  5:03   ` Himanshu Chauhan
2024-12-13  8:33     ` Clément Léger
2025-01-16 13:58   ` Conor Dooley
2025-01-23 10:52     ` Clément Léger
2025-01-24 14:15       ` Conor Dooley [this message]
2024-12-06 16:31 ` [PATCH v3 4/4] perf: RISC-V: add support for SSE event Clément Léger

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