From: Andrew Jones <ajones@ventanamicro.com>
To: "Clément Léger" <cleger@rivosinc.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Himanshu Chauhan <hchauhan@ventanamicro.com>,
Anup Patel <apatel@ventanamicro.com>,
Xu Lu <luxu.kernel@bytedance.com>,
Atish Patra <atishp@atishpatra.org>
Subject: Re: [PATCH v3 2/4] riscv: add support for SBI Supervisor Software Events extension
Date: Wed, 19 Mar 2025 18:08:43 +0100 [thread overview]
Message-ID: <20250319-46b625cf8b771616d4c7c053@orel> (raw)
In-Reply-To: <20241206163102.843505-3-cleger@rivosinc.com>
On Fri, Dec 06, 2024 at 05:30:58PM +0100, Clément Léger wrote:
...
> +int arch_sse_init_event(struct sse_event_arch_data *arch_evt, u32 evt_id, int cpu)
> +{
> + void *stack;
> +
> + arch_evt->evt_id = evt_id;
> + stack = sse_stack_alloc(cpu, SSE_STACK_SIZE);
> + if (!stack)
> + return -ENOMEM;
> +
> + arch_evt->stack = stack + SSE_STACK_SIZE;
> +
> + if (sse_init_scs(cpu, arch_evt))
> + goto free_stack;
> +
> + if (is_kernel_percpu_address((unsigned long)&arch_evt->interrupted)) {
> + arch_evt->interrupted_state_phys =
> + per_cpu_ptr_to_phys(&arch_evt->interrupted);
> + } else {
> + arch_evt->interrupted_state_phys =
> + virt_to_phys(&arch_evt->interrupted);
> + }
> +
> + return 0;
Hi Clément,
Testing SSE support with tools/testing/selftests/kvm/riscv/sbi_pmu_test
led to an opensbi sbi_trap_error because the output_phys_lo address passed
to sbi_sse_read_attrs() wasn't a physical address. The reason is that
is_kernel_percpu_address() can only be used on static percpu addresses,
but local sse events get their percpu addresses with alloc_percpu(), so
is_kernel_percpu_address() was returning false even for local events. I
made the following changes to get things working.
Thanks,
drew
diff --git a/arch/riscv/kernel/sse.c b/arch/riscv/kernel/sse.c
index b48ae69dad8d..f46893946086 100644
--- a/arch/riscv/kernel/sse.c
+++ b/arch/riscv/kernel/sse.c
@@ -100,12 +100,12 @@ int arch_sse_init_event(struct sse_event_arch_data *arch_evt, u32 evt_id, int cp
if (sse_init_scs(cpu, arch_evt))
goto free_stack;
- if (is_kernel_percpu_address((unsigned long)&arch_evt->interrupted)) {
+ if (sse_event_is_global(evt_id)) {
arch_evt->interrupted_state_phys =
- per_cpu_ptr_to_phys(&arch_evt->interrupted);
+ virt_to_phys(&arch_evt->interrupted);
} else {
arch_evt->interrupted_state_phys =
- virt_to_phys(&arch_evt->interrupted);
+ per_cpu_ptr_to_phys(&arch_evt->interrupted);
}
return 0;
diff --git a/drivers/firmware/riscv/riscv_sse.c b/drivers/firmware/riscv/riscv_sse.c
index 511db9ad7a9e..fef375046f75 100644
--- a/drivers/firmware/riscv/riscv_sse.c
+++ b/drivers/firmware/riscv/riscv_sse.c
@@ -62,11 +62,6 @@ void sse_handle_event(struct sse_event_arch_data *arch_event,
ret);
}
-static bool sse_event_is_global(u32 evt)
-{
- return !!(evt & SBI_SSE_EVENT_GLOBAL);
-}
-
static
struct sse_event *sse_event_get(u32 evt)
{
diff --git a/include/linux/riscv_sse.h b/include/linux/riscv_sse.h
index 16700677f1e8..06b757b036b0 100644
--- a/include/linux/riscv_sse.h
+++ b/include/linux/riscv_sse.h
@@ -8,6 +8,7 @@
#include <linux/types.h>
#include <linux/linkage.h>
+#include <asm/sbi.h>
struct sse_event;
struct pt_regs;
@@ -16,6 +17,11 @@ struct ghes;
typedef int (sse_event_handler)(u32 event_num, void *arg, struct pt_regs *regs);
+static inline bool sse_event_is_global(u32 evt)
+{
+ return !!(evt & SBI_SSE_EVENT_GLOBAL);
+}
+
#ifdef CONFIG_RISCV_SSE
struct sse_event *sse_event_register(u32 event_num, u32 priority,
next prev parent reply other threads:[~2025-03-19 17:10 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-06 16:30 [PATCH v3 0/4] riscv: add support for SBI Supervisor Software Events Clément Léger
2024-12-06 16:30 ` [PATCH v3 1/4] riscv: add SBI SSE extension definitions Clément Léger
2024-12-06 16:30 ` [PATCH v3 2/4] riscv: add support for SBI Supervisor Software Events extension Clément Léger
2024-12-10 4:51 ` Himanshu Chauhan
2025-01-22 12:15 ` Alexandre Ghiti
2025-01-22 12:23 ` Alexandre Ghiti
2025-01-23 8:41 ` Clément Léger
2025-01-23 8:39 ` Clément Léger
2025-01-27 8:09 ` Alexandre Ghiti
2025-01-28 8:10 ` Clément Léger
2025-01-30 10:01 ` Alexandre Ghiti
2025-03-19 17:08 ` Andrew Jones [this message]
2025-03-20 8:16 ` Clément Léger
2025-03-20 11:52 ` Andrew Jones
2025-03-20 12:26 ` Clément Léger
2024-12-06 16:30 ` [PATCH v3 3/4] drivers: firmware: add riscv SSE support Clément Léger
2024-12-13 5:03 ` Himanshu Chauhan
2024-12-13 8:33 ` Clément Léger
2025-01-16 13:58 ` Conor Dooley
2025-01-23 10:52 ` Clément Léger
2025-01-24 14:15 ` Conor Dooley
2024-12-06 16:31 ` [PATCH v3 4/4] perf: RISC-V: add support for SSE event Clément Léger
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250319-46b625cf8b771616d4c7c053@orel \
--to=ajones@ventanamicro.com \
--cc=apatel@ventanamicro.com \
--cc=atishp@atishpatra.org \
--cc=cleger@rivosinc.com \
--cc=hchauhan@ventanamicro.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=luxu.kernel@bytedance.com \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox