[boot-wrapper] aarch64: Enable access into FEAT_PMUv3p9 registers from EL2 and below

[boot-wrapper] aarch64: Enable access into FEAT_PMUv3p9 registers from EL2 and below

[Anshuman Khandual]

FEAT_PMUv3p9 adds system register PMUACR_EL1 and similarly FEAT_PMUv3_ICNTR
adds system registers PMICFILTR_EL0 and PMICNTR_EL0. But access into these
system registers from EL2 and below exception levels, will trap into EL3
unless MDCR_EL3.EnPM2 is set.

Enable access to FEAT_PMUv3p9 registers when they are implemented.

Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 arch/aarch64/include/asm/cpu.h | 2 ++
 arch/aarch64/init.c            | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
index e049cda..b04bf71 100644
--- a/arch/aarch64/include/asm/cpu.h
+++ b/arch/aarch64/include/asm/cpu.h
@@ -56,6 +56,7 @@
 #define MDCR_EL3_SBRBE_NOTRAP_NOPROHIBIT	(UL(3) << 32)
 #define MDCR_EL3_ENPMSN				BIT(36)
 #define MDCR_EL3_EBWE				BIT(43)
+#define MDCR_EL3_EnPM2				BIT(7)
 
 #define SCR_EL3_RES1			BITS(5, 4)
 #define SCR_EL3_NS			BIT(0)
@@ -87,6 +88,7 @@
 #define ID_AA64DFR0_EL1_PMSVER		BITS(35, 32)
 #define ID_AA64DFR0_EL1_TRACEBUFFER	BITS(47, 44)
 #define ID_AA64DFR0_EL1_BRBE		BITS(55, 52)
+#define ID_AA64DFR0_EL1_PMUVER		BITS(11, 8)
 #define ID_AA64DFR0_EL1_DEBUGVER	BITS(3, 0)
 
 #define ID_AA64ISAR0_EL1_TME		BITS(27, 24)
diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c
index 54e4cc4..fe7ed5f 100644
--- a/arch/aarch64/init.c
+++ b/arch/aarch64/init.c
@@ -152,6 +152,9 @@ static void cpu_init_el3(void)
 	if (mrs_field(ID_AA64DFR0_EL1, DEBUGVER) >= 11)
 		mdcr |= MDCR_EL3_EBWE;
 
+	if (mrs_field(ID_AA64DFR0_EL1, PMUVER) >= 0b1001)
+		mdcr |= MDCR_EL3_EnPM2;
+
 	msr(MDCR_EL3, mdcr);
 
 	if (mrs_field(ID_AA64PFR0_EL1, SVE)) {
-- 
2.25.1

Re: [boot-wrapper] aarch64: Enable access into FEAT_PMUv3p9 registers from EL2 and below

[Mark Rutland]

On Thu, Feb 27, 2025 at 09:46:03AM +0530, Anshuman Khandual wrote:
> FEAT_PMUv3p9 adds system register PMUACR_EL1 and similarly FEAT_PMUv3_ICNTR
> adds system registers PMICFILTR_EL0 and PMICNTR_EL0. But access into these
> system registers from EL2 and below exception levels, will trap into EL3
> unless MDCR_EL3.EnPM2 is set.
> 
> Enable access to FEAT_PMUv3p9 registers when they are implemented.
> 
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>

Applied.

Mark.

> ---
>  arch/aarch64/include/asm/cpu.h | 2 ++
>  arch/aarch64/init.c            | 3 +++
>  2 files changed, 5 insertions(+)
> 
> diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
> index e049cda..b04bf71 100644
> --- a/arch/aarch64/include/asm/cpu.h
> +++ b/arch/aarch64/include/asm/cpu.h
> @@ -56,6 +56,7 @@
>  #define MDCR_EL3_SBRBE_NOTRAP_NOPROHIBIT	(UL(3) << 32)
>  #define MDCR_EL3_ENPMSN				BIT(36)
>  #define MDCR_EL3_EBWE				BIT(43)
> +#define MDCR_EL3_EnPM2				BIT(7)
>  
>  #define SCR_EL3_RES1			BITS(5, 4)
>  #define SCR_EL3_NS			BIT(0)
> @@ -87,6 +88,7 @@
>  #define ID_AA64DFR0_EL1_PMSVER		BITS(35, 32)
>  #define ID_AA64DFR0_EL1_TRACEBUFFER	BITS(47, 44)
>  #define ID_AA64DFR0_EL1_BRBE		BITS(55, 52)
> +#define ID_AA64DFR0_EL1_PMUVER		BITS(11, 8)
>  #define ID_AA64DFR0_EL1_DEBUGVER	BITS(3, 0)
>  
>  #define ID_AA64ISAR0_EL1_TME		BITS(27, 24)
> diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c
> index 54e4cc4..fe7ed5f 100644
> --- a/arch/aarch64/init.c
> +++ b/arch/aarch64/init.c
> @@ -152,6 +152,9 @@ static void cpu_init_el3(void)
>  	if (mrs_field(ID_AA64DFR0_EL1, DEBUGVER) >= 11)
>  		mdcr |= MDCR_EL3_EBWE;
>  
> +	if (mrs_field(ID_AA64DFR0_EL1, PMUVER) >= 0b1001)
> +		mdcr |= MDCR_EL3_EnPM2;
> +
>  	msr(MDCR_EL3, mdcr);
>  
>  	if (mrs_field(ID_AA64PFR0_EL1, SVE)) {
> -- 
> 2.25.1
>