* [PATCH 0/8] dmaengine: ti: Add support for BCDMA v2 and PKTDMA v2
@ 2025-04-28 7:20 Sai Sree Kartheek Adivi
2025-04-28 7:20 ` [PATCH 1/8] dt-bindings: dma: ti: Add document for K3 BCDMA V2 Sai Sree Kartheek Adivi
` (7 more replies)
0 siblings, 8 replies; 17+ messages in thread
From: Sai Sree Kartheek Adivi @ 2025-04-28 7:20 UTC (permalink / raw)
To: peter.ujfalusi, vkoul, robh, krzk+dt, conor+dt, nm, ssantosh,
s-adivi, dmaengine, devicetree, linux-kernel, linux-arm-kernel,
praneeth, vigneshr, u-kumar1, a-chavda
This series adds support for the BCDMA_V2 and PKTDMA_V2 which is
introduced in AM62L.
The key differences between the existing DMA and DMA V2 are:
- Absence of TISCI: Instead of configuring via TISCI calls, direct
register writes are required.
- Autopair: There is no longer a need for PSIL pair and instead AUTOPAIR
bit needs to set in the RT_CTL register.
- Static channel mapping: Each channel is mapped to a single peripheral.
- Direct IRQs: There is no INT-A and interrupt lines from DMA are
directly connected to GIC.
- Remote side configuration handled by DMA. So no need to write to PEER
registers to START / STOP / PAUSE / TEARDOWN.
Sai Sree Kartheek Adivi (8):
dt-bindings: dma: ti: Add document for K3 BCDMA V2
dt-bindings: dma: ti: Add document for K3 PKTDMA V2
drivers: dma: ti: Refactor TI K3 UDMA driver
dmaengine: ti: k3-psil-am62l: Add AM62Lx PSIL and PDMA data
drivers: soc: ti: k3-ringacc: handle absence of tisci
dmaengine: ti: New driver for K3 BCDMA_V2
dmaengine: ti: k3-udma-v2: Add support for PKTDMA V2
dmaengine: ti: k3-udma-v2: Update glue layer to support PKTDMA V2
.../bindings/dma/ti/k3-bcdma-v2.yaml | 97 +
.../bindings/dma/ti/k3-pktdma-v2.yaml | 73 +
drivers/dma/ti/Kconfig | 14 +-
drivers/dma/ti/Makefile | 4 +-
drivers/dma/ti/k3-psil-am62l.c | 132 +
drivers/dma/ti/k3-psil-priv.h | 1 +
drivers/dma/ti/k3-psil.c | 1 +
drivers/dma/ti/k3-udma-common.c | 2974 +++++++++++++
drivers/dma/ti/k3-udma-glue.c | 91 +-
drivers/dma/ti/k3-udma-private.c | 48 +-
drivers/dma/ti/k3-udma-v2.c | 1513 +++++++
drivers/dma/ti/k3-udma.c | 3751 ++---------------
drivers/dma/ti/k3-udma.h | 571 ++-
drivers/soc/ti/k3-ringacc.c | 162 +-
include/linux/soc/ti/k3-ringacc.h | 7 +
15 files changed, 5873 insertions(+), 3566 deletions(-)
create mode 100644 Documentation/devicetree/bindings/dma/ti/k3-bcdma-v2.yaml
create mode 100644 Documentation/devicetree/bindings/dma/ti/k3-pktdma-v2.yaml
create mode 100644 drivers/dma/ti/k3-psil-am62l.c
create mode 100644 drivers/dma/ti/k3-udma-common.c
create mode 100644 drivers/dma/ti/k3-udma-v2.c
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 1/8] dt-bindings: dma: ti: Add document for K3 BCDMA V2
2025-04-28 7:20 [PATCH 0/8] dmaengine: ti: Add support for BCDMA v2 and PKTDMA v2 Sai Sree Kartheek Adivi
@ 2025-04-28 7:20 ` Sai Sree Kartheek Adivi
2025-04-30 10:26 ` Krzysztof Kozlowski
2025-04-28 7:20 ` [PATCH 2/8] dt-bindings: dma: ti: Add document for K3 PKTDMA V2 Sai Sree Kartheek Adivi
` (6 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: Sai Sree Kartheek Adivi @ 2025-04-28 7:20 UTC (permalink / raw)
To: peter.ujfalusi, vkoul, robh, krzk+dt, conor+dt, nm, ssantosh,
s-adivi, dmaengine, devicetree, linux-kernel, linux-arm-kernel,
praneeth, vigneshr, u-kumar1, a-chavda
New binding document for
Texas Instruments K3 Block Copy DMA (BCDMA) V2.
BCDMA V2 is introduced as part of AM62L.
Signed-off-by: Sai Sree Kartheek Adivi <s-adivi@ti.com>
---
.../bindings/dma/ti/k3-bcdma-v2.yaml | 97 +++++++++++++++++++
1 file changed, 97 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/ti/k3-bcdma-v2.yaml
diff --git a/Documentation/devicetree/bindings/dma/ti/k3-bcdma-v2.yaml b/Documentation/devicetree/bindings/dma/ti/k3-bcdma-v2.yaml
new file mode 100644
index 0000000000000..af4aa3839fd66
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/ti/k3-bcdma-v2.yaml
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2024-2025 Texas Instruments Incorporated
+# Author: Sai Sree Kartheek Adivi <s-adivi@ti.com>
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/ti/k3-bcdma-v2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments K3 DMSS BCDMA V2
+
+maintainers:
+ - Sai Sree Kartheek Adivi <s-adivi@ti.com>
+
+description: |
+ The BCDMA V2 is intended to perform similar functions as the TR
+ mode channels of K3 UDMA-P.
+ BCDMA V2 includes block copy channels and Split channels.
+
+ Block copy channels mainly used for memory to memory transfers, but with
+ optional triggers a block copy channel can service peripherals by accessing
+ directly to memory mapped registers or area.
+
+ Split channels can be used to service PSI-L based peripherals.
+ The peripherals can be PSI-L native or legacy, non PSI-L native peripherals
+ with PDMAs. PDMA is tasked to act as a bridge between the PSI-L fabric and the
+ legacy peripheral.
+
+allOf:
+ - $ref: /schemas/dma/dma-controller.yaml#
+
+properties:
+ compatible:
+ const: ti,dmss-bcdma-v2
+
+ reg:
+ items:
+ - description: BCDMA Control /Status Registers region
+ - description: Block Copy Channel Realtime Registers region
+ - description: Channel Realtime Registers region
+ - description: Ring Realtime Registers region
+
+ reg-names:
+ items:
+ - const: gcfg
+ - const: bchanrt
+ - const: chanrt
+ - const: ringrt
+
+ "#dma-cells":
+ const: 4
+ description: |
+ cell 1: Trigger type for the channel
+ 0 - disable / no trigger
+ 1 - internal channel event
+ 2 - external signal
+ 3 - timer manager event
+
+ cell 2: parameter for the trigger:
+ if cell 1 is 0 (disable / no trigger):
+ Unused, ignored
+ if cell 1 is 1 (internal channel event):
+ channel number whose TR event should trigger the current channel.
+ if cell 1 is 2 or 3 (external signal or timer manager event):
+ index of global interfaces that come into the DMA.
+
+ Please refer to the device documentation for global interface indexes.
+
+ cell 3: Channel number for the peripheral
+
+ Please refer to the device documentation for the channel map.
+
+ cell 4: ASEL value for the channel
+
+required:
+ - compatible
+ - "#dma-cells"
+ - reg
+ - reg-names
+
+unevaluatedProperties: false
+
+examples:
+ - |+
+ cbass_main {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ main_bcdma: dma-controller@485c4000 {
+ compatible = "ti,dmss-bcdma-v2";
+ reg = <0x00 0x485c4000 0x00 0x4000>,
+ <0x00 0x48880000 0x00 0x10000>,
+ <0x00 0x48800000 0x00 0x80000>,
+ <0x00 0x47000000 0x00 0x200000>;
+ reg-names = "gcfg", "bchanrt", "chanrt", "ringrt";
+ #dma-cells = <4>;
+ };
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 2/8] dt-bindings: dma: ti: Add document for K3 PKTDMA V2
2025-04-28 7:20 [PATCH 0/8] dmaengine: ti: Add support for BCDMA v2 and PKTDMA v2 Sai Sree Kartheek Adivi
2025-04-28 7:20 ` [PATCH 1/8] dt-bindings: dma: ti: Add document for K3 BCDMA V2 Sai Sree Kartheek Adivi
@ 2025-04-28 7:20 ` Sai Sree Kartheek Adivi
2025-04-30 10:26 ` Krzysztof Kozlowski
2025-04-28 7:20 ` [PATCH 4/8] dmaengine: ti: k3-psil-am62l: Add AM62Lx PSIL and PDMA data Sai Sree Kartheek Adivi
` (5 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: Sai Sree Kartheek Adivi @ 2025-04-28 7:20 UTC (permalink / raw)
To: peter.ujfalusi, vkoul, robh, krzk+dt, conor+dt, nm, ssantosh,
s-adivi, dmaengine, devicetree, linux-kernel, linux-arm-kernel,
praneeth, vigneshr, u-kumar1, a-chavda
New binding document for
Texas Instruments K3 Packet DMA (PKTDMA) V2.
PKTDMA V2 is introduced as part of AM62L.
Signed-off-by: Sai Sree Kartheek Adivi <s-adivi@ti.com>
---
.../bindings/dma/ti/k3-pktdma-v2.yaml | 73 +++++++++++++++++++
1 file changed, 73 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/ti/k3-pktdma-v2.yaml
diff --git a/Documentation/devicetree/bindings/dma/ti/k3-pktdma-v2.yaml b/Documentation/devicetree/bindings/dma/ti/k3-pktdma-v2.yaml
new file mode 100644
index 0000000000000..a6aae96af44df
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/ti/k3-pktdma-v2.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2024-2025 Texas Instruments Incorporated
+# Author: Sai Sree Kartheek Adivi <s-adivi@ti.com>
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/ti/k3-pktdma-v2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments K3 DMSS PKTDMA V2
+
+maintainers:
+ - Sai Sree Kartheek Adivi <s-adivi@ti.com>
+
+description: |
+ The PKTDMA V2 is intended to perform similar functions as the packet
+ mode channels of K3 UDMA-P.
+ PKTDMA V2 only includes Split channels to service PSI-L based peripherals.
+
+ The peripherals can be PSI-L native or legacy, non PSI-L native peripherals
+ with PDMAs. PDMA is tasked to act as a bridge between the PSI-L fabric and the
+ legacy peripheral.
+
+allOf:
+ - $ref: /schemas/dma/dma-controller.yaml#
+
+properties:
+ compatible:
+ const: ti,dmss-pktdma-v2
+
+ "#dma-cells":
+ const: 2
+ description: |
+ cell 1: Channel number for the peripheral
+
+ Please refer to the device documentation for the channel map.
+
+ cell 2: ASEL value for the channel
+
+ reg:
+ items:
+ - description: Packet DMA Control /Status Registers region
+ - description: Channel Realtime Registers region
+ - description: Ring Realtime Registers region
+
+ reg-names:
+ items:
+ - const: gcfg
+ - const: chanrt
+ - const: ringrt
+
+required:
+ - compatible
+ - "#dma-cells"
+ - reg
+ - reg-names
+
+unevaluatedProperties: false
+
+examples:
+ - |+
+ cbass_main {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ main_pktdma: dma-controller@485c0000 {
+ compatible = "ti,dmss-pktdma-v2";
+ reg = <0x00 0x485c0000 0x00 0x4000>,
+ <0x00 0x48900000 0x00 0x80000>,
+ <0x00 0x47200000 0x00 0x100000>;
+ reg-names = "gcfg", "chanrt", "ringrt";
+ #dma-cells = <2>;
+ };
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 4/8] dmaengine: ti: k3-psil-am62l: Add AM62Lx PSIL and PDMA data
2025-04-28 7:20 [PATCH 0/8] dmaengine: ti: Add support for BCDMA v2 and PKTDMA v2 Sai Sree Kartheek Adivi
2025-04-28 7:20 ` [PATCH 1/8] dt-bindings: dma: ti: Add document for K3 BCDMA V2 Sai Sree Kartheek Adivi
2025-04-28 7:20 ` [PATCH 2/8] dt-bindings: dma: ti: Add document for K3 PKTDMA V2 Sai Sree Kartheek Adivi
@ 2025-04-28 7:20 ` Sai Sree Kartheek Adivi
2025-04-28 7:20 ` [PATCH 5/8] drivers: soc: ti: k3-ringacc: handle absence of tisci Sai Sree Kartheek Adivi
` (4 subsequent siblings)
7 siblings, 0 replies; 17+ messages in thread
From: Sai Sree Kartheek Adivi @ 2025-04-28 7:20 UTC (permalink / raw)
To: peter.ujfalusi, vkoul, robh, krzk+dt, conor+dt, nm, ssantosh,
s-adivi, dmaengine, devicetree, linux-kernel, linux-arm-kernel,
praneeth, vigneshr, u-kumar1, a-chavda
Add PSIL and PDMA data for AM62Lx SoC.
Signed-off-by: Sai Sree Kartheek Adivi <s-adivi@ti.com>
---
drivers/dma/ti/Makefile | 1 +
drivers/dma/ti/k3-psil-am62l.c | 132 +++++++++++++++++++++++++++++++++
drivers/dma/ti/k3-psil-priv.h | 1 +
drivers/dma/ti/k3-psil.c | 1 +
4 files changed, 135 insertions(+)
create mode 100644 drivers/dma/ti/k3-psil-am62l.c
diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile
index 257e8141d7fe0..b03235a78d6cc 100644
--- a/drivers/dma/ti/Makefile
+++ b/drivers/dma/ti/Makefile
@@ -12,6 +12,7 @@ k3-psil-lib-objs := k3-psil.o \
k3-psil-j721s2.o \
k3-psil-am62.o \
k3-psil-am62a.o \
+ k3-psil-am62l.o \
k3-psil-j784s4.o \
k3-psil-am62p.o
obj-$(CONFIG_TI_K3_PSIL) += k3-psil-lib.o
diff --git a/drivers/dma/ti/k3-psil-am62l.c b/drivers/dma/ti/k3-psil-am62l.c
new file mode 100644
index 0000000000000..45f5aac32f6a0
--- /dev/null
+++ b/drivers/dma/ti/k3-psil-am62l.c
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com
+ */
+
+#include <linux/kernel.h>
+
+#include "k3-psil-priv.h"
+
+#define PSIL_PDMA_XY_TR(x, ch) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ .mapped_channel_id = ch, \
+ .default_flow_id = -1, \
+ }, \
+ }
+
+#define PSIL_PDMA_XY_PKT(x, ch) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ .mapped_channel_id = ch, \
+ .pkt_mode = 1, \
+ .default_flow_id = -1 \
+ }, \
+ }
+
+#define PSIL_ETHERNET(x, ch, flow_base, flow_cnt) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_NATIVE, \
+ .pkt_mode = 1, \
+ .needs_epib = 1, \
+ .psd_size = 16, \
+ .mapped_channel_id = ch, \
+ .flow_start = flow_base, \
+ .flow_num = flow_cnt, \
+ .default_flow_id = flow_base, \
+ }, \
+ }
+
+#define PSIL_PDMA_MCASP(x, ch) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ .pdma_acc32 = 1, \
+ .pdma_burst = 1, \
+ .mapped_channel_id = ch, \
+ }, \
+ }
+
+/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
+static struct psil_ep am62l_src_ep_map[] = {
+ /* PDMA_MAIN1 - UART0-6 */
+ PSIL_PDMA_XY_PKT(0x4400, 0),
+ PSIL_PDMA_XY_PKT(0x4401, 2),
+ PSIL_PDMA_XY_PKT(0x4402, 4),
+ PSIL_PDMA_XY_PKT(0x4403, 6),
+ PSIL_PDMA_XY_PKT(0x4404, 8),
+ PSIL_PDMA_XY_PKT(0x4405, 10),
+ PSIL_PDMA_XY_PKT(0x4406, 12),
+ /* PDMA_MAIN0 - SPI0 - CH0-3 */
+ PSIL_PDMA_XY_TR(0x4300, 16),
+ /* PDMA_MAIN0 - SPI1 - CH0-3 */
+ PSIL_PDMA_XY_TR(0x4301, 24),
+ /* PDMA_MAIN0 - SPI2 - CH0-3 */
+ PSIL_PDMA_XY_TR(0x4302, 32),
+ /* PDMA_MAIN0 - SPI3 - CH0-3 */
+ PSIL_PDMA_XY_TR(0x4303, 40),
+ /* PDMA_MAIN2 - MCASP0-2 */
+ PSIL_PDMA_MCASP(0x4500, 48),
+ PSIL_PDMA_MCASP(0x4501, 50),
+ PSIL_PDMA_MCASP(0x4502, 52),
+ /* PDMA_MAIN0 - AES */
+ PSIL_PDMA_XY_TR(0x4700, 65),
+ /* PDMA_MAIN0 - ADC */
+ PSIL_PDMA_XY_TR(0x4503, 80),
+ PSIL_PDMA_XY_TR(0x4504, 81),
+ PSIL_ETHERNET(0x4600, 96, 96, 16),
+};
+
+/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
+static struct psil_ep am62l_dst_ep_map[] = {
+ /* PDMA_MAIN1 - UART0-6 */
+ PSIL_PDMA_XY_PKT(0xC400, 1),
+ PSIL_PDMA_XY_PKT(0xC401, 3),
+ PSIL_PDMA_XY_PKT(0xC402, 5),
+ PSIL_PDMA_XY_PKT(0xC403, 7),
+ PSIL_PDMA_XY_PKT(0xC404, 9),
+ PSIL_PDMA_XY_PKT(0xC405, 11),
+ PSIL_PDMA_XY_PKT(0xC406, 13),
+ /* PDMA_MAIN0 - SPI0 - CH0-3 */
+ PSIL_PDMA_XY_TR(0xC300, 17),
+ /* PDMA_MAIN0 - SPI1 - CH0-3 */
+ PSIL_PDMA_XY_TR(0xC301, 25),
+ /* PDMA_MAIN0 - SPI2 - CH0-3 */
+ PSIL_PDMA_XY_TR(0xC302, 33),
+ /* PDMA_MAIN0 - SPI3 - CH0-3 */
+ PSIL_PDMA_XY_TR(0xC303, 41),
+ /* PDMA_MAIN2 - MCASP0-2 */
+ PSIL_PDMA_MCASP(0xC500, 49),
+ PSIL_PDMA_MCASP(0xC501, 51),
+ PSIL_PDMA_MCASP(0xC502, 53),
+ /* PDMA_MAIN0 - SHA */
+ PSIL_PDMA_XY_TR(0xC700, 64),
+ /* PDMA_MAIN0 - AES */
+ PSIL_PDMA_XY_TR(0xC701, 66),
+ /* PDMA_MAIN0 - CRC32 - CH0-1 */
+ PSIL_PDMA_XY_TR(0xC702, 67),
+ /* CPSW3G */
+ PSIL_ETHERNET(0xc600, 64, 64, 2),
+ PSIL_ETHERNET(0xc601, 66, 66, 2),
+ PSIL_ETHERNET(0xc602, 68, 68, 2),
+ PSIL_ETHERNET(0xc603, 70, 70, 2),
+ PSIL_ETHERNET(0xc604, 72, 72, 2),
+ PSIL_ETHERNET(0xc605, 74, 74, 2),
+ PSIL_ETHERNET(0xc606, 76, 76, 2),
+ PSIL_ETHERNET(0xc607, 78, 78, 2),
+};
+
+struct psil_ep_map am62l_ep_map = {
+ .name = "am62l",
+ .src = am62l_src_ep_map,
+ .src_count = ARRAY_SIZE(am62l_src_ep_map),
+ .dst = am62l_dst_ep_map,
+ .dst_count = ARRAY_SIZE(am62l_dst_ep_map),
+};
diff --git a/drivers/dma/ti/k3-psil-priv.h b/drivers/dma/ti/k3-psil-priv.h
index a577be97e3447..b2eb6d3b63e1b 100644
--- a/drivers/dma/ti/k3-psil-priv.h
+++ b/drivers/dma/ti/k3-psil-priv.h
@@ -44,6 +44,7 @@ extern struct psil_ep_map am64_ep_map;
extern struct psil_ep_map j721s2_ep_map;
extern struct psil_ep_map am62_ep_map;
extern struct psil_ep_map am62a_ep_map;
+extern struct psil_ep_map am62l_ep_map;
extern struct psil_ep_map j784s4_ep_map;
extern struct psil_ep_map am62p_ep_map;
diff --git a/drivers/dma/ti/k3-psil.c b/drivers/dma/ti/k3-psil.c
index c4b6f0df46861..27c1bf347b248 100644
--- a/drivers/dma/ti/k3-psil.c
+++ b/drivers/dma/ti/k3-psil.c
@@ -25,6 +25,7 @@ static const struct soc_device_attribute k3_soc_devices[] = {
{ .family = "J721S2", .data = &j721s2_ep_map },
{ .family = "AM62X", .data = &am62_ep_map },
{ .family = "AM62AX", .data = &am62a_ep_map },
+ { .family = "AM62LX", .data = &am62l_ep_map },
{ .family = "J784S4", .data = &j784s4_ep_map },
{ .family = "AM62PX", .data = &am62p_ep_map },
{ .family = "J722S", .data = &am62p_ep_map },
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 5/8] drivers: soc: ti: k3-ringacc: handle absence of tisci
2025-04-28 7:20 [PATCH 0/8] dmaengine: ti: Add support for BCDMA v2 and PKTDMA v2 Sai Sree Kartheek Adivi
` (2 preceding siblings ...)
2025-04-28 7:20 ` [PATCH 4/8] dmaengine: ti: k3-psil-am62l: Add AM62Lx PSIL and PDMA data Sai Sree Kartheek Adivi
@ 2025-04-28 7:20 ` Sai Sree Kartheek Adivi
2025-04-28 18:45 ` kernel test robot
2025-05-09 16:29 ` Péter Ujfalusi
2025-04-28 7:20 ` [PATCH 6/8] dmaengine: ti: New driver for K3 BCDMA_V2 Sai Sree Kartheek Adivi
` (3 subsequent siblings)
7 siblings, 2 replies; 17+ messages in thread
From: Sai Sree Kartheek Adivi @ 2025-04-28 7:20 UTC (permalink / raw)
To: peter.ujfalusi, vkoul, robh, krzk+dt, conor+dt, nm, ssantosh,
s-adivi, dmaengine, devicetree, linux-kernel, linux-arm-kernel,
praneeth, vigneshr, u-kumar1, a-chavda
Handle absence of tisci with direct register writes. This will support
platforms that do not have tisci firmware like AM62L.
Signed-off-by: Sai Sree Kartheek Adivi <s-adivi@ti.com>
---
drivers/soc/ti/k3-ringacc.c | 162 +++++++++++++++++++++++++-----
include/linux/soc/ti/k3-ringacc.h | 4 +
2 files changed, 142 insertions(+), 24 deletions(-)
diff --git a/drivers/soc/ti/k3-ringacc.c b/drivers/soc/ti/k3-ringacc.c
index 82a15cad1c6c4..49e0483676a14 100644
--- a/drivers/soc/ti/k3-ringacc.c
+++ b/drivers/soc/ti/k3-ringacc.c
@@ -45,6 +45,38 @@ struct k3_ring_rt_regs {
u32 hwindx;
};
+#define K3_RINGACC_RT_CFG_REGS_OFS 0x40
+#define K3_DMARING_CFG_ADDR_HI_MASK GENMASK(3, 0)
+#define K3_DMARING_CFG_ASEL_SHIFT 16
+#define K3_DMARING_CFG_SIZE_MASK GENMASK(15, 0)
+
+/**
+ * struct k3_ring_cfg_regs - The RA Configuration Registers region
+ *
+ * @ba_lo: Ring Base Address Low Register
+ * @ba_hi: Ring Base Address High Register
+ * @size: Ring Size Register
+ */
+struct k3_ring_cfg_regs {
+ u32 ba_lo;
+ u32 ba_hi;
+ u32 size;
+};
+
+#define K3_RINGACC_RT_INT_REGS_OFS 0x140
+#define K3_RINGACC_RT_INT_ENABLE_SET_COMPLETE BIT(0)
+#define K3_RINGACC_RT_INT_ENABLE_SET_TR BIT(2)
+
+struct k3_ring_intr_regs {
+ u32 enable_set;
+ u32 resv_4;
+ u32 clr;
+ u32 resv_16;
+ u32 status_set;
+ u32 resv_8;
+ u32 status;
+};
+
#define K3_RINGACC_RT_REGS_STEP 0x1000
#define K3_DMARING_RT_REGS_STEP 0x2000
#define K3_DMARING_RT_REGS_REVERSE_OFS 0x1000
@@ -157,6 +189,8 @@ struct k3_ring_state {
*/
struct k3_ring {
struct k3_ring_rt_regs __iomem *rt;
+ struct k3_ring_cfg_regs __iomem *cfg;
+ struct k3_ring_intr_regs __iomem *intr;
struct k3_ring_fifo_regs __iomem *fifos;
struct k3_ringacc_proxy_target_regs __iomem *proxy;
dma_addr_t ring_mem_dma;
@@ -465,16 +499,30 @@ static void k3_ringacc_ring_reset_sci(struct k3_ring *ring)
struct ti_sci_msg_rm_ring_cfg ring_cfg = { 0 };
struct k3_ringacc *ringacc = ring->parent;
int ret;
+ u32 reg;
- ring_cfg.nav_id = ringacc->tisci_dev_id;
- ring_cfg.index = ring->ring_id;
- ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID;
- ring_cfg.count = ring->size;
+ if (!ringacc->tisci) {
+ if (ring->cfg == NULL)
+ return;
+ reg = readl(&ring->cfg->size);
+ reg &= ~K3_DMARING_CFG_SIZE_MASK;
- ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
- if (ret)
- dev_err(ringacc->dev, "TISCI reset ring fail (%d) ring_idx %d\n",
- ret, ring->ring_id);
+ writel(reg, &ring->cfg->size);
+ wmb();
+ reg |= ring->size;
+
+ writel(reg, &ring->cfg->size);
+ } else {
+ ring_cfg.nav_id = ringacc->tisci_dev_id;
+ ring_cfg.index = ring->ring_id;
+ ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID;
+ ring_cfg.count = ring->size;
+
+ ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
+ if (ret)
+ dev_err(ringacc->dev, "TISCI reset ring fail (%d) ring_idx %d\n",
+ ret, ring->ring_id);
+ }
}
void k3_ringacc_ring_reset(struct k3_ring *ring)
@@ -494,16 +542,30 @@ static void k3_ringacc_ring_reconfig_qmode_sci(struct k3_ring *ring,
struct ti_sci_msg_rm_ring_cfg ring_cfg = { 0 };
struct k3_ringacc *ringacc = ring->parent;
int ret;
+ u32 reg;
ring_cfg.nav_id = ringacc->tisci_dev_id;
ring_cfg.index = ring->ring_id;
ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_RING_MODE_VALID;
ring_cfg.mode = mode;
- ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
- if (ret)
- dev_err(ringacc->dev, "TISCI reconf qmode fail (%d) ring_idx %d\n",
- ret, ring->ring_id);
+ if (!ringacc->tisci) {
+ writel(ring_cfg.addr_lo, &ring->cfg->ba_lo);
+ writel((ring_cfg.addr_hi & K3_DMARING_CFG_ADDR_HI_MASK) +
+ (ring_cfg.asel << K3_DMARING_CFG_ASEL_SHIFT),
+ &ring->cfg->ba_hi);
+
+ reg = readl(&ring->cfg->size);
+ reg &= ~K3_DMARING_CFG_SIZE_MASK;
+ reg |= ring_cfg.count & K3_DMARING_CFG_SIZE_MASK;
+
+ writel(reg, &ring->cfg->size);
+ } else {
+ ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
+ if (ret)
+ dev_err(ringacc->dev, "TISCI reconf qmode fail (%d) ring_idx %d\n",
+ ret, ring->ring_id);
+ }
}
void k3_ringacc_ring_reset_dma(struct k3_ring *ring, u32 occ)
@@ -570,15 +632,29 @@ static void k3_ringacc_ring_free_sci(struct k3_ring *ring)
struct ti_sci_msg_rm_ring_cfg ring_cfg = { 0 };
struct k3_ringacc *ringacc = ring->parent;
int ret;
+ u32 reg;
ring_cfg.nav_id = ringacc->tisci_dev_id;
ring_cfg.index = ring->ring_id;
ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER;
- ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
- if (ret)
- dev_err(ringacc->dev, "TISCI ring free fail (%d) ring_idx %d\n",
- ret, ring->ring_id);
+ if (!ringacc->tisci) {
+ writel(ring_cfg.addr_lo, &ring->cfg->ba_lo);
+ writel((ring_cfg.addr_hi & K3_DMARING_CFG_ADDR_HI_MASK) +
+ (ring_cfg.asel << K3_DMARING_CFG_ASEL_SHIFT),
+ &ring->cfg->ba_hi);
+
+ reg = readl(&ring->cfg->size);
+ reg &= ~K3_DMARING_CFG_SIZE_MASK;
+ reg |= ring_cfg.count & K3_DMARING_CFG_SIZE_MASK;
+
+ writel(reg, &ring->cfg->size);
+ } else {
+ ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
+ if (ret)
+ dev_err(ringacc->dev, "TISCI ring free fail (%d) ring_idx %d\n",
+ ret, ring->ring_id);
+ }
}
int k3_ringacc_ring_free(struct k3_ring *ring)
@@ -669,15 +745,31 @@ int k3_ringacc_get_ring_irq_num(struct k3_ring *ring)
}
EXPORT_SYMBOL_GPL(k3_ringacc_get_ring_irq_num);
+u32 k3_ringacc_ring_get_irq_status(struct k3_ring *ring)
+{
+ struct k3_ringacc *ringacc = ring->parent;
+ struct k3_ring *ring2 = &ringacc->rings[ring->ring_id];
+
+ return readl(&ring2->intr->status);
+}
+EXPORT_SYMBOL_GPL(k3_ringacc_ring_get_irq_status);
+
+void k3_ringacc_ring_clear_irq(struct k3_ring *ring)
+{
+ struct k3_ringacc *ringacc = ring->parent;
+ struct k3_ring *ring2 = &ringacc->rings[ring->ring_id];
+
+ writel(0xFF, &ring2->intr->status);
+}
+EXPORT_SYMBOL_GPL(k3_ringacc_ring_clear_irq);
+
static int k3_ringacc_ring_cfg_sci(struct k3_ring *ring)
{
struct ti_sci_msg_rm_ring_cfg ring_cfg = { 0 };
struct k3_ringacc *ringacc = ring->parent;
+ u32 reg;
int ret;
- if (!ringacc->tisci)
- return -EINVAL;
-
ring_cfg.nav_id = ringacc->tisci_dev_id;
ring_cfg.index = ring->ring_id;
ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER;
@@ -688,11 +780,26 @@ static int k3_ringacc_ring_cfg_sci(struct k3_ring *ring)
ring_cfg.size = ring->elm_size;
ring_cfg.asel = ring->asel;
+ if (!ringacc->tisci) {
+ writel(ring_cfg.addr_lo, &ring->cfg->ba_lo);
+ writel((ring_cfg.addr_hi & K3_DMARING_CFG_ADDR_HI_MASK) +
+ (ring_cfg.asel << K3_DMARING_CFG_ASEL_SHIFT),
+ &ring->cfg->ba_hi);
+
+ reg = readl(&ring->cfg->size);
+ reg &= ~K3_DMARING_CFG_SIZE_MASK;
+ reg |= ring_cfg.count & K3_DMARING_CFG_SIZE_MASK;
+
+ writel(reg, &ring->cfg->size);
+ writel(K3_RINGACC_RT_INT_ENABLE_SET_COMPLETE | K3_RINGACC_RT_INT_ENABLE_SET_TR,
+ &ring->intr->enable_set);
+ return 0;
+ }
+
ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
if (ret)
dev_err(ringacc->dev, "TISCI config ring fail (%d) ring_idx %d\n",
- ret, ring->ring_id);
-
+ ret, ring->ring_id);
return ret;
}
@@ -1480,9 +1587,12 @@ struct k3_ringacc *k3_ringacc_dmarings_init(struct platform_device *pdev,
mutex_init(&ringacc->req_lock);
- base_rt = devm_platform_ioremap_resource_byname(pdev, "ringrt");
- if (IS_ERR(base_rt))
- return ERR_CAST(base_rt);
+ base_rt = data->base_rt;
+ if (!base_rt) {
+ base_rt = devm_platform_ioremap_resource_byname(pdev, "ringrt");
+ if (IS_ERR(base_rt))
+ return ERR_CAST(base_rt);
+ }
ringacc->rings = devm_kzalloc(dev,
sizeof(*ringacc->rings) *
@@ -1498,6 +1608,10 @@ struct k3_ringacc *k3_ringacc_dmarings_init(struct platform_device *pdev,
struct k3_ring *ring = &ringacc->rings[i];
ring->rt = base_rt + K3_DMARING_RT_REGS_STEP * i;
+ ring->cfg = base_rt + K3_RINGACC_RT_CFG_REGS_OFS +
+ K3_DMARING_RT_REGS_STEP * i;
+ ring->intr = base_rt + K3_RINGACC_RT_INT_REGS_OFS +
+ K3_DMARING_RT_REGS_STEP * i;
ring->parent = ringacc;
ring->ring_id = i;
ring->proxy_id = K3_RINGACC_PROXY_NOT_USED;
diff --git a/include/linux/soc/ti/k3-ringacc.h b/include/linux/soc/ti/k3-ringacc.h
index 39b022b925986..fcf6fbd4a8594 100644
--- a/include/linux/soc/ti/k3-ringacc.h
+++ b/include/linux/soc/ti/k3-ringacc.h
@@ -158,6 +158,9 @@ u32 k3_ringacc_get_ring_id(struct k3_ring *ring);
*/
int k3_ringacc_get_ring_irq_num(struct k3_ring *ring);
+u32 k3_ringacc_ring_get_irq_status(struct k3_ring *ring);
+void k3_ringacc_ring_clear_irq(struct k3_ring *ring);
+
/**
* k3_ringacc_ring_cfg - ring configure
* @ring: pointer on ring
@@ -262,6 +265,7 @@ struct k3_ringacc_init_data {
const struct ti_sci_handle *tisci;
u32 tisci_dev_id;
u32 num_rings;
+ void __iomem *base_rt;
};
struct k3_ringacc *k3_ringacc_dmarings_init(struct platform_device *pdev,
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 6/8] dmaengine: ti: New driver for K3 BCDMA_V2
2025-04-28 7:20 [PATCH 0/8] dmaengine: ti: Add support for BCDMA v2 and PKTDMA v2 Sai Sree Kartheek Adivi
` (3 preceding siblings ...)
2025-04-28 7:20 ` [PATCH 5/8] drivers: soc: ti: k3-ringacc: handle absence of tisci Sai Sree Kartheek Adivi
@ 2025-04-28 7:20 ` Sai Sree Kartheek Adivi
2025-04-29 8:05 ` kernel test robot
2025-05-07 7:31 ` kernel test robot
2025-04-28 7:20 ` [PATCH 7/8] dmaengine: ti: k3-udma-v2: Add support for PKTDMA V2 Sai Sree Kartheek Adivi
` (2 subsequent siblings)
7 siblings, 2 replies; 17+ messages in thread
From: Sai Sree Kartheek Adivi @ 2025-04-28 7:20 UTC (permalink / raw)
To: peter.ujfalusi, vkoul, robh, krzk+dt, conor+dt, nm, ssantosh,
s-adivi, dmaengine, devicetree, linux-kernel, linux-arm-kernel,
praneeth, vigneshr, u-kumar1, a-chavda
Add support for BCDMA_V2.
The BCDMA_V2 is different than the existing BCDMA supported by the
k3-udma driver.
The changes in BCDMA_V2 are:
- Autopair: There is no longer a need for PSIL pair and AUTOPAIR bit
needs to set in the RT_CTL register.
- Static channel mapping: Each channel is mapped to a single peripheral.
- Direct IRQs: There is no INT-A and interrupt lines from DMA are
directly connected to GIC.
- Remote side configuration handled by DMA. So no need to write to PEER
registers to START / STOP / PAUSE / TEARDOWN.
Signed-off-by: Sai Sree Kartheek Adivi <s-adivi@ti.com>
---
drivers/dma/ti/Kconfig | 14 +-
drivers/dma/ti/Makefile | 1 +
drivers/dma/ti/k3-udma-common.c | 76 +-
drivers/dma/ti/k3-udma-v2.c | 1322 +++++++++++++++++++++++++++++
drivers/dma/ti/k3-udma.h | 118 +--
include/linux/soc/ti/k3-ringacc.h | 3 +
6 files changed, 1467 insertions(+), 67 deletions(-)
create mode 100644 drivers/dma/ti/k3-udma-v2.c
diff --git a/drivers/dma/ti/Kconfig b/drivers/dma/ti/Kconfig
index 2adc2cca10e92..bb37015074834 100644
--- a/drivers/dma/ti/Kconfig
+++ b/drivers/dma/ti/Kconfig
@@ -47,17 +47,27 @@ config TI_K3_UDMA
Enable support for the TI UDMA (Unified DMA) controller. This
DMA engine is used in AM65x and j721e.
+config TI_K3_UDMA_V2
+ tristate "Texas Instruments AM62L UDMA v2 support"
+ depends on ARCH_K3
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ select TI_K3_RINGACC
+ select TI_K3_PSIL
+ help
+ Enable support for the TI UDMA (Unified DMA) v2 controller.
+
config TI_K3_UDMA_GLUE_LAYER
tristate "Texas Instruments UDMA Glue layer for non DMAengine users"
depends on ARCH_K3
- depends on TI_K3_UDMA
+ depends on TI_K3_UDMA || TI_K3_UDMA_AM62L
help
Say y here to support the K3 NAVSS DMA glue interface
If unsure, say N.
config TI_K3_PSIL
tristate
- default TI_K3_UDMA
+ default TI_K3_UDMA || TI_K3_UDMA_AM62L
config TI_DMA_CROSSBAR
bool
diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile
index b03235a78d6cc..f4e06412ab53f 100644
--- a/drivers/dma/ti/Makefile
+++ b/drivers/dma/ti/Makefile
@@ -3,6 +3,7 @@ obj-$(CONFIG_TI_CPPI41) += cppi41.o
obj-$(CONFIG_TI_EDMA) += edma.o
obj-$(CONFIG_DMA_OMAP) += omap-dma.o
obj-$(CONFIG_TI_K3_UDMA) += k3-udma.o k3-udma-common.o
+obj-$(CONFIG_TI_K3_UDMA_V2) += k3-udma-v2.o k3-udma-common.o
obj-$(CONFIG_TI_K3_UDMA_GLUE_LAYER) += k3-udma-glue.o
k3-psil-lib-objs := k3-psil.o \
k3-psil-am654.o \
diff --git a/drivers/dma/ti/k3-udma-common.c b/drivers/dma/ti/k3-udma-common.c
index 078b018b22830..462ad17c74604 100644
--- a/drivers/dma/ti/k3-udma-common.c
+++ b/drivers/dma/ti/k3-udma-common.c
@@ -597,6 +597,8 @@ int udma_get_tchan(struct udma_chan *uc)
uc->tchan = NULL;
return ret;
}
+ if (ud->match_data->type == DMA_TYPE_BCDMA_V2)
+ uc->chan = uc->tchan;
if (ud->tflow_cnt) {
int tflow_id;
@@ -646,6 +648,8 @@ int udma_get_rchan(struct udma_chan *uc)
uc->rchan = NULL;
return ret;
}
+ if (ud->match_data->type == DMA_TYPE_BCDMA_V2)
+ uc->chan = uc->rchan;
return 0;
}
@@ -967,6 +971,7 @@ udma_prep_slave_sg_tr(struct udma_chan *uc, struct scatterlist *sgl,
size_t tr_size;
int num_tr = 0;
int tr_idx = 0;
+ u32 extra_flags = 0;
u64 asel;
/* estimate the number of TRs we will need */
@@ -990,6 +995,11 @@ udma_prep_slave_sg_tr(struct udma_chan *uc, struct scatterlist *sgl,
else
asel = (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT;
+
+ if (dir == DMA_MEM_TO_DEV && uc->ud->match_data->type == DMA_TYPE_BCDMA_V2)
+ extra_flags = CPPI5_TR_CSF_EOP;
+
+
tr_req = d->hwdesc[0].tr_req_base;
for_each_sg(sgl, sgent, sglen, i) {
dma_addr_t sg_addr = sg_dma_address(sgent);
@@ -1006,7 +1016,7 @@ udma_prep_slave_sg_tr(struct udma_chan *uc, struct scatterlist *sgl,
cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, false,
false, CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
- cppi5_tr_csf_set(&tr_req[tr_idx].flags, CPPI5_TR_CSF_SUPR_EVT);
+ cppi5_tr_csf_set(&tr_req[tr_idx].flags, CPPI5_TR_CSF_SUPR_EVT | extra_flags);
sg_addr |= asel;
tr_req[tr_idx].addr = sg_addr;
@@ -1020,7 +1030,7 @@ udma_prep_slave_sg_tr(struct udma_chan *uc, struct scatterlist *sgl,
false, false,
CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
cppi5_tr_csf_set(&tr_req[tr_idx].flags,
- CPPI5_TR_CSF_SUPR_EVT);
+ CPPI5_TR_CSF_SUPR_EVT | extra_flags);
tr_req[tr_idx].addr = sg_addr + tr0_cnt1 * tr0_cnt0;
tr_req[tr_idx].icnt0 = tr1_cnt0;
@@ -1280,7 +1290,8 @@ int udma_configure_statictr(struct udma_chan *uc, struct udma_desc *d,
d->static_tr.bstcnt = d->residue / d->sglen / div;
else
d->static_tr.bstcnt = d->residue / div;
- } else if (uc->ud->match_data->type == DMA_TYPE_BCDMA &&
+ } else if ((uc->ud->match_data->type == DMA_TYPE_BCDMA ||
+ uc->ud->match_data->type == DMA_TYPE_BCDMA_V2) &&
uc->config.dir == DMA_DEV_TO_MEM &&
uc->cyclic) {
/*
@@ -1605,7 +1616,8 @@ udma_prep_dma_cyclic_tr(struct udma_chan *uc, dma_addr_t buf_addr,
* last one, so set the flag for each period.
*/
if (uc->config.ep_type == PSIL_EP_PDMA_XY &&
- uc->ud->match_data->type == DMA_TYPE_BCDMA) {
+ (uc->ud->match_data->type == DMA_TYPE_BCDMA ||
+ uc->ud->match_data->type == DMA_TYPE_BCDMA_V2)) {
period_csf = CPPI5_TR_CSF_EOP;
}
@@ -2057,8 +2069,9 @@ void udma_free_chan_resources(struct dma_chan *chan)
/* Release PSI-L pairing */
if (uc->psil_paired) {
- navss_psil_unpair(ud, uc->config.src_thread,
- uc->config.dst_thread);
+ if (ud->match_data->type < DMA_TYPE_BCDMA_V2 && IS_ENABLED(CONFIG_TI_K3_UDMA))
+ navss_psil_unpair(ud, uc->config.src_thread,
+ uc->config.dst_thread);
uc->psil_paired = false;
}
@@ -2086,6 +2099,7 @@ int setup_resources(struct udma_dev *ud)
ret = udma_setup_resources(ud);
break;
case DMA_TYPE_BCDMA:
+ case DMA_TYPE_BCDMA_V2:
ret = bcdma_setup_resources(ud);
break;
case DMA_TYPE_PKTDMA:
@@ -2098,11 +2112,18 @@ int setup_resources(struct udma_dev *ud)
if (ret)
return ret;
- ch_count = ud->bchan_cnt + ud->tchan_cnt + ud->rchan_cnt;
- if (ud->bchan_cnt)
- ch_count -= bitmap_weight(ud->bchan_map, ud->bchan_cnt);
- ch_count -= bitmap_weight(ud->tchan_map, ud->tchan_cnt);
- ch_count -= bitmap_weight(ud->rchan_map, ud->rchan_cnt);
+ if (ud->match_data->type == DMA_TYPE_BCDMA_V2) {
+ ch_count = ud->bchan_cnt + ud->tchan_cnt;
+ if (ud->bchan_cnt)
+ ch_count -= bitmap_weight(ud->bchan_map, ud->bchan_cnt);
+ ch_count -= bitmap_weight(ud->tchan_map, ud->tchan_cnt);
+ } else {
+ ch_count = ud->bchan_cnt + ud->tchan_cnt + ud->rchan_cnt;
+ if (ud->bchan_cnt)
+ ch_count -= bitmap_weight(ud->bchan_map, ud->bchan_cnt);
+ ch_count -= bitmap_weight(ud->tchan_map, ud->tchan_cnt);
+ ch_count -= bitmap_weight(ud->rchan_map, ud->rchan_cnt);
+ }
if (!ch_count)
return -ENODEV;
@@ -2134,6 +2155,15 @@ int setup_resources(struct udma_dev *ud)
ud->rchan_cnt - bitmap_weight(ud->rchan_map,
ud->rchan_cnt));
break;
+ case DMA_TYPE_BCDMA_V2:
+ dev_info(dev,
+ "Channels: %d (bchan: %u, chan: %u)\n",
+ ch_count,
+ ud->bchan_cnt - bitmap_weight(ud->bchan_map,
+ ud->bchan_cnt),
+ ud->chan_cnt - bitmap_weight(ud->chan_map,
+ ud->chan_cnt));
+ break;
case DMA_TYPE_PKTDMA:
dev_info(dev,
"Channels: %d (tchan: %u, rchan: %u)\n",
@@ -2370,16 +2400,26 @@ int bcdma_setup_resources(struct udma_dev *ud)
ud->bchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->bchan_cnt),
sizeof(unsigned long), GFP_KERNEL);
+ bitmap_zero(ud->bchan_map, ud->bchan_cnt);
ud->bchans = devm_kcalloc(dev, ud->bchan_cnt, sizeof(*ud->bchans),
GFP_KERNEL);
ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt),
sizeof(unsigned long), GFP_KERNEL);
+ bitmap_zero(ud->tchan_map, ud->tchan_cnt);
ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans),
GFP_KERNEL);
- ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt),
- sizeof(unsigned long), GFP_KERNEL);
- ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans),
- GFP_KERNEL);
+ if (ud->match_data->type == DMA_TYPE_BCDMA_V2) {
+ ud->rchan_map = ud->tchan_map;
+ ud->rchans = ud->tchans;
+ ud->chan_map = ud->tchan_map;
+ ud->chans = ud->tchans;
+ } else {
+ ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt),
+ sizeof(unsigned long), GFP_KERNEL);
+ bitmap_zero(ud->rchan_map, ud->rchan_cnt);
+ ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans),
+ GFP_KERNEL);
+ }
/* BCDMA do not really have flows, but the driver expect it */
ud->rflow_in_use = devm_kcalloc(dev, BITS_TO_LONGS(ud->rchan_cnt),
sizeof(unsigned long),
@@ -2392,6 +2432,9 @@ int bcdma_setup_resources(struct udma_dev *ud)
!ud->rflows)
return -ENOMEM;
+ if (ud->match_data->type == DMA_TYPE_BCDMA_V2)
+ return 0;
+
/* Get resource ranges from tisci */
for (i = 0; i < RM_RANGE_LAST; i++) {
if (i == RM_RANGE_RFLOW || i == RM_RANGE_TFLOW)
@@ -2821,7 +2864,8 @@ void udma_dbg_summary_show_chan(struct seq_file *s,
switch (uc->config.dir) {
case DMA_MEM_TO_MEM:
- if (uc->ud->match_data->type == DMA_TYPE_BCDMA) {
+ if (uc->ud->match_data->type == DMA_TYPE_BCDMA ||
+ uc->ud->match_data->type == DMA_TYPE_BCDMA_V2) {
seq_printf(s, "bchan%d)\n", uc->bchan->id);
return;
}
diff --git a/drivers/dma/ti/k3-udma-v2.c b/drivers/dma/ti/k3-udma-v2.c
new file mode 100644
index 0000000000000..90b5ac5e00ead
--- /dev/null
+++ b/drivers/dma/ti/k3-udma-v2.c
@@ -0,0 +1,1322 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Derived from K3 UDMA driver (k3-udma.c)
+ * Copyright (C) 2024-2025 Texas Instruments Incorporated - http://www.ti.com
+ * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
+ * Author: Sai Sree Kartheek Adivi <s-adivi@ti.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <linux/dmapool.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/sys_soc.h>
+#include <linux/of.h>
+#include <linux/of_dma.h>
+#include <linux/of_irq.h>
+#include <linux/workqueue.h>
+#include <linux/completion.h>
+#include <linux/iopoll.h>
+#include <linux/soc/ti/k3-ringacc.h>
+#include <linux/dma/k3-event-router.h>
+#include <linux/dma/ti-cppi5.h>
+
+#include "../virt-dma.h"
+#include "k3-udma.h"
+#include "k3-psil-priv.h"
+
+#define UDMA_CHAN_RT_STATIC_TR_XY_REG 0x800
+#define UDMA_CHAN_RT_STATIC_TR_Z_REG 0x804
+#define UDMA_CHAN_RT_PERIPH_BCNT_REG 0x810
+
+static const char * const v2_mmr_names[] = {
+ [V2_MMR_GCFG] = "gcfg",
+ [V2_MMR_BCHANRT] = "bchanrt",
+ [V2_MMR_CHANRT] = "chanrt",
+};
+
+static int udma_v2_check_chan_autopair_completion(struct udma_chan *uc)
+{
+ u32 val;
+
+ val = udma_chanrt_read(uc, UDMA_CHAN_RT_CTL_REG);
+ if (val & UDMA_CHAN_RT_CTL_PAIR_TIMEOUT)
+ return -ETIMEDOUT;
+ else if (val & UDMA_CHAN_RT_CTL_PAIR_COMPLETE)
+ return 1;
+
+ /* timeout didn't occur and also pairing didn't happen yet. */
+ return 0;
+}
+
+static bool udma_v2_is_chan_paused(struct udma_chan *uc)
+{
+ u32 val, pause_mask;
+
+ if (uc->config.dir == DMA_MEM_TO_MEM) {
+ val = udma_chanrt_read(uc, UDMA_CHAN_RT_CTL_REG);
+ pause_mask = UDMA_CHAN_RT_CTL_PAUSE;
+ } else {
+ val = udma_chanrt_read(uc, UDMA_CHAN_RT_PDMA_STATE_REG);
+ pause_mask = UDMA_CHAN_RT_PDMA_STATE_PAUSE;
+ }
+
+ if (val & pause_mask)
+ return true;
+
+ return false;
+}
+
+static void udma_v2_decrement_byte_counters(struct udma_chan *uc, u32 val)
+{
+ udma_chanrt_write(uc, UDMA_CHAN_RT_BCNT_REG, val);
+ udma_chanrt_write(uc, UDMA_CHAN_RT_SBCNT_REG, val);
+ if (uc->config.ep_type != PSIL_EP_NATIVE)
+ udma_chanrt_write(uc, UDMA_CHAN_RT_PERIPH_BCNT_REG, val);
+}
+
+static void udma_v2_reset_counters(struct udma_chan *uc)
+{
+ u32 val;
+
+ val = udma_chanrt_read(uc, UDMA_CHAN_RT_BCNT_REG);
+ udma_chanrt_write(uc, UDMA_CHAN_RT_BCNT_REG, val);
+
+ val = udma_chanrt_read(uc, UDMA_CHAN_RT_SBCNT_REG);
+ udma_chanrt_write(uc, UDMA_CHAN_RT_SBCNT_REG, val);
+
+ val = udma_chanrt_read(uc, UDMA_CHAN_RT_PCNT_REG);
+ udma_chanrt_write(uc, UDMA_CHAN_RT_PCNT_REG, val);
+
+ if (!uc->bchan) {
+ val = udma_chanrt_read(uc, UDMA_CHAN_RT_PERIPH_BCNT_REG);
+ udma_chanrt_write(uc, UDMA_CHAN_RT_PERIPH_BCNT_REG, val);
+ }
+}
+
+static int udma_v2_reset_chan(struct udma_chan *uc, bool hard)
+{
+ udma_chanrt_write(uc, UDMA_CHAN_RT_CTL_REG, 0);
+
+ /* Reset all counters */
+ udma_v2_reset_counters(uc);
+
+ /* Hard reset: re-initialize the channel to reset */
+ if (hard) {
+ struct udma_chan_config ucc_backup;
+ int ret;
+
+ memcpy(&ucc_backup, &uc->config, sizeof(uc->config));
+ uc->ud->ddev.device_free_chan_resources(&uc->vc.chan);
+
+ /* restore the channel configuration */
+ memcpy(&uc->config, &ucc_backup, sizeof(uc->config));
+ ret = uc->ud->ddev.device_alloc_chan_resources(&uc->vc.chan);
+ if (ret)
+ return ret;
+
+ /*
+ * Setting forced teardown after forced reset helps recovering
+ * the rchan.
+ */
+ if (uc->config.dir == DMA_DEV_TO_MEM)
+ udma_chanrt_update_bits(uc, UDMA_CHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_TDOWN |
+ UDMA_CHAN_RT_CTL_FTDOWN,
+ UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_TDOWN |
+ UDMA_CHAN_RT_CTL_FTDOWN);
+ }
+ uc->state = UDMA_CHAN_IS_IDLE;
+
+ return 0;
+}
+
+static int udma_v2_start(struct udma_chan *uc)
+{
+ struct virt_dma_desc *vd = vchan_next_desc(&uc->vc);
+ struct udma_dev *ud = uc->ud;
+ int status, ret;
+
+ if (!vd) {
+ uc->desc = NULL;
+ return -ENOENT;
+ }
+
+ list_del(&vd->node);
+
+ uc->desc = to_udma_desc(&vd->tx);
+
+ /* Channel is already running and does not need reconfiguration */
+ if (udma_is_chan_running(uc) && !udma_chan_needs_reconfiguration(uc)) {
+ udma_start_desc(uc);
+ goto out;
+ }
+
+ /* Make sure that we clear the teardown bit, if it is set */
+ ud->udma_reset_chan(uc, false);
+
+ /* Push descriptors before we start the channel */
+ udma_start_desc(uc);
+
+ switch (uc->desc->dir) {
+ case DMA_DEV_TO_MEM:
+ /* Config remote TR */
+ if (uc->config.ep_type == PSIL_EP_PDMA_XY) {
+ u32 val = PDMA_STATIC_TR_Y(uc->desc->static_tr.elcnt) |
+ PDMA_STATIC_TR_X(uc->desc->static_tr.elsize);
+ const struct udma_match_data *match_data =
+ uc->ud->match_data;
+
+ if (uc->config.enable_acc32)
+ val |= PDMA_STATIC_TR_XY_ACC32;
+ if (uc->config.enable_burst)
+ val |= PDMA_STATIC_TR_XY_BURST;
+
+ udma_chanrt_write(uc,
+ UDMA_CHAN_RT_STATIC_TR_XY_REG,
+ val);
+
+ udma_chanrt_write(uc,
+ UDMA_CHAN_RT_STATIC_TR_Z_REG,
+ PDMA_STATIC_TR_Z(uc->desc->static_tr.bstcnt,
+ match_data->statictr_z_mask));
+
+ /* save the current staticTR configuration */
+ memcpy(&uc->static_tr, &uc->desc->static_tr,
+ sizeof(uc->static_tr));
+ }
+
+ udma_chanrt_write(uc, UDMA_CHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_AUTOPAIR);
+
+ /* Poll for autopair completion */
+ ret = read_poll_timeout_atomic(udma_v2_check_chan_autopair_completion,
+ status, status != 0, 100, 500, false, uc);
+
+ if (status <= 0)
+ return -ETIMEDOUT;
+
+ break;
+ case DMA_MEM_TO_DEV:
+ /* Config remote TR */
+ if (uc->config.ep_type == PSIL_EP_PDMA_XY) {
+ u32 val = PDMA_STATIC_TR_Y(uc->desc->static_tr.elcnt) |
+ PDMA_STATIC_TR_X(uc->desc->static_tr.elsize);
+
+ if (uc->config.enable_acc32)
+ val |= PDMA_STATIC_TR_XY_ACC32;
+ if (uc->config.enable_burst)
+ val |= PDMA_STATIC_TR_XY_BURST;
+
+ udma_chanrt_write(uc,
+ UDMA_CHAN_RT_STATIC_TR_XY_REG,
+ val);
+
+ /* save the current staticTR configuration */
+ memcpy(&uc->static_tr, &uc->desc->static_tr,
+ sizeof(uc->static_tr));
+ }
+
+ udma_chanrt_write(uc, UDMA_CHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_AUTOPAIR);
+
+ /* Poll for autopair completion */
+ ret = read_poll_timeout_atomic(udma_v2_check_chan_autopair_completion,
+ status, status != 0, 100, 500, false, uc);
+
+ if (status <= 0)
+ return -ETIMEDOUT;
+
+ break;
+ case DMA_MEM_TO_MEM:
+ udma_bchanrt_write(uc, UDMA_CHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_EN);
+ udma_bchanrt_write(uc, UDMA_CHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_EN);
+
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ uc->state = UDMA_CHAN_IS_ACTIVE;
+out:
+
+ return 0;
+}
+
+static int udma_v2_stop(struct udma_chan *uc)
+{
+ uc->state = UDMA_CHAN_IS_TERMINATING;
+ reinit_completion(&uc->teardown_completed);
+
+ if (uc->config.dir == DMA_DEV_TO_MEM) {
+ if (!uc->cyclic && !uc->desc)
+ udma_push_to_ring(uc, -1);
+ }
+
+ udma_chanrt_write(uc, UDMA_CHAN_RT_PEER_REG(8), UDMA_CHAN_RT_PEER_REG8_FLUSH);
+ udma_chanrt_update_bits(uc, UDMA_CHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_TDOWN,
+ UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_TDOWN);
+
+ return 0;
+}
+
+static bool udma_v2_is_desc_really_done(struct udma_chan *uc, struct udma_desc *d)
+{
+ u32 peer_bcnt, bcnt;
+
+ /*
+ * Only TX towards PDMA is affected.
+ * If DMA_PREP_INTERRUPT is not set by consumer then skip the transfer
+ * completion calculation, consumer must ensure that there is no stale
+ * data in DMA fabric in this case.
+ */
+ if (uc->config.ep_type == PSIL_EP_NATIVE ||
+ uc->config.dir != DMA_MEM_TO_DEV || !(uc->config.tx_flags & DMA_PREP_INTERRUPT))
+ return true;
+
+ peer_bcnt = udma_chanrt_read(uc, UDMA_CHAN_RT_PERIPH_BCNT_REG);
+ bcnt = udma_chanrt_read(uc, UDMA_CHAN_RT_BCNT_REG);
+
+ /* Transfer is incomplete, store current residue and time stamp */
+ if (peer_bcnt < bcnt) {
+ uc->tx_drain.residue = bcnt - peer_bcnt;
+ uc->tx_drain.tstamp = ktime_get();
+ return false;
+ }
+
+ return true;
+}
+
+static irqreturn_t udma_v2_udma_irq_handler(int irq, void *data)
+{
+ struct udma_chan *uc = data;
+ struct udma_dev *ud = uc->ud;
+ struct udma_desc *d;
+
+ switch (uc->config.dir) {
+ case DMA_DEV_TO_MEM:
+ k3_ringacc_ring_clear_irq(uc->rflow->r_ring);
+ break;
+ case DMA_MEM_TO_DEV:
+ case DMA_MEM_TO_MEM:
+ k3_ringacc_ring_clear_irq(uc->tchan->tc_ring);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ spin_lock(&uc->vc.lock);
+ d = uc->desc;
+ if (d) {
+ d->tr_idx = (d->tr_idx + 1) % d->sglen;
+
+ if (uc->cyclic) {
+ vchan_cyclic_callback(&d->vd);
+ } else {
+ /* TODO: figure out the real amount of data */
+ ud->udma_decrement_byte_counters(uc, d->residue);
+ ud->udma_start(uc);
+ vchan_cookie_complete(&d->vd);
+ }
+ }
+
+ spin_unlock(&uc->vc.lock);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t udma_v2_ring_irq_handler(int irq, void *data)
+{
+ struct udma_chan *uc = data;
+ struct udma_dev *ud = uc->ud;
+ struct udma_desc *d;
+ dma_addr_t paddr = 0;
+ u32 intr_status, reg;
+
+ switch (uc->config.dir) {
+ case DMA_DEV_TO_MEM:
+ intr_status = k3_ringacc_ring_get_irq_status(uc->rflow->r_ring);
+ break;
+ case DMA_MEM_TO_DEV:
+ case DMA_MEM_TO_MEM:
+ intr_status = k3_ringacc_ring_get_irq_status(uc->tchan->tc_ring);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ reg = udma_chanrt_read(uc, UDMA_CHAN_RT_CTL_REG);
+
+ if (intr_status & K3_RINGACC_RT_INT_STATUS_TR) {
+ /* check teardown status */
+ if ((reg & UDMA_CHAN_RT_CTL_TDOWN) && !(reg & UDMA_CHAN_RT_CTL_EN))
+ complete_all(&uc->teardown_completed);
+ return udma_v2_udma_irq_handler(irq, data);
+ }
+
+ if (udma_pop_from_ring(uc, &paddr) || !paddr)
+ return IRQ_HANDLED;
+
+ spin_lock(&uc->vc.lock);
+
+ /* Teardown completion message */
+ if (cppi5_desc_is_tdcm(paddr)) {
+ complete_all(&uc->teardown_completed);
+
+ if (uc->terminated_desc) {
+ udma_desc_free(&uc->terminated_desc->vd);
+ uc->terminated_desc = NULL;
+ }
+
+ if (!uc->desc)
+ ud->udma_start(uc);
+
+ goto out;
+ }
+
+ d = udma_udma_desc_from_paddr(uc, paddr);
+
+ if (d) {
+ dma_addr_t desc_paddr = udma_curr_cppi5_desc_paddr(d,
+ d->desc_idx);
+ if (desc_paddr != paddr) {
+ dev_err(uc->ud->dev, "not matching descriptors!\n");
+ goto out;
+ }
+
+ if (d == uc->desc) {
+ /* active descriptor */
+ if (uc->cyclic) {
+ udma_cyclic_packet_elapsed(uc);
+ vchan_cyclic_callback(&d->vd);
+ } else {
+ if (ud->udma_is_desc_really_done(uc, d)) {
+ ud->udma_decrement_byte_counters(uc, d->residue);
+ ud->udma_start(uc);
+ vchan_cookie_complete(&d->vd);
+ } else {
+ schedule_delayed_work(&uc->tx_drain.work,
+ 0);
+ }
+ }
+ } else {
+ /*
+ * terminated descriptor, mark the descriptor as
+ * completed to update the channel's cookie marker
+ */
+ dma_cookie_complete(&d->vd.tx);
+ }
+ }
+out:
+ spin_unlock(&uc->vc.lock);
+
+ return IRQ_HANDLED;
+}
+
+static int bcdma_v2_get_bchan(struct udma_chan *uc)
+{
+ struct udma_dev *ud = uc->ud;
+ enum udma_tp_level tpl;
+ int ret;
+
+ if (uc->bchan) {
+ dev_dbg(ud->dev, "chan%d: already have bchan%d allocated\n",
+ uc->id, uc->bchan->id);
+ return 0;
+ }
+
+ /*
+ * Use normal channels for peripherals, and highest TPL channel for
+ * mem2mem
+ */
+ if (uc->config.tr_trigger_type)
+ tpl = 0;
+ else
+ tpl = ud->bchan_tpl.levels - 1;
+
+ uc->bchan = __udma_reserve_bchan(ud, tpl, uc->id);
+ if (IS_ERR(uc->bchan)) {
+ ret = PTR_ERR(uc->bchan);
+ uc->bchan = NULL;
+ return ret;
+ }
+ uc->chan = uc->bchan;
+ uc->tchan = uc->bchan;
+
+ return 0;
+}
+
+static int bcdma_v2_alloc_bchan_resources(struct udma_chan *uc)
+{
+ struct k3_ring_cfg ring_cfg;
+ struct udma_dev *ud = uc->ud;
+ int ret;
+
+ ret = bcdma_v2_get_bchan(uc);
+ if (ret)
+ return ret;
+
+ ret = k3_ringacc_request_rings_pair(ud->ringacc, ud->match_data->chan_cnt + uc->id, -1,
+ &uc->bchan->t_ring,
+ &uc->bchan->tc_ring);
+ if (ret) {
+ ret = -EBUSY;
+ goto err_ring;
+ }
+
+ memset(&ring_cfg, 0, sizeof(ring_cfg));
+ ring_cfg.size = K3_UDMA_DEFAULT_RING_SIZE;
+ ring_cfg.elm_size = K3_RINGACC_RING_ELSIZE_8;
+ ring_cfg.mode = K3_RINGACC_RING_MODE_RING;
+
+ k3_configure_chan_coherency(&uc->vc.chan, ud->asel);
+ ring_cfg.asel = ud->asel;
+ ring_cfg.dma_dev = dmaengine_get_dma_device(&uc->vc.chan);
+
+ ret = k3_ringacc_ring_cfg(uc->bchan->t_ring, &ring_cfg);
+ if (ret)
+ goto err_ringcfg;
+
+ return 0;
+
+err_ringcfg:
+ k3_ringacc_ring_free(uc->bchan->tc_ring);
+ uc->bchan->tc_ring = NULL;
+ k3_ringacc_ring_free(uc->bchan->t_ring);
+ uc->bchan->t_ring = NULL;
+ k3_configure_chan_coherency(&uc->vc.chan, 0);
+err_ring:
+ bcdma_put_bchan(uc);
+
+ return ret;
+}
+
+static int udma_v2_alloc_tx_resources(struct udma_chan *uc)
+{
+ struct k3_ring_cfg ring_cfg;
+ struct udma_dev *ud = uc->ud;
+ struct udma_tchan *tchan;
+ int ring_idx, ret;
+
+ ret = udma_get_tchan(uc);
+ if (ret)
+ return ret;
+
+ tchan = uc->tchan;
+ if (tchan->tflow_id >= 0)
+ ring_idx = tchan->tflow_id;
+ else
+ ring_idx = tchan->id;
+
+ ret = k3_ringacc_request_rings_pair(ud->ringacc, ring_idx, -1,
+ &tchan->t_ring,
+ &tchan->tc_ring);
+ if (ret) {
+ ret = -EBUSY;
+ goto err_ring;
+ }
+
+ memset(&ring_cfg, 0, sizeof(ring_cfg));
+ ring_cfg.size = K3_UDMA_DEFAULT_RING_SIZE;
+ ring_cfg.elm_size = K3_RINGACC_RING_ELSIZE_8;
+ ring_cfg.mode = K3_RINGACC_RING_MODE_RING;
+
+ k3_configure_chan_coherency(&uc->vc.chan, uc->config.asel);
+ ring_cfg.asel = uc->config.asel;
+ ring_cfg.dma_dev = dmaengine_get_dma_device(&uc->vc.chan);
+
+ ret = k3_ringacc_ring_cfg(tchan->t_ring, &ring_cfg);
+ ret |= k3_ringacc_ring_cfg(tchan->tc_ring, &ring_cfg);
+
+ if (ret)
+ goto err_ringcfg;
+
+ return 0;
+
+err_ringcfg:
+ k3_ringacc_ring_free(uc->tchan->tc_ring);
+ uc->tchan->tc_ring = NULL;
+ k3_ringacc_ring_free(uc->tchan->t_ring);
+ uc->tchan->t_ring = NULL;
+err_ring:
+ udma_put_tchan(uc);
+
+ return ret;
+}
+
+static int udma_v2_alloc_rx_resources(struct udma_chan *uc)
+{
+ struct udma_dev *ud = uc->ud;
+ struct k3_ring_cfg ring_cfg;
+ struct udma_rflow *rflow;
+ int fd_ring_id;
+ int ret;
+
+ ret = udma_get_rchan(uc);
+ if (ret)
+ return ret;
+
+ /* For MEM_TO_MEM we don't need rflow or rings */
+ if (uc->config.dir == DMA_MEM_TO_MEM)
+ return 0;
+
+ if (uc->config.default_flow_id >= 0)
+ ret = udma_get_rflow(uc, uc->config.default_flow_id);
+ else
+ ret = udma_get_rflow(uc, uc->rchan->id);
+
+ if (ret) {
+ ret = -EBUSY;
+ goto err_rflow;
+ }
+
+ rflow = uc->rflow;
+ if (ud->tflow_cnt)
+ fd_ring_id = ud->tflow_cnt + rflow->id;
+ else
+ fd_ring_id = uc->rchan->id;
+ ret = k3_ringacc_request_rings_pair(ud->ringacc, fd_ring_id, -1,
+ &rflow->fd_ring, &rflow->r_ring);
+ if (ret) {
+ ret = -EBUSY;
+ goto err_ring;
+ }
+
+ memset(&ring_cfg, 0, sizeof(ring_cfg));
+
+ ring_cfg.elm_size = K3_RINGACC_RING_ELSIZE_8;
+ ring_cfg.size = K3_UDMA_DEFAULT_RING_SIZE;
+ ring_cfg.mode = K3_RINGACC_RING_MODE_RING;
+
+ k3_configure_chan_coherency(&uc->vc.chan, uc->config.asel);
+ ring_cfg.asel = uc->config.asel;
+ ring_cfg.dma_dev = dmaengine_get_dma_device(&uc->vc.chan);
+
+ ret = k3_ringacc_ring_cfg(rflow->fd_ring, &ring_cfg);
+
+ ring_cfg.size = K3_UDMA_DEFAULT_RING_SIZE;
+ ret |= k3_ringacc_ring_cfg(rflow->r_ring, &ring_cfg);
+
+ if (ret)
+ goto err_ringcfg;
+
+ return 0;
+
+err_ringcfg:
+ k3_ringacc_ring_free(rflow->r_ring);
+ rflow->r_ring = NULL;
+ k3_ringacc_ring_free(rflow->fd_ring);
+ rflow->fd_ring = NULL;
+err_ring:
+ udma_put_rflow(uc);
+err_rflow:
+ udma_put_rchan(uc);
+
+ return ret;
+}
+
+static int bcdma_v2_alloc_chan_resources(struct dma_chan *chan)
+{
+ struct udma_chan *uc = to_udma_chan(chan);
+ struct udma_dev *ud = to_udma_dev(chan->device);
+ u32 irq_ring_idx;
+ __be32 addr[2] = {0, 0};
+ struct of_phandle_args out_irq;
+ int ret;
+
+ /* Only TR mode is supported */
+ uc->config.pkt_mode = false;
+
+ /*
+ * Make sure that the completion is in a known state:
+ * No teardown, the channel is idle
+ */
+ reinit_completion(&uc->teardown_completed);
+ complete_all(&uc->teardown_completed);
+ uc->state = UDMA_CHAN_IS_IDLE;
+
+ switch (uc->config.dir) {
+ case DMA_MEM_TO_MEM:
+ /* Non synchronized - mem to mem type of transfer */
+ dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-MEM\n", __func__,
+ uc->id);
+
+ ret = bcdma_v2_alloc_bchan_resources(uc);
+ if (ret)
+ return ret;
+
+ irq_ring_idx = ud->match_data->chan_cnt + uc->id;
+ break;
+ case DMA_MEM_TO_DEV:
+ /* Slave transfer synchronized - mem to dev (TX) trasnfer */
+ dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-DEV\n", __func__,
+ uc->id);
+
+ ret = udma_v2_alloc_tx_resources(uc);
+ if (ret) {
+ uc->config.remote_thread_id = -1;
+ return ret;
+ }
+
+ uc->config.src_thread = ud->psil_base + uc->tchan->id;
+ uc->config.dst_thread = uc->config.remote_thread_id;
+ uc->config.dst_thread |= K3_PSIL_DST_THREAD_ID_OFFSET;
+
+ irq_ring_idx = uc->tchan->id;
+
+ break;
+ case DMA_DEV_TO_MEM:
+ /* Slave transfer synchronized - dev to mem (RX) trasnfer */
+ dev_dbg(uc->ud->dev, "%s: chan%d as DEV-to-MEM\n", __func__,
+ uc->id);
+
+ ret = udma_v2_alloc_rx_resources(uc);
+ if (ret) {
+ uc->config.remote_thread_id = -1;
+ return ret;
+ }
+
+ uc->config.src_thread = uc->config.remote_thread_id;
+ uc->config.dst_thread = (ud->psil_base + uc->rchan->id) |
+ K3_PSIL_DST_THREAD_ID_OFFSET;
+
+ irq_ring_idx = uc->rchan->id;
+
+ break;
+ default:
+ /* Can not happen */
+ dev_err(uc->ud->dev, "%s: chan%d invalid direction (%u)\n",
+ __func__, uc->id, uc->config.dir);
+ return -EINVAL;
+ }
+
+ /* check if the channel configuration was successful */
+ if (ret)
+ goto err_res_free;
+
+ if (udma_is_chan_running(uc)) {
+ dev_warn(ud->dev, "chan%d: is running!\n", uc->id);
+ ud->udma_reset_chan(uc, false);
+ if (udma_is_chan_running(uc)) {
+ dev_err(ud->dev, "chan%d: won't stop!\n", uc->id);
+ ret = -EBUSY;
+ goto err_res_free;
+ }
+ }
+
+ uc->dma_dev = dmaengine_get_dma_device(chan);
+ if (uc->config.dir == DMA_MEM_TO_MEM && !uc->config.tr_trigger_type) {
+ uc->config.hdesc_size = cppi5_trdesc_calc_size(
+ sizeof(struct cppi5_tr_type15_t), 2);
+
+ uc->hdesc_pool = dma_pool_create(uc->name, ud->ddev.dev,
+ uc->config.hdesc_size,
+ ud->desc_align,
+ 0);
+ if (!uc->hdesc_pool) {
+ dev_err(ud->ddev.dev,
+ "Descriptor pool allocation failed\n");
+ uc->use_dma_pool = false;
+ ret = -ENOMEM;
+ goto err_res_free;
+ }
+
+ uc->use_dma_pool = true;
+ } else if (uc->config.dir != DMA_MEM_TO_MEM) {
+ uc->psil_paired = true;
+ }
+
+ out_irq.np = dev_of_node(ud->dev);
+ out_irq.args_count = 1;
+ out_irq.args[0] = irq_ring_idx;
+ ret = of_irq_parse_raw(addr, &out_irq);
+ if (ret)
+ return ret;
+
+ uc->irq_num_ring = irq_create_of_mapping(&out_irq);
+
+ ret = devm_request_irq(ud->dev, uc->irq_num_ring, udma_v2_ring_irq_handler,
+ IRQF_TRIGGER_HIGH, uc->name, uc);
+ if (ret) {
+ dev_err(ud->dev, "chan%d: ring irq request failed\n", uc->id);
+ goto err_irq_free;
+ }
+
+ udma_reset_rings(uc);
+
+ INIT_DELAYED_WORK_ONSTACK(&uc->tx_drain.work,
+ udma_check_tx_completion);
+ return 0;
+
+err_irq_free:
+ uc->irq_num_ring = 0;
+ uc->irq_num_udma = 0;
+err_res_free:
+ bcdma_free_bchan_resources(uc);
+ udma_free_tx_resources(uc);
+ udma_free_rx_resources(uc);
+
+ udma_reset_uchan(uc);
+
+ if (uc->use_dma_pool) {
+ dma_pool_destroy(uc->hdesc_pool);
+ uc->use_dma_pool = false;
+ }
+
+ return ret;
+}
+
+static enum dma_status udma_v2_tx_status(struct dma_chan *chan,
+ dma_cookie_t cookie,
+ struct dma_tx_state *txstate)
+{
+ struct udma_chan *uc = to_udma_chan(chan);
+ enum dma_status ret;
+ unsigned long flags;
+
+ spin_lock_irqsave(&uc->vc.lock, flags);
+
+ ret = dma_cookie_status(chan, cookie, txstate);
+
+ if (!udma_is_chan_running(uc))
+ ret = DMA_COMPLETE;
+
+ if (ret == DMA_IN_PROGRESS && udma_v2_is_chan_paused(uc))
+ ret = DMA_PAUSED;
+
+ if (ret == DMA_COMPLETE || !txstate)
+ goto out;
+
+ if (uc->desc && uc->desc->vd.tx.cookie == cookie) {
+ u32 peer_bcnt = 0;
+ u32 bcnt = 0;
+ u32 residue = uc->desc->residue;
+ u32 delay = 0;
+
+ if (uc->desc->dir == DMA_MEM_TO_DEV) {
+ bcnt = udma_chanrt_read(uc, UDMA_CHAN_RT_SBCNT_REG);
+
+ if (uc->config.ep_type != PSIL_EP_NATIVE) {
+ peer_bcnt = udma_chanrt_read(uc, 0x810);
+
+ if (bcnt > peer_bcnt)
+ delay = bcnt - peer_bcnt;
+ }
+ } else if (uc->desc->dir == DMA_DEV_TO_MEM) {
+ bcnt = udma_chanrt_read(uc, UDMA_CHAN_RT_BCNT_REG);
+
+ if (uc->config.ep_type != PSIL_EP_NATIVE) {
+ peer_bcnt = udma_chanrt_read(uc, 0x810);
+
+ if (peer_bcnt > bcnt)
+ delay = peer_bcnt - bcnt;
+ }
+ } else {
+ bcnt = udma_chanrt_read(uc, UDMA_CHAN_RT_BCNT_REG);
+ }
+
+ if (bcnt && !(bcnt % uc->desc->residue))
+ residue = 0;
+ else
+ residue -= bcnt % uc->desc->residue;
+
+ if (!residue && (uc->config.dir == DMA_DEV_TO_MEM || !delay)) {
+ ret = DMA_COMPLETE;
+ delay = 0;
+ }
+
+ dma_set_residue(txstate, residue);
+ dma_set_in_flight_bytes(txstate, delay);
+
+ } else {
+ ret = DMA_COMPLETE;
+ }
+
+out:
+ spin_unlock_irqrestore(&uc->vc.lock, flags);
+ return ret;
+}
+
+static int udma_v2_pause(struct dma_chan *chan)
+{
+ struct udma_chan *uc = to_udma_chan(chan);
+
+ /* pause the channel */
+ udma_chanrt_update_bits(uc, UDMA_CHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_PAUSE, UDMA_CHAN_RT_CTL_PAUSE);
+
+ return 0;
+}
+
+static int udma_v2_resume(struct dma_chan *chan)
+{
+ struct udma_chan *uc = to_udma_chan(chan);
+
+ /* resume the channel */
+ udma_chanrt_update_bits(uc, UDMA_CHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_PAUSE, 0);
+
+ return 0;
+}
+
+static struct platform_driver bcdma_v2_driver;
+
+static bool udma_v2_dma_filter_fn(struct dma_chan *chan, void *param)
+{
+ struct udma_chan_config *ucc;
+ struct psil_endpoint_config *ep_config;
+ struct udma_v2_filter_param *filter_param;
+ struct udma_chan *uc;
+ struct udma_dev *ud;
+
+ if (chan->device->dev->driver != &bcdma_v2_driver.driver)
+ return false;
+
+ uc = to_udma_chan(chan);
+ ucc = &uc->config;
+ ud = uc->ud;
+ filter_param = param;
+
+ if (filter_param->asel > 15) {
+ dev_err(ud->dev, "Invalid channel asel: %u\n",
+ filter_param->asel);
+ return false;
+ }
+
+ ucc->remote_thread_id = filter_param->remote_thread_id;
+ ucc->asel = filter_param->asel;
+ ucc->tr_trigger_type = filter_param->tr_trigger_type;
+
+ if (ucc->tr_trigger_type) {
+ ucc->dir = DMA_MEM_TO_MEM;
+ goto triggered_bchan;
+ } else if (ucc->remote_thread_id & K3_PSIL_DST_THREAD_ID_OFFSET) {
+ ucc->dir = DMA_MEM_TO_DEV;
+ } else {
+ ucc->dir = DMA_DEV_TO_MEM;
+ }
+
+ ep_config = psil_get_ep_config(ucc->remote_thread_id);
+ if (IS_ERR(ep_config)) {
+ dev_err(ud->dev, "No configuration for psi-l thread 0x%04x\n",
+ ucc->remote_thread_id);
+ ucc->dir = DMA_MEM_TO_MEM;
+ ucc->remote_thread_id = -1;
+ ucc->atype = 0;
+ ucc->asel = 0;
+ return false;
+ }
+
+ ucc->pkt_mode = ep_config->pkt_mode;
+ ucc->channel_tpl = ep_config->channel_tpl;
+ ucc->notdpkt = ep_config->notdpkt;
+ ucc->ep_type = ep_config->ep_type;
+
+ if ((ud->match_data->type == DMA_TYPE_BCDMA_V2) &&
+ ep_config->mapped_channel_id >= 0) {
+ ucc->mapped_channel_id = ep_config->mapped_channel_id;
+ ucc->default_flow_id = ep_config->default_flow_id;
+ } else {
+ ucc->mapped_channel_id = -1;
+ ucc->default_flow_id = -1;
+ }
+
+ ucc->needs_epib = ep_config->needs_epib;
+ ucc->psd_size = ep_config->psd_size;
+ ucc->metadata_size =
+ (ucc->needs_epib ? CPPI5_INFO0_HDESC_EPIB_SIZE : 0) +
+ ucc->psd_size;
+
+ if (ucc->ep_type != PSIL_EP_NATIVE) {
+ const struct udma_match_data *match_data = ud->match_data;
+
+ if ((match_data->flags & UDMA_FLAG_PDMA_ACC32) && (ep_config->pdma_acc32))
+ ucc->enable_acc32 = true;
+ else
+ ucc->enable_acc32 = false;
+
+ if ((match_data->flags & UDMA_FLAG_PDMA_BURST) && (ep_config->pdma_burst))
+ ucc->enable_burst = true;
+ else
+ ucc->enable_burst = false;
+ }
+ if (ucc->pkt_mode)
+ ucc->hdesc_size = ALIGN(sizeof(struct cppi5_host_desc_t) +
+ ucc->metadata_size, ud->desc_align);
+
+ dev_dbg(ud->dev, "chan%d: Remote thread: 0x%04x (%s)\n", uc->id,
+ ucc->remote_thread_id, dmaengine_get_direction_text(ucc->dir));
+
+ return true;
+
+triggered_bchan:
+ dev_dbg(ud->dev, "chan%d: triggered channel (type: %u)\n", uc->id,
+ ucc->tr_trigger_type);
+
+ return true;
+}
+
+static struct dma_chan *udma_v2_of_xlate(struct of_phandle_args *dma_spec,
+ struct of_dma *ofdma)
+{
+ struct udma_dev *ud = ofdma->of_dma_data;
+ dma_cap_mask_t mask = ud->ddev.cap_mask;
+ struct udma_v2_filter_param filter_param;
+ struct dma_chan *chan;
+
+ if (ud->match_data->type == DMA_TYPE_BCDMA_V2) {
+ if (dma_spec->args_count != 4)
+ return NULL;
+
+ filter_param.tr_trigger_type = dma_spec->args[0];
+ filter_param.trigger_param = dma_spec->args[1];
+ filter_param.remote_thread_id = dma_spec->args[2];
+ filter_param.asel = dma_spec->args[3];
+ } else {
+ if (dma_spec->args_count != 1 && dma_spec->args_count != 2)
+ return NULL;
+
+ filter_param.remote_thread_id = dma_spec->args[0];
+ filter_param.tr_trigger_type = 0;
+ if (dma_spec->args_count == 2)
+ filter_param.asel = dma_spec->args[1];
+ else
+ filter_param.asel = 0;
+ }
+
+ chan = __dma_request_channel(&mask, udma_v2_dma_filter_fn, &filter_param,
+ ofdma->of_node);
+ if (!chan) {
+ dev_err(ud->dev, "get channel fail in %s.\n", __func__);
+ return ERR_PTR(-EINVAL);
+ }
+
+ return chan;
+}
+
+static struct udma_match_data bcdma_v2_data = {
+ .type = DMA_TYPE_BCDMA_V2,
+ .psil_base = 0x2000, /* for tchan and rchan, not applicable to bchan */
+ .enable_memcpy_support = true, /* Supported via bchan */
+ .flags = UDMA_FLAGS_J7_CLASS,
+ .statictr_z_mask = GENMASK(23, 0),
+ .burst_size = {
+ TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES, /* Normal Channels */
+ 0, /* No H Channels */
+ 0, /* No UH Channels */
+ },
+ .bchan_cnt = 16,
+ .chan_cnt = 128,
+ .tchan_cnt = 128,
+ .rchan_cnt = 128,
+};
+
+static const struct of_device_id udma_of_match[] = {
+ {
+ .compatible = "ti,dmss-bcdma-v2",
+ .data = &bcdma_v2_data,
+ },
+ { /* Sentinel */ },
+};
+
+static const struct soc_device_attribute k3_soc_devices[] = {
+ { .family = "AM62LX", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, udma_of_match);
+
+static int udma_v2_get_mmrs(struct platform_device *pdev, struct udma_dev *ud)
+{
+ u32 cap2, cap3;
+ int i;
+
+ ud->mmrs[V2_MMR_GCFG] = devm_platform_ioremap_resource_byname(pdev,
+ v2_mmr_names[V2_MMR_GCFG]);
+ if (IS_ERR(ud->mmrs[V2_MMR_GCFG]))
+ return PTR_ERR(ud->mmrs[V2_MMR_GCFG]);
+
+ cap2 = udma_read(ud->mmrs[V2_MMR_GCFG], 0x28);
+ cap3 = udma_read(ud->mmrs[V2_MMR_GCFG], 0x2c);
+
+ ud->bchan_cnt = ud->match_data->bchan_cnt;
+ /* There are no tchan and rchan in BCDMA_V2.
+ * Duplicate chan as tchan and rchan to keep the common code
+ * in k3-udma-common.c functional for BCDMA_V2.
+ */
+ ud->chan_cnt = ud->match_data->chan_cnt;
+ ud->tchan_cnt = ud->match_data->chan_cnt;
+ ud->rchan_cnt = ud->match_data->chan_cnt;
+ ud->rflow_cnt = ud->chan_cnt;
+
+ for (i = 1; i < V2_MMR_LAST; i++) {
+ if (i == V2_MMR_BCHANRT && ud->bchan_cnt == 0)
+ continue;
+ if (i == V2_MMR_CHANRT && ud->chan_cnt == 0)
+ continue;
+
+ ud->mmrs[i] = devm_platform_ioremap_resource_byname(pdev, v2_mmr_names[i]);
+ if (IS_ERR(ud->mmrs[i]))
+ return PTR_ERR(ud->mmrs[i]);
+ }
+
+ return 0;
+}
+
+static int udma_v2_probe(struct platform_device *pdev)
+{
+ const struct soc_device_attribute *soc;
+ struct device *dev = &pdev->dev;
+ struct udma_dev *ud;
+ const struct of_device_id *match;
+ int i, ret;
+ int ch_count;
+
+ ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(48));
+ if (ret)
+ dev_err(dev, "failed to set dma mask stuff\n");
+
+ ud = devm_kzalloc(dev, sizeof(*ud), GFP_KERNEL);
+ if (!ud)
+ return -ENOMEM;
+
+ match = of_match_node(udma_of_match, dev->of_node);
+ if (!match) {
+ dev_err(dev, "No compatible match found\n");
+ return -ENODEV;
+ }
+ ud->match_data = match->data;
+
+ ud->soc_data = ud->match_data->soc_data;
+ if (!ud->soc_data) {
+ soc = soc_device_match(k3_soc_devices);
+ if (!soc) {
+ dev_err(dev, "No compatible SoC found\n");
+ return -ENODEV;
+ }
+ ud->soc_data = soc->data;
+ }
+ // Setup function pointers
+ ud->udma_start = udma_v2_start;
+ ud->udma_stop = udma_v2_stop;
+ ud->udma_reset_chan = udma_v2_reset_chan;
+ ud->udma_is_desc_really_done = udma_v2_is_desc_really_done;
+ ud->udma_decrement_byte_counters = udma_v2_decrement_byte_counters;
+
+ ret = udma_v2_get_mmrs(pdev, ud);
+ if (ret)
+ return ret;
+
+ struct k3_ringacc_init_data ring_init_data = {0};
+
+ ring_init_data.num_rings = ud->bchan_cnt + ud->chan_cnt;
+
+ ud->ringacc = k3_ringacc_dmarings_init(pdev, &ring_init_data);
+
+ if (IS_ERR(ud->ringacc))
+ return PTR_ERR(ud->ringacc);
+
+ dma_cap_set(DMA_SLAVE, ud->ddev.cap_mask);
+
+ dma_cap_set(DMA_CYCLIC, ud->ddev.cap_mask);
+ ud->ddev.device_prep_dma_cyclic = udma_prep_dma_cyclic;
+
+ ud->ddev.device_config = udma_slave_config;
+ ud->ddev.device_prep_slave_sg = udma_prep_slave_sg;
+ ud->ddev.device_issue_pending = udma_issue_pending;
+ ud->ddev.device_tx_status = udma_v2_tx_status;
+ ud->ddev.device_pause = udma_v2_pause;
+ ud->ddev.device_resume = udma_v2_resume;
+ ud->ddev.device_terminate_all = udma_terminate_all;
+ ud->ddev.device_synchronize = udma_synchronize;
+#ifdef CONFIG_DEBUG_FS
+ ud->ddev.dbg_summary_show = udma_dbg_summary_show;
+#endif
+
+ ud->ddev.device_alloc_chan_resources =
+ bcdma_v2_alloc_chan_resources;
+
+ ud->ddev.device_free_chan_resources = udma_free_chan_resources;
+
+ ud->ddev.src_addr_widths = TI_UDMAC_BUSWIDTHS;
+ ud->ddev.dst_addr_widths = TI_UDMAC_BUSWIDTHS;
+ ud->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
+ ud->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
+ ud->ddev.desc_metadata_modes = DESC_METADATA_CLIENT |
+ DESC_METADATA_ENGINE;
+ if (ud->match_data->enable_memcpy_support &&
+ !(ud->match_data->type == DMA_TYPE_BCDMA && ud->bchan_cnt == 0)) {
+ dma_cap_set(DMA_MEMCPY, ud->ddev.cap_mask);
+ ud->ddev.device_prep_dma_memcpy = udma_prep_dma_memcpy;
+ ud->ddev.directions |= BIT(DMA_MEM_TO_MEM);
+ }
+
+ ud->ddev.dev = dev;
+ ud->dev = dev;
+ ud->psil_base = ud->match_data->psil_base;
+
+ INIT_LIST_HEAD(&ud->ddev.channels);
+ INIT_LIST_HEAD(&ud->desc_to_purge);
+
+ ch_count = setup_resources(ud);
+ if (ch_count <= 0)
+ return ch_count;
+
+ spin_lock_init(&ud->lock);
+ INIT_WORK(&ud->purge_work, udma_purge_desc_work);
+
+ ud->desc_align = 64;
+ if (ud->desc_align < dma_get_cache_alignment())
+ ud->desc_align = dma_get_cache_alignment();
+
+ ret = udma_setup_rx_flush(ud);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < ud->bchan_cnt; i++) {
+ struct udma_bchan *bchan = &ud->bchans[i];
+
+ bchan->id = i;
+ bchan->reg_rt = ud->mmrs[V2_MMR_BCHANRT] + i * 0x1000;
+ }
+
+ for (i = 0; i < ud->tchan_cnt; i++) {
+ struct udma_tchan *tchan = &ud->tchans[i];
+
+ tchan->id = i;
+ tchan->reg_rt = ud->mmrs[V2_MMR_CHANRT] + i * 0x1000;
+ }
+
+ for (i = 0; i < ud->rchan_cnt; i++) {
+ struct udma_rchan *rchan = &ud->rchans[i];
+
+ rchan->id = i;
+ rchan->reg_rt = ud->mmrs[V2_MMR_CHANRT] + i * 0x1000;
+ }
+
+ for (i = 0; i < ud->rflow_cnt; i++) {
+ struct udma_rflow *rflow = &ud->rflows[i];
+
+ rflow->id = i;
+ rflow->reg_rt = ud->rflow_rt + i * 0x2000;
+ }
+
+ for (i = 0; i < ch_count; i++) {
+ struct udma_chan *uc = &ud->channels[i];
+
+ uc->ud = ud;
+ uc->vc.desc_free = udma_desc_free;
+ uc->id = i;
+ uc->bchan = NULL;
+ uc->tchan = NULL;
+ uc->rchan = NULL;
+ uc->config.remote_thread_id = -1;
+ uc->config.mapped_channel_id = -1;
+ uc->config.default_flow_id = -1;
+ uc->config.dir = DMA_MEM_TO_MEM;
+ uc->name = devm_kasprintf(dev, GFP_KERNEL, "%s chan%d",
+ dev_name(dev), i);
+
+ vchan_init(&uc->vc, &ud->ddev);
+ /* Use custom vchan completion handling */
+ tasklet_setup(&uc->vc.task, udma_vchan_complete);
+ init_completion(&uc->teardown_completed);
+ INIT_DELAYED_WORK(&uc->tx_drain.work, udma_check_tx_completion);
+ }
+
+ /* Configure the copy_align to the maximum burst size the device supports */
+ ud->ddev.copy_align = udma_get_copy_align(ud);
+
+ ret = dma_async_device_register(&ud->ddev);
+ if (ret) {
+ dev_err(dev, "failed to register slave DMA engine: %d\n", ret);
+ return ret;
+ }
+
+ platform_set_drvdata(pdev, ud);
+
+ ret = of_dma_controller_register(dev->of_node, udma_v2_of_xlate, ud);
+ if (ret) {
+ dev_err(dev, "failed to register of_dma controller\n");
+ dma_async_device_unregister(&ud->ddev);
+ }
+
+ return ret;
+}
+
+static int __maybe_unused udma_v2_pm_suspend(struct device *dev)
+{
+ struct udma_dev *ud = dev_get_drvdata(dev);
+ struct dma_device *dma_dev = &ud->ddev;
+ struct dma_chan *chan;
+ struct udma_chan *uc;
+
+ list_for_each_entry(chan, &dma_dev->channels, device_node) {
+ if (chan->client_count) {
+ uc = to_udma_chan(chan);
+ /* backup the channel configuration */
+ memcpy(&uc->backup_config, &uc->config,
+ sizeof(struct udma_chan_config));
+ dev_dbg(dev, "Suspending channel %s\n",
+ dma_chan_name(chan));
+ ud->ddev.device_free_chan_resources(chan);
+ }
+ }
+
+ return 0;
+}
+
+static int __maybe_unused udma_v2_pm_resume(struct device *dev)
+{
+ struct udma_dev *ud = dev_get_drvdata(dev);
+ struct dma_device *dma_dev = &ud->ddev;
+ struct dma_chan *chan;
+ struct udma_chan *uc;
+ int ret;
+
+ list_for_each_entry(chan, &dma_dev->channels, device_node) {
+ if (chan->client_count) {
+ uc = to_udma_chan(chan);
+ /* restore the channel configuration */
+ memcpy(&uc->config, &uc->backup_config,
+ sizeof(struct udma_chan_config));
+ dev_dbg(dev, "Resuming channel %s\n",
+ dma_chan_name(chan));
+ ret = ud->ddev.device_alloc_chan_resources(chan);
+ if (ret)
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static const struct dev_pm_ops udma_pm_ops = {
+ SET_LATE_SYSTEM_SLEEP_PM_OPS(udma_v2_pm_suspend, udma_v2_pm_resume)
+};
+
+static struct platform_driver bcdma_v2_driver = {
+ .driver = {
+ .name = "ti-udma-v2",
+ .of_match_table = udma_of_match,
+ .suppress_bind_attrs = true,
+ .pm = &udma_pm_ops,
+ },
+ .probe = udma_v2_probe,
+};
+
+module_platform_driver(bcdma_v2_driver);
+MODULE_DESCRIPTION("Texas Instruments K3 UDMA v2 support");
+MODULE_LICENSE("GPL");
+
diff --git a/drivers/dma/ti/k3-udma.h b/drivers/dma/ti/k3-udma.h
index 4de6f38089ce7..c054113640bf4 100644
--- a/drivers/dma/ti/k3-udma.h
+++ b/drivers/dma/ti/k3-udma.h
@@ -49,6 +49,8 @@
#define UDMA_CHAN_RT_SWTRIG_REG 0x8
#define UDMA_CHAN_RT_STDATA_REG 0x80
+#define UDMA_CHAN_RT_PDMA_STATE_REG 0x80c
+
#define UDMA_CHAN_RT_PEER_REG(i) (0x200 + ((i) * 0x4))
#define UDMA_CHAN_RT_PEER_STATIC_TR_XY_REG \
UDMA_CHAN_RT_PEER_REG(0) /* PSI-L: 0x400 */
@@ -88,8 +90,16 @@
#define UDMA_CHAN_RT_CTL_TDOWN BIT(30)
#define UDMA_CHAN_RT_CTL_PAUSE BIT(29)
#define UDMA_CHAN_RT_CTL_FTDOWN BIT(28)
+#define UDMA_CHAN_RT_CTL_AUTOPAIR BIT(23)
+#define UDMA_CHAN_RT_CTL_PAIR_TIMEOUT BIT(17)
+#define UDMA_CHAN_RT_CTL_PAIR_COMPLETE BIT(16)
#define UDMA_CHAN_RT_CTL_ERROR BIT(0)
+/* UDMA_CHAN_RT_PDMA_STATE_REG */
+#define UDMA_CHAN_RT_PDMA_STATE_IN_EVT BIT(31)
+#define UDMA_CHAN_RT_PDMA_STATE_TDOWN BIT(30)
+#define UDMA_CHAN_RT_PDMA_STATE_PAUSE BIT(29)
+
/* UDMA_CHAN_RT_PEER_RT_EN_REG */
#define UDMA_PEER_RT_EN_ENABLE BIT(31)
#define UDMA_PEER_RT_EN_TEARDOWN BIT(30)
@@ -120,6 +130,9 @@
*/
#define PDMA_STATIC_TR_Z(x, mask) ((x) & (mask))
+/* UDMA_CHAN_RT_PEER_REG(8) */
+#define UDMA_CHAN_RT_PEER_REG8_FLUSH 0x09000000
+
/* Address Space Select */
#define K3_ADDRESS_ASEL_SHIFT 48
@@ -154,10 +167,15 @@
BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
+struct udma_chan;
+struct udma_dev;
+
enum k3_dma_type {
DMA_TYPE_UDMA = 0,
DMA_TYPE_BCDMA,
DMA_TYPE_PKTDMA,
+ DMA_TYPE_BCDMA_V2,
+ DMA_TYPE_PKTDMA_V2,
};
enum udma_mmr {
@@ -168,6 +186,13 @@ enum udma_mmr {
MMR_LAST,
};
+enum udma_v2_mmr {
+ V2_MMR_GCFG = 0,
+ V2_MMR_BCHANRT,
+ V2_MMR_CHANRT,
+ V2_MMR_LAST,
+};
+
enum udma_rm_range {
RM_RANGE_BCHAN = 0,
RM_RANGE_TCHAN,
@@ -190,6 +215,13 @@ struct udma_filter_param {
u32 tr_trigger_type;
};
+struct udma_v2_filter_param {
+ u32 tr_trigger_type;
+ u32 trigger_param;
+ int remote_thread_id;
+ u32 asel;
+};
+
struct udma_static_tr {
u8 elsize; /* RPSTR0 */
u16 elcnt; /* RPSTR0 */
@@ -206,17 +238,13 @@ struct udma_tchan {
};
#define udma_bchan udma_tchan
+#define udma_rchan udma_tchan
struct udma_rflow {
int id;
struct k3_ring *fd_ring; /* Free Descriptor ring */
struct k3_ring *r_ring; /* Receive ring */
-};
-
-struct udma_rchan {
void __iomem *reg_rt;
-
- int id;
};
struct udma_oes_offsets {
@@ -256,6 +284,12 @@ struct udma_match_data {
u32 statictr_z_mask;
u8 burst_size[3];
struct udma_soc_data *soc_data;
+ u32 bchan_cnt;
+ u32 chan_cnt;
+ u32 tchan_cnt;
+ u32 rchan_cnt;
+ u32 tflow_cnt;
+ u32 rflow_cnt;
};
struct udma_soc_data {
@@ -345,6 +379,7 @@ struct udma_dev {
struct dma_device ddev;
struct device *dev;
void __iomem *mmrs[MMR_LAST];
+ void __iomem *rflow_rt;
const struct udma_match_data *match_data;
const struct udma_soc_data *soc_data;
@@ -365,12 +400,14 @@ struct udma_dev {
struct udma_rx_flush rx_flush;
int bchan_cnt;
+ int chan_cnt;
int tchan_cnt;
int echan_cnt;
int rchan_cnt;
int rflow_cnt;
int tflow_cnt;
unsigned long *bchan_map;
+ unsigned long *chan_map;
unsigned long *tchan_map;
unsigned long *rchan_map;
unsigned long *rflow_gp_map;
@@ -379,6 +416,7 @@ struct udma_dev {
unsigned long *tflow_map;
struct udma_bchan *bchans;
+ struct udma_tchan *chans;
struct udma_tchan *tchans;
struct udma_rchan *rchans;
struct udma_rflow *rflows;
@@ -395,7 +433,6 @@ struct udma_dev {
void (*udma_decrement_byte_counters)(struct udma_chan *uc, u32 val);
};
-
struct udma_chan {
struct virt_dma_chan vc;
struct dma_slave_config cfg;
@@ -407,6 +444,7 @@ struct udma_chan {
char *name;
struct udma_bchan *bchan;
+ struct udma_tchan *chan;
struct udma_tchan *tchan;
struct udma_rchan *rchan;
struct udma_rflow *rflow;
@@ -476,51 +514,33 @@ static inline void udma_update_bits(void __iomem *base, int reg,
writel(tmp, base + reg);
}
-/* TCHANRT */
-static inline u32 udma_tchanrt_read(struct udma_chan *uc, int reg)
-{
- if (!uc->tchan)
- return 0;
- return udma_read(uc->tchan->reg_rt, reg);
-}
-
-static inline void udma_tchanrt_write(struct udma_chan *uc, int reg, u32 val)
-{
- if (!uc->tchan)
- return;
- udma_write(uc->tchan->reg_rt, reg, val);
+#define _UDMA_REG_ACCESS(channel) \
+static inline u32 udma_##channel##rt_read(struct udma_chan *uc, int reg) \
+{ \
+ if (!uc->channel) \
+ return 0; \
+ return udma_read(uc->channel->reg_rt, reg); \
+} \
+\
+static inline void udma_##channel##rt_write(struct udma_chan *uc, int reg, u32 val) \
+{ \
+ if (!uc->channel) \
+ return; \
+ udma_write(uc->channel->reg_rt, reg, val); \
+} \
+\
+static inline void udma_##channel##rt_update_bits(struct udma_chan *uc, int reg, \
+ u32 mask, u32 val) \
+{ \
+ if (!uc->channel) \
+ return; \
+ udma_update_bits(uc->channel->reg_rt, reg, mask, val); \
}
-static inline void udma_tchanrt_update_bits(struct udma_chan *uc, int reg,
- u32 mask, u32 val)
-{
- if (!uc->tchan)
- return;
- udma_update_bits(uc->tchan->reg_rt, reg, mask, val);
-}
-
-/* RCHANRT */
-static inline u32 udma_rchanrt_read(struct udma_chan *uc, int reg)
-{
- if (!uc->rchan)
- return 0;
- return udma_read(uc->rchan->reg_rt, reg);
-}
-
-static inline void udma_rchanrt_write(struct udma_chan *uc, int reg, u32 val)
-{
- if (!uc->rchan)
- return;
- udma_write(uc->rchan->reg_rt, reg, val);
-}
-
-static inline void udma_rchanrt_update_bits(struct udma_chan *uc, int reg,
- u32 mask, u32 val)
-{
- if (!uc->rchan)
- return;
- udma_update_bits(uc->rchan->reg_rt, reg, mask, val);
-}
+_UDMA_REG_ACCESS(chan);
+_UDMA_REG_ACCESS(bchan);
+_UDMA_REG_ACCESS(tchan);
+_UDMA_REG_ACCESS(rchan);
static inline dma_addr_t udma_curr_cppi5_desc_paddr(struct udma_desc *d,
int idx)
diff --git a/include/linux/soc/ti/k3-ringacc.h b/include/linux/soc/ti/k3-ringacc.h
index fcf6fbd4a8594..2711f4119b0ee 100644
--- a/include/linux/soc/ti/k3-ringacc.h
+++ b/include/linux/soc/ti/k3-ringacc.h
@@ -10,6 +10,9 @@
#include <linux/types.h>
+#define K3_RINGACC_RT_INT_STATUS_COMPLETE BIT(0)
+#define K3_RINGACC_RT_INT_STATUS_TR BIT(2)
+
struct device_node;
/**
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 7/8] dmaengine: ti: k3-udma-v2: Add support for PKTDMA V2
2025-04-28 7:20 [PATCH 0/8] dmaengine: ti: Add support for BCDMA v2 and PKTDMA v2 Sai Sree Kartheek Adivi
` (4 preceding siblings ...)
2025-04-28 7:20 ` [PATCH 6/8] dmaengine: ti: New driver for K3 BCDMA_V2 Sai Sree Kartheek Adivi
@ 2025-04-28 7:20 ` Sai Sree Kartheek Adivi
2025-04-28 7:20 ` [PATCH 8/8] dmaengine: ti: k3-udma-v2: Update glue layer to support " Sai Sree Kartheek Adivi
[not found] ` <20250428072032.946008-4-s-adivi@ti.com>
7 siblings, 0 replies; 17+ messages in thread
From: Sai Sree Kartheek Adivi @ 2025-04-28 7:20 UTC (permalink / raw)
To: peter.ujfalusi, vkoul, robh, krzk+dt, conor+dt, nm, ssantosh,
s-adivi, dmaengine, devicetree, linux-kernel, linux-arm-kernel,
praneeth, vigneshr, u-kumar1, a-chavda
The PKTDMA V2 is different than the existing PKTDMA supported by the
k3-udma driver.
The changes in PKTDMA V2 are:
- Autopair: There is no longer a need for PSIL pair and AUTOPAIR bit
needs to set in the RT_CTL register.
- Static channel mapping: Each channel is mapped to a single
peripheral.
- Direct IRQs: There is no INT-A and interrupt lines from DMA are
directly connected to GIC.
- Remote side configuration handled by DMA. So no need to write to
PEER registers to START / STOP / PAUSE / TEARDOWN.
Signed-off-by: Sai Sree Kartheek Adivi <s-adivi@ti.com>
---
drivers/dma/ti/k3-udma-common.c | 33 ++++-
drivers/dma/ti/k3-udma-v2.c | 219 ++++++++++++++++++++++++++++++--
drivers/dma/ti/k3-udma.h | 3 +
3 files changed, 235 insertions(+), 20 deletions(-)
diff --git a/drivers/dma/ti/k3-udma-common.c b/drivers/dma/ti/k3-udma-common.c
index 462ad17c74604..b3de76893149a 100644
--- a/drivers/dma/ti/k3-udma-common.c
+++ b/drivers/dma/ti/k3-udma-common.c
@@ -2103,6 +2103,7 @@ int setup_resources(struct udma_dev *ud)
ret = bcdma_setup_resources(ud);
break;
case DMA_TYPE_PKTDMA:
+ case DMA_TYPE_PKTDMA_V2:
ret = pktdma_setup_resources(ud);
break;
default:
@@ -2112,7 +2113,7 @@ int setup_resources(struct udma_dev *ud)
if (ret)
return ret;
- if (ud->match_data->type == DMA_TYPE_BCDMA_V2) {
+ if (ud->match_data->type >= DMA_TYPE_BCDMA_V2) {
ch_count = ud->bchan_cnt + ud->tchan_cnt;
if (ud->bchan_cnt)
ch_count -= bitmap_weight(ud->bchan_map, ud->bchan_cnt);
@@ -2157,7 +2158,7 @@ int setup_resources(struct udma_dev *ud)
break;
case DMA_TYPE_BCDMA_V2:
dev_info(dev,
- "Channels: %d (bchan: %u, chan: %u)\n",
+ "Channels: %d (bchan: %u, tchan + rchan: %u)\n",
ch_count,
ud->bchan_cnt - bitmap_weight(ud->bchan_map,
ud->bchan_cnt),
@@ -2173,6 +2174,13 @@ int setup_resources(struct udma_dev *ud)
ud->rchan_cnt - bitmap_weight(ud->rchan_map,
ud->rchan_cnt));
break;
+ case DMA_TYPE_PKTDMA_V2:
+ dev_info(dev,
+ "Channels: %d (tchan + rchan: %u)\n",
+ ch_count,
+ ud->chan_cnt - bitmap_weight(ud->chan_map,
+ ud->chan_cnt));
+ break;
default:
break;
}
@@ -2625,12 +2633,21 @@ int pktdma_setup_resources(struct udma_dev *ud)
ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt),
sizeof(unsigned long), GFP_KERNEL);
+ bitmap_zero(ud->tchan_map, ud->tchan_cnt);
ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans),
GFP_KERNEL);
- ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt),
- sizeof(unsigned long), GFP_KERNEL);
- ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans),
- GFP_KERNEL);
+ if (ud->match_data->type == DMA_TYPE_PKTDMA_V2) {
+ ud->rchan_map = ud->tchan_map;
+ ud->rchans = ud->tchans;
+ ud->chan_map = ud->tchan_map;
+ ud->chans = ud->tchans;
+ } else {
+ ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt),
+ sizeof(unsigned long), GFP_KERNEL);
+ bitmap_zero(ud->rchan_map, ud->rchan_cnt);
+ ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans),
+ GFP_KERNEL);
+ }
ud->rflow_in_use = devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt),
sizeof(unsigned long),
GFP_KERNEL);
@@ -2638,11 +2655,15 @@ int pktdma_setup_resources(struct udma_dev *ud)
GFP_KERNEL);
ud->tflow_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tflow_cnt),
sizeof(unsigned long), GFP_KERNEL);
+ bitmap_zero(ud->tflow_map, ud->tflow_cnt);
if (!ud->tchan_map || !ud->rchan_map || !ud->tflow_map || !ud->tchans ||
!ud->rchans || !ud->rflows || !ud->rflow_in_use)
return -ENOMEM;
+ if (ud->match_data->type == DMA_TYPE_PKTDMA_V2)
+ return 0;
+
/* Get resource ranges from tisci */
for (i = 0; i < RM_RANGE_LAST; i++) {
if (i == RM_RANGE_BCHAN)
diff --git a/drivers/dma/ti/k3-udma-v2.c b/drivers/dma/ti/k3-udma-v2.c
index 90b5ac5e00ead..1e7fc39a4600e 100644
--- a/drivers/dma/ti/k3-udma-v2.c
+++ b/drivers/dma/ti/k3-udma-v2.c
@@ -778,6 +778,147 @@ static int bcdma_v2_alloc_chan_resources(struct dma_chan *chan)
return ret;
}
+static int pktdma_v2_alloc_chan_resources(struct dma_chan *chan)
+{
+ struct udma_chan *uc = to_udma_chan(chan);
+ struct udma_dev *ud = to_udma_dev(chan->device);
+ u32 irq_ring_idx;
+ __be32 addr[2] = {0, 0};
+ struct of_phandle_args out_irq;
+ int ret;
+
+ /*
+ * Make sure that the completion is in a known state:
+ * No teardown, the channel is idle
+ */
+ reinit_completion(&uc->teardown_completed);
+ complete_all(&uc->teardown_completed);
+ uc->state = UDMA_CHAN_IS_IDLE;
+
+ switch (uc->config.dir) {
+ case DMA_MEM_TO_DEV:
+ /* Slave transfer synchronized - mem to dev (TX) trasnfer */
+ dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-DEV\n", __func__,
+ uc->id);
+
+ ret = udma_v2_alloc_tx_resources(uc);
+ if (ret) {
+ uc->config.remote_thread_id = -1;
+ return ret;
+ }
+
+ uc->config.src_thread = ud->psil_base + uc->tchan->id;
+ uc->config.dst_thread = uc->config.remote_thread_id;
+ uc->config.dst_thread |= K3_PSIL_DST_THREAD_ID_OFFSET;
+
+
+ irq_ring_idx = uc->config.mapped_channel_id;
+ break;
+ case DMA_DEV_TO_MEM:
+ /* Slave transfer synchronized - dev to mem (RX) trasnfer */
+ dev_dbg(uc->ud->dev, "%s: chan%d as DEV-to-MEM\n", __func__,
+ uc->id);
+
+ ret = udma_v2_alloc_rx_resources(uc);
+ if (ret) {
+ uc->config.remote_thread_id = -1;
+ return ret;
+ }
+
+ uc->config.src_thread = uc->config.remote_thread_id;
+ uc->config.dst_thread = (ud->psil_base + uc->rchan->id) |
+ K3_PSIL_DST_THREAD_ID_OFFSET;
+
+ irq_ring_idx = uc->config.mapped_channel_id;
+ udma_write(uc->rflow->reg_rt, UDMA_RX_FLOWRT_RFA, BIT(28));
+ break;
+ default:
+ /* Can not happen */
+ dev_err(uc->ud->dev, "%s: chan%d invalid direction (%u)\n",
+ __func__, uc->id, uc->config.dir);
+ return -EINVAL;
+ }
+
+ /* check if the channel configuration was successful */
+ if (ret)
+ goto err_res_free;
+
+ if (udma_is_chan_running(uc)) {
+ dev_warn(ud->dev, "chan%d: is running!\n", uc->id);
+ ud->udma_reset_chan(uc, false);
+ if (udma_is_chan_running(uc)) {
+ dev_err(ud->dev, "chan%d: won't stop!\n", uc->id);
+ ret = -EBUSY;
+ goto err_res_free;
+ }
+ }
+
+ uc->dma_dev = dmaengine_get_dma_device(chan);
+ uc->hdesc_pool = dma_pool_create(uc->name, uc->dma_dev,
+ uc->config.hdesc_size, ud->desc_align,
+ 0);
+ if (!uc->hdesc_pool) {
+ dev_err(ud->ddev.dev,
+ "Descriptor pool allocation failed\n");
+ uc->use_dma_pool = false;
+ ret = -ENOMEM;
+ goto err_res_free;
+ }
+
+ uc->use_dma_pool = true;
+
+ uc->psil_paired = true;
+
+ out_irq.np = dev_of_node(ud->dev);
+ out_irq.args_count = 1;
+ out_irq.args[0] = irq_ring_idx;
+ ret = of_irq_parse_raw(addr, &out_irq);
+ if (ret)
+ return ret;
+
+ uc->irq_num_ring = irq_create_of_mapping(&out_irq);
+
+ ret = devm_request_irq(ud->dev, uc->irq_num_ring, udma_v2_ring_irq_handler,
+ IRQF_TRIGGER_HIGH, uc->name, uc);
+
+ if (ret) {
+ dev_err(ud->dev, "chan%d: ring irq request failed\n", uc->id);
+ goto err_irq_free;
+ }
+
+ uc->irq_num_udma = 0;
+
+ udma_reset_rings(uc);
+
+ INIT_DELAYED_WORK_ONSTACK(&uc->tx_drain.work,
+ udma_check_tx_completion);
+
+ if (uc->tchan)
+ dev_dbg(ud->dev,
+ "chan%d: tchan%d, tflow%d, Remote thread: 0x%04x\n",
+ uc->id, uc->tchan->id, uc->tchan->tflow_id,
+ uc->config.remote_thread_id);
+ else if (uc->rchan)
+ dev_dbg(ud->dev,
+ "chan%d: rchan%d, rflow%d, Remote thread: 0x%04x\n",
+ uc->id, uc->rchan->id, uc->rflow->id,
+ uc->config.remote_thread_id);
+ return 0;
+
+err_irq_free:
+ uc->irq_num_ring = 0;
+err_res_free:
+ udma_free_tx_resources(uc);
+ udma_free_rx_resources(uc);
+
+ udma_reset_uchan(uc);
+
+ dma_pool_destroy(uc->hdesc_pool);
+ uc->use_dma_pool = false;
+
+ return ret;
+}
+
static enum dma_status udma_v2_tx_status(struct dma_chan *chan,
dma_cookie_t cookie,
struct dma_tx_state *txstate)
@@ -872,6 +1013,7 @@ static int udma_v2_resume(struct dma_chan *chan)
}
static struct platform_driver bcdma_v2_driver;
+static struct platform_driver pktdma_v2_driver;
static bool udma_v2_dma_filter_fn(struct dma_chan *chan, void *param)
{
@@ -881,7 +1023,8 @@ static bool udma_v2_dma_filter_fn(struct dma_chan *chan, void *param)
struct udma_chan *uc;
struct udma_dev *ud;
- if (chan->device->dev->driver != &bcdma_v2_driver.driver)
+ if (chan->device->dev->driver != &bcdma_v2_driver.driver &&
+ chan->device->dev->driver != &pktdma_v2_driver.driver)
return false;
uc = to_udma_chan(chan);
@@ -924,7 +1067,7 @@ static bool udma_v2_dma_filter_fn(struct dma_chan *chan, void *param)
ucc->notdpkt = ep_config->notdpkt;
ucc->ep_type = ep_config->ep_type;
- if ((ud->match_data->type == DMA_TYPE_BCDMA_V2) &&
+ if ((ud->match_data->type >= DMA_TYPE_BCDMA_V2) &&
ep_config->mapped_channel_id >= 0) {
ucc->mapped_channel_id = ep_config->mapped_channel_id;
ucc->default_flow_id = ep_config->default_flow_id;
@@ -1023,11 +1166,33 @@ static struct udma_match_data bcdma_v2_data = {
.rchan_cnt = 128,
};
+static struct udma_match_data pktdma_v2_data = {
+ .type = DMA_TYPE_PKTDMA_V2,
+ .psil_base = 0x1000,
+ .enable_memcpy_support = false, /* PKTDMA does not support MEM_TO_MEM */
+ .flags = UDMA_FLAGS_J7_CLASS,
+ .statictr_z_mask = GENMASK(23, 0),
+ .burst_size = {
+ TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES, /* Normal Channels */
+ 0, /* No H Channels */
+ 0, /* No UH Channels */
+ },
+ .tchan_cnt = 97,
+ .rchan_cnt = 97,
+ .chan_cnt = 97,
+ .tflow_cnt = 112,
+ .rflow_cnt = 112,
+};
+
static const struct of_device_id udma_of_match[] = {
{
.compatible = "ti,dmss-bcdma-v2",
.data = &bcdma_v2_data,
},
+ {
+ .compatible = "ti,dmss-pktdma-v2",
+ .data = &pktdma_v2_data,
+ },
{ /* Sentinel */ },
};
@@ -1050,15 +1215,22 @@ static int udma_v2_get_mmrs(struct platform_device *pdev, struct udma_dev *ud)
cap2 = udma_read(ud->mmrs[V2_MMR_GCFG], 0x28);
cap3 = udma_read(ud->mmrs[V2_MMR_GCFG], 0x2c);
- ud->bchan_cnt = ud->match_data->bchan_cnt;
- /* There are no tchan and rchan in BCDMA_V2.
+ /* There are no tchan and rchan in BCDMA_V2 and PKTDMA_V2.
* Duplicate chan as tchan and rchan to keep the common code
- * in k3-udma-common.c functional for BCDMA_V2.
+ * in k3-udma-common.c functional.
*/
- ud->chan_cnt = ud->match_data->chan_cnt;
- ud->tchan_cnt = ud->match_data->chan_cnt;
- ud->rchan_cnt = ud->match_data->chan_cnt;
- ud->rflow_cnt = ud->chan_cnt;
+ if (ud->match_data->type == DMA_TYPE_BCDMA_V2) {
+ ud->bchan_cnt = ud->match_data->bchan_cnt;
+ ud->chan_cnt = ud->match_data->chan_cnt;
+ ud->tchan_cnt = ud->match_data->chan_cnt;
+ ud->rchan_cnt = ud->match_data->chan_cnt;
+ ud->rflow_cnt = ud->chan_cnt;
+ } else if (ud->match_data->type == DMA_TYPE_PKTDMA_V2) {
+ ud->chan_cnt = ud->match_data->chan_cnt;
+ ud->tchan_cnt = ud->match_data->tchan_cnt;
+ ud->rchan_cnt = ud->match_data->rchan_cnt;
+ ud->rflow_cnt = ud->match_data->rflow_cnt;
+ }
for (i = 1; i < V2_MMR_LAST; i++) {
if (i == V2_MMR_BCHANRT && ud->bchan_cnt == 0)
@@ -1120,7 +1292,14 @@ static int udma_v2_probe(struct platform_device *pdev)
struct k3_ringacc_init_data ring_init_data = {0};
- ring_init_data.num_rings = ud->bchan_cnt + ud->chan_cnt;
+ if (ud->match_data->type == DMA_TYPE_BCDMA_V2) {
+ ring_init_data.num_rings = ud->bchan_cnt + ud->chan_cnt;
+ } else if (ud->match_data->type == DMA_TYPE_PKTDMA_V2) {
+ ring_init_data.num_rings = ud->rflow_cnt;
+
+ ud->rflow_rt = devm_platform_ioremap_resource_byname(pdev, "ringrt");
+ ring_init_data.base_rt = ud->rflow_rt;
+ }
ud->ringacc = k3_ringacc_dmarings_init(pdev, &ring_init_data);
@@ -1129,8 +1308,10 @@ static int udma_v2_probe(struct platform_device *pdev)
dma_cap_set(DMA_SLAVE, ud->ddev.cap_mask);
- dma_cap_set(DMA_CYCLIC, ud->ddev.cap_mask);
- ud->ddev.device_prep_dma_cyclic = udma_prep_dma_cyclic;
+ if (ud->match_data->type != DMA_TYPE_PKTDMA_V2) {
+ dma_cap_set(DMA_CYCLIC, ud->ddev.cap_mask);
+ ud->ddev.device_prep_dma_cyclic = udma_prep_dma_cyclic;
+ }
ud->ddev.device_config = udma_slave_config;
ud->ddev.device_prep_slave_sg = udma_prep_slave_sg;
@@ -1144,8 +1325,18 @@ static int udma_v2_probe(struct platform_device *pdev)
ud->ddev.dbg_summary_show = udma_dbg_summary_show;
#endif
- ud->ddev.device_alloc_chan_resources =
- bcdma_v2_alloc_chan_resources;
+ switch (ud->match_data->type) {
+ case DMA_TYPE_BCDMA_V2:
+ ud->ddev.device_alloc_chan_resources =
+ bcdma_v2_alloc_chan_resources;
+ break;
+ case DMA_TYPE_PKTDMA_V2:
+ ud->ddev.device_alloc_chan_resources =
+ pktdma_v2_alloc_chan_resources;
+ break;
+ default:
+ return -EINVAL;
+ }
ud->ddev.device_free_chan_resources = udma_free_chan_resources;
diff --git a/drivers/dma/ti/k3-udma.h b/drivers/dma/ti/k3-udma.h
index c054113640bf4..a112ce4186ca9 100644
--- a/drivers/dma/ti/k3-udma.h
+++ b/drivers/dma/ti/k3-udma.h
@@ -44,8 +44,11 @@
#define UDMA_RX_FLOW_ID_FW_OES_REG 0x80
#define UDMA_RX_FLOW_ID_FW_STATUS_REG 0x88
+#define UDMA_RX_FLOWRT_RFA 0x8
+
/* BCHANRT/TCHANRT/RCHANRT registers */
#define UDMA_CHAN_RT_CTL_REG 0x0
+#define UDMA_CHAN_RT_CFG_REG 0x4
#define UDMA_CHAN_RT_SWTRIG_REG 0x8
#define UDMA_CHAN_RT_STDATA_REG 0x80
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 8/8] dmaengine: ti: k3-udma-v2: Update glue layer to support PKTDMA V2
2025-04-28 7:20 [PATCH 0/8] dmaengine: ti: Add support for BCDMA v2 and PKTDMA v2 Sai Sree Kartheek Adivi
` (5 preceding siblings ...)
2025-04-28 7:20 ` [PATCH 7/8] dmaengine: ti: k3-udma-v2: Add support for PKTDMA V2 Sai Sree Kartheek Adivi
@ 2025-04-28 7:20 ` Sai Sree Kartheek Adivi
[not found] ` <20250428072032.946008-4-s-adivi@ti.com>
7 siblings, 0 replies; 17+ messages in thread
From: Sai Sree Kartheek Adivi @ 2025-04-28 7:20 UTC (permalink / raw)
To: peter.ujfalusi, vkoul, robh, krzk+dt, conor+dt, nm, ssantosh,
s-adivi, dmaengine, devicetree, linux-kernel, linux-arm-kernel,
praneeth, vigneshr, u-kumar1, a-chavda
Update glue layer to support PKTDMA V2 for non DMAengine users.
The updates include
- Handling absence of TISCI
- Direct IRQs
- Autopair: Lack of PSIL pair.
Signed-off-by: Sai Sree Kartheek Adivi <s-adivi@ti.com>
---
drivers/dma/ti/k3-udma-glue.c | 91 ++++++++++++++++++++++----------
drivers/dma/ti/k3-udma-private.c | 48 +++++++++++++++--
drivers/dma/ti/k3-udma.h | 2 +
3 files changed, 110 insertions(+), 31 deletions(-)
diff --git a/drivers/dma/ti/k3-udma-glue.c b/drivers/dma/ti/k3-udma-glue.c
index f87d244cc2d67..886d57dadacae 100644
--- a/drivers/dma/ti/k3-udma-glue.c
+++ b/drivers/dma/ti/k3-udma-glue.c
@@ -244,6 +244,9 @@ static int k3_udma_glue_cfg_tx_chn(struct k3_udma_glue_tx_channel *tx_chn)
const struct udma_tisci_rm *tisci_rm = tx_chn->common.tisci_rm;
struct ti_sci_msg_rm_udmap_tx_ch_cfg req;
+ if (!tisci_rm->tisci)
+ return 0;
+
memset(&req, 0, sizeof(req));
req.valid_params = TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID |
@@ -502,21 +505,26 @@ int k3_udma_glue_enable_tx_chn(struct k3_udma_glue_tx_channel *tx_chn)
{
int ret;
- ret = xudma_navss_psil_pair(tx_chn->common.udmax,
- tx_chn->common.src_thread,
- tx_chn->common.dst_thread);
- if (ret) {
- dev_err(tx_chn->common.dev, "PSI-L request err %d\n", ret);
- return ret;
- }
+ if (tx_chn->common.udmax->match_data->type == DMA_TYPE_PKTDMA_V2) {
+ xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_AUTOPAIR | UDMA_CHAN_RT_CTL_EN);
+ } else {
+ ret = xudma_navss_psil_pair(tx_chn->common.udmax,
+ tx_chn->common.src_thread,
+ tx_chn->common.dst_thread);
+ if (ret) {
+ dev_err(tx_chn->common.dev, "PSI-L request err %d\n", ret);
+ return ret;
+ }
- tx_chn->psil_paired = true;
+ tx_chn->psil_paired = true;
- xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_PEER_RT_EN_REG,
- UDMA_PEER_RT_EN_ENABLE);
+ xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_PEER_RT_EN_REG,
+ UDMA_PEER_RT_EN_ENABLE);
- xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG,
- UDMA_CHAN_RT_CTL_EN);
+ xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_EN);
+ }
k3_udma_glue_dump_tx_rt_chn(tx_chn, "txchn en");
return 0;
@@ -682,7 +690,6 @@ static int k3_udma_glue_cfg_rx_chn(struct k3_udma_glue_rx_channel *rx_chn)
TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID |
TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID;
- req.nav_id = tisci_rm->tisci_dev_id;
req.index = rx_chn->udma_rchan_id;
req.rx_fetch_size = rx_chn->common.hdesc_size >> 2;
/*
@@ -702,11 +709,18 @@ static int k3_udma_glue_cfg_rx_chn(struct k3_udma_glue_rx_channel *rx_chn)
req.rx_chan_type = TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR;
req.rx_atype = rx_chn->common.atype_asel;
+ if (!tisci_rm->tisci) {
+ // TODO: look at the chan settings
+ xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CFG_REG,
+ UDMA_CHAN_RT_CTL_TDOWN | UDMA_CHAN_RT_CTL_PAUSE);
+ return 0;
+ }
+
+ req.nav_id = tisci_rm->tisci_dev_id;
ret = tisci_rm->tisci_udmap_ops->rx_ch_cfg(tisci_rm->tisci, &req);
if (ret)
dev_err(rx_chn->common.dev, "rchan%d cfg failed %d\n",
- rx_chn->udma_rchan_id, ret);
-
+ rx_chn->udma_rchan_id, ret);
return ret;
}
@@ -755,8 +769,11 @@ static int k3_udma_glue_cfg_rx_flow(struct k3_udma_glue_rx_channel *rx_chn,
}
if (xudma_is_pktdma(rx_chn->common.udmax)) {
- rx_ringfdq_id = flow->udma_rflow_id +
+ if (tisci_rm->tisci)
+ rx_ringfdq_id = flow->udma_rflow_id +
xudma_get_rflow_ring_offset(rx_chn->common.udmax);
+ else
+ rx_ringfdq_id = flow->udma_rflow_id;
rx_ring_id = 0;
} else {
rx_ring_id = flow_cfg->ring_rxq_id;
@@ -803,6 +820,13 @@ static int k3_udma_glue_cfg_rx_flow(struct k3_udma_glue_rx_channel *rx_chn,
rx_ringfdq_id = k3_ringacc_get_ring_id(flow->ringrxfdq);
}
+ if (!tisci_rm->tisci) {
+ xudma_rflowrt_write(flow->udma_rflow, UDMA_RX_FLOWRT_RFA,
+ UDMA_CHAN_RT_CTL_TDOWN | UDMA_CHAN_RT_CTL_PAUSE);
+ rx_chn->flows_ready++;
+ return 0;
+ }
+
memset(&req, 0, sizeof(req));
req.valid_params =
@@ -1307,6 +1331,9 @@ int k3_udma_glue_rx_flow_enable(struct k3_udma_glue_rx_channel *rx_chn,
if (!rx_chn->remote)
return -EINVAL;
+ if (!tisci_rm->tisci)
+ return 0;
+
rx_ring_id = k3_ringacc_get_ring_id(flow->ringrx);
rx_ringfdq_id = k3_ringacc_get_ring_id(flow->ringrxfdq);
@@ -1348,6 +1375,9 @@ int k3_udma_glue_rx_flow_disable(struct k3_udma_glue_rx_channel *rx_chn,
if (!rx_chn->remote)
return -EINVAL;
+ if (!tisci_rm->tisci)
+ return 0;
+
memset(&req, 0, sizeof(req));
req.valid_params =
TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID |
@@ -1383,21 +1413,26 @@ int k3_udma_glue_enable_rx_chn(struct k3_udma_glue_rx_channel *rx_chn)
if (rx_chn->flows_ready < rx_chn->flow_num)
return -EINVAL;
- ret = xudma_navss_psil_pair(rx_chn->common.udmax,
- rx_chn->common.src_thread,
- rx_chn->common.dst_thread);
- if (ret) {
- dev_err(rx_chn->common.dev, "PSI-L request err %d\n", ret);
- return ret;
- }
+ if (rx_chn->common.udmax->match_data->type == DMA_TYPE_PKTDMA_V2) {
+ xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_AUTOPAIR | UDMA_CHAN_RT_CTL_EN);
+ } else {
+ ret = xudma_navss_psil_pair(rx_chn->common.udmax,
+ rx_chn->common.src_thread,
+ rx_chn->common.dst_thread);
+ if (ret) {
+ dev_err(rx_chn->common.dev, "PSI-L request err %d\n", ret);
+ return ret;
+ }
- rx_chn->psil_paired = true;
+ rx_chn->psil_paired = true;
- xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG,
- UDMA_CHAN_RT_CTL_EN);
+ xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_EN);
- xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_PEER_RT_EN_REG,
- UDMA_PEER_RT_EN_ENABLE);
+ xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_PEER_RT_EN_REG,
+ UDMA_PEER_RT_EN_ENABLE);
+ }
k3_udma_glue_dump_rx_rt_chn(rx_chn, "rxrt en");
return 0;
diff --git a/drivers/dma/ti/k3-udma-private.c b/drivers/dma/ti/k3-udma-private.c
index 05228bf000333..5fccb8d18c898 100644
--- a/drivers/dma/ti/k3-udma-private.c
+++ b/drivers/dma/ti/k3-udma-private.c
@@ -3,18 +3,28 @@
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
* Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
*/
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqdomain.h>
+#include <linux/interrupt.h>
#include <linux/of.h>
#include <linux/of_platform.h>
int xudma_navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_thread)
{
- return navss_psil_pair(ud, src_thread, dst_thread);
+ if (IS_ENABLED(CONFIG_TI_K3_UDMA))
+ return navss_psil_pair(ud, src_thread, dst_thread);
+
+ return 0;
}
EXPORT_SYMBOL(xudma_navss_psil_pair);
int xudma_navss_psil_unpair(struct udma_dev *ud, u32 src_thread, u32 dst_thread)
{
- return navss_psil_unpair(ud, src_thread, dst_thread);
+ if (IS_ENABLED(CONFIG_TI_K3_UDMA))
+ return navss_psil_unpair(ud, src_thread, dst_thread);
+
+ return 0;
}
EXPORT_SYMBOL(xudma_navss_psil_unpair);
@@ -159,15 +169,32 @@ void xudma_##res##rt_write(struct udma_##res *p, int reg, u32 val) \
EXPORT_SYMBOL(xudma_##res##rt_write)
XUDMA_RT_IO_FUNCTIONS(tchan);
XUDMA_RT_IO_FUNCTIONS(rchan);
+XUDMA_RT_IO_FUNCTIONS(rflow);
int xudma_is_pktdma(struct udma_dev *ud)
{
- return ud->match_data->type == DMA_TYPE_PKTDMA;
+ return (ud->match_data->type == DMA_TYPE_PKTDMA ||
+ ud->match_data->type == DMA_TYPE_PKTDMA_V2);
}
EXPORT_SYMBOL(xudma_is_pktdma);
int xudma_pktdma_tflow_get_irq(struct udma_dev *ud, int udma_tflow_id)
{
+ if (ud->match_data->type == DMA_TYPE_PKTDMA_V2) {
+ __be32 addr[2] = {0, 0};
+ struct of_phandle_args out_irq;
+ int ret;
+
+ out_irq.np = dev_of_node(ud->dev);
+ out_irq.args_count = 1;
+ out_irq.args[0] = udma_tflow_id;
+ ret = of_irq_parse_raw(addr, &out_irq);
+ if (ret)
+ return ret;
+
+ return irq_create_of_mapping(&out_irq);
+ }
+
const struct udma_oes_offsets *oes = &ud->soc_data->oes;
return msi_get_virq(ud->dev, udma_tflow_id + oes->pktdma_tchan_flow);
@@ -176,6 +203,21 @@ EXPORT_SYMBOL(xudma_pktdma_tflow_get_irq);
int xudma_pktdma_rflow_get_irq(struct udma_dev *ud, int udma_rflow_id)
{
+ if (ud->match_data->type == DMA_TYPE_PKTDMA_V2) {
+ __be32 addr[2] = {0, 0};
+ struct of_phandle_args out_irq;
+ int ret;
+
+ out_irq.np = dev_of_node(ud->dev);
+ out_irq.args_count = 1;
+ out_irq.args[0] = udma_rflow_id;
+ ret = of_irq_parse_raw(addr, &out_irq);
+ if (ret)
+ return ret;
+
+ return irq_create_of_mapping(&out_irq);
+ }
+
const struct udma_oes_offsets *oes = &ud->soc_data->oes;
return msi_get_virq(ud->dev, udma_rflow_id + oes->pktdma_rchan_flow);
diff --git a/drivers/dma/ti/k3-udma.h b/drivers/dma/ti/k3-udma.h
index a112ce4186ca9..b09a7339a6442 100644
--- a/drivers/dma/ti/k3-udma.h
+++ b/drivers/dma/ti/k3-udma.h
@@ -718,6 +718,8 @@ u32 xudma_rchanrt_read(struct udma_rchan *rchan, int reg);
void xudma_rchanrt_write(struct udma_rchan *rchan, int reg, u32 val);
bool xudma_rflow_is_gp(struct udma_dev *ud, int id);
int xudma_get_rflow_ring_offset(struct udma_dev *ud);
+u32 xudma_rflowrt_read(struct udma_rflow *rflow, int reg);
+void xudma_rflowrt_write(struct udma_rflow *rflow, int reg, u32 val);
int xudma_is_pktdma(struct udma_dev *ud);
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH 5/8] drivers: soc: ti: k3-ringacc: handle absence of tisci
2025-04-28 7:20 ` [PATCH 5/8] drivers: soc: ti: k3-ringacc: handle absence of tisci Sai Sree Kartheek Adivi
@ 2025-04-28 18:45 ` kernel test robot
2025-05-09 16:29 ` Péter Ujfalusi
1 sibling, 0 replies; 17+ messages in thread
From: kernel test robot @ 2025-04-28 18:45 UTC (permalink / raw)
To: Sai Sree Kartheek Adivi, peter.ujfalusi, vkoul, robh, krzk+dt,
conor+dt, nm, ssantosh, dmaengine, devicetree, linux-kernel,
linux-arm-kernel, praneeth, vigneshr, u-kumar1, a-chavda
Cc: llvm, oe-kbuild-all
Hi Sai,
kernel test robot noticed the following build warnings:
[auto build test WARNING on vkoul-dmaengine/next]
[also build test WARNING on linus/master v6.15-rc4]
[cannot apply to next-20250428]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Sai-Sree-Kartheek-Adivi/dt-bindings-dma-ti-Add-document-for-K3-BCDMA-V2/20250428-152616
base: https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git next
patch link: https://lore.kernel.org/r/20250428072032.946008-6-s-adivi%40ti.com
patch subject: [PATCH 5/8] drivers: soc: ti: k3-ringacc: handle absence of tisci
config: arm64-randconfig-001-20250428 (https://download.01.org/0day-ci/archive/20250429/202504290207.ct0tnV56-lkp@intel.com/config)
compiler: clang version 20.1.2 (https://github.com/llvm/llvm-project 58df0ef89dd64126512e4ee27b4ac3fd8ddf6247)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250429/202504290207.ct0tnV56-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202504290207.ct0tnV56-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/soc/ti/k3-ringacc.c:214: warning: Function parameter or struct member 'cfg' not described in 'k3_ring'
>> drivers/soc/ti/k3-ringacc.c:214: warning: Function parameter or struct member 'intr' not described in 'k3_ring'
vim +214 drivers/soc/ti/k3-ringacc.c
6b3da0b475b877 Peter Ujfalusi 2020-07-24 168
3277e8aa2504d9 Grygorii Strashko 2020-01-15 169 /**
3277e8aa2504d9 Grygorii Strashko 2020-01-15 170 * struct k3_ring - RA Ring descriptor
3277e8aa2504d9 Grygorii Strashko 2020-01-15 171 *
3277e8aa2504d9 Grygorii Strashko 2020-01-15 172 * @rt: Ring control/status registers
3277e8aa2504d9 Grygorii Strashko 2020-01-15 173 * @fifos: Ring queues registers
3277e8aa2504d9 Grygorii Strashko 2020-01-15 174 * @proxy: Ring Proxy Datapath registers
3277e8aa2504d9 Grygorii Strashko 2020-01-15 175 * @ring_mem_dma: Ring buffer dma address
3277e8aa2504d9 Grygorii Strashko 2020-01-15 176 * @ring_mem_virt: Ring buffer virt address
3277e8aa2504d9 Grygorii Strashko 2020-01-15 177 * @ops: Ring operations
3277e8aa2504d9 Grygorii Strashko 2020-01-15 178 * @size: Ring size in elements
3277e8aa2504d9 Grygorii Strashko 2020-01-15 179 * @elm_size: Size of the ring element
3277e8aa2504d9 Grygorii Strashko 2020-01-15 180 * @mode: Ring mode
3277e8aa2504d9 Grygorii Strashko 2020-01-15 181 * @flags: flags
50883affe17e11 Lee Jones 2020-11-21 182 * @state: Ring state
3277e8aa2504d9 Grygorii Strashko 2020-01-15 183 * @ring_id: Ring Id
3277e8aa2504d9 Grygorii Strashko 2020-01-15 184 * @parent: Pointer on struct @k3_ringacc
3277e8aa2504d9 Grygorii Strashko 2020-01-15 185 * @use_count: Use count for shared rings
3277e8aa2504d9 Grygorii Strashko 2020-01-15 186 * @proxy_id: RA Ring Proxy Id (only if @K3_RINGACC_RING_USE_PROXY)
8c42379e40e2db Peter Ujfalusi 2020-10-25 187 * @dma_dev: device to be used for DMA API (allocation, mapping)
d782298c6f6b85 Grygorii Strashko 2020-12-08 188 * @asel: Address Space Select value for physical addresses
3277e8aa2504d9 Grygorii Strashko 2020-01-15 189 */
3277e8aa2504d9 Grygorii Strashko 2020-01-15 190 struct k3_ring {
3277e8aa2504d9 Grygorii Strashko 2020-01-15 191 struct k3_ring_rt_regs __iomem *rt;
babdc2c3524293 Sai Sree Kartheek Adivi 2025-04-28 192 struct k3_ring_cfg_regs __iomem *cfg;
babdc2c3524293 Sai Sree Kartheek Adivi 2025-04-28 193 struct k3_ring_intr_regs __iomem *intr;
3277e8aa2504d9 Grygorii Strashko 2020-01-15 194 struct k3_ring_fifo_regs __iomem *fifos;
3277e8aa2504d9 Grygorii Strashko 2020-01-15 195 struct k3_ringacc_proxy_target_regs __iomem *proxy;
3277e8aa2504d9 Grygorii Strashko 2020-01-15 196 dma_addr_t ring_mem_dma;
3277e8aa2504d9 Grygorii Strashko 2020-01-15 197 void *ring_mem_virt;
d9483b44c94eba Christophe JAILLET 2024-07-09 198 const struct k3_ring_ops *ops;
3277e8aa2504d9 Grygorii Strashko 2020-01-15 199 u32 size;
3277e8aa2504d9 Grygorii Strashko 2020-01-15 200 enum k3_ring_size elm_size;
3277e8aa2504d9 Grygorii Strashko 2020-01-15 201 enum k3_ring_mode mode;
3277e8aa2504d9 Grygorii Strashko 2020-01-15 202 u32 flags;
3277e8aa2504d9 Grygorii Strashko 2020-01-15 203 #define K3_RING_FLAG_BUSY BIT(1)
3277e8aa2504d9 Grygorii Strashko 2020-01-15 204 #define K3_RING_FLAG_SHARED BIT(2)
d782298c6f6b85 Grygorii Strashko 2020-12-08 205 #define K3_RING_FLAG_REVERSE BIT(3)
6b3da0b475b877 Peter Ujfalusi 2020-07-24 206 struct k3_ring_state state;
3277e8aa2504d9 Grygorii Strashko 2020-01-15 207 u32 ring_id;
3277e8aa2504d9 Grygorii Strashko 2020-01-15 208 struct k3_ringacc *parent;
3277e8aa2504d9 Grygorii Strashko 2020-01-15 209 u32 use_count;
3277e8aa2504d9 Grygorii Strashko 2020-01-15 210 int proxy_id;
8c42379e40e2db Peter Ujfalusi 2020-10-25 211 struct device *dma_dev;
d782298c6f6b85 Grygorii Strashko 2020-12-08 212 u32 asel;
d782298c6f6b85 Grygorii Strashko 2020-12-08 213 #define K3_ADDRESS_ASEL_SHIFT 48
3277e8aa2504d9 Grygorii Strashko 2020-01-15 @214 };
3277e8aa2504d9 Grygorii Strashko 2020-01-15 215
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 6/8] dmaengine: ti: New driver for K3 BCDMA_V2
2025-04-28 7:20 ` [PATCH 6/8] dmaengine: ti: New driver for K3 BCDMA_V2 Sai Sree Kartheek Adivi
@ 2025-04-29 8:05 ` kernel test robot
2025-05-07 7:31 ` kernel test robot
1 sibling, 0 replies; 17+ messages in thread
From: kernel test robot @ 2025-04-29 8:05 UTC (permalink / raw)
To: Sai Sree Kartheek Adivi, peter.ujfalusi, vkoul, robh, krzk+dt,
conor+dt, nm, ssantosh, dmaengine, devicetree, linux-kernel,
linux-arm-kernel, praneeth, vigneshr, u-kumar1, a-chavda
Cc: Paul Gazzillo, Necip Fazil Yildiran, oe-kbuild-all
Hi Sai,
kernel test robot noticed the following build warnings:
[auto build test WARNING on vkoul-dmaengine/next]
[also build test WARNING on linus/master v6.15-rc4]
[cannot apply to next-20250428]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Sai-Sree-Kartheek-Adivi/dt-bindings-dma-ti-Add-document-for-K3-BCDMA-V2/20250428-152616
base: https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git next
patch link: https://lore.kernel.org/r/20250428072032.946008-7-s-adivi%40ti.com
patch subject: [PATCH 6/8] dmaengine: ti: New driver for K3 BCDMA_V2
config: arm64-kismet-CONFIG_TI_K3_RINGACC-CONFIG_TI_K3_UDMA_V2-0-0 (https://download.01.org/0day-ci/archive/20250429/202504291527.tCMC8UGh-lkp@intel.com/config)
reproduce: (https://download.01.org/0day-ci/archive/20250429/202504291527.tCMC8UGh-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202504291527.tCMC8UGh-lkp@intel.com/
kismet warnings: (new ones prefixed by >>)
>> kismet: WARNING: unmet direct dependencies detected for TI_K3_RINGACC when selected by TI_K3_UDMA_V2
WARNING: unmet direct dependencies detected for TI_K3_RINGACC
Depends on [n]: SOC_TI [=y] && (ARCH_K3 [=y] || COMPILE_TEST [=y]) && TI_SCI_INTA_IRQCHIP [=n]
Selected by [y]:
- TI_K3_UDMA_V2 [=y] && DMADEVICES [=y] && ARCH_K3 [=y]
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/8] dt-bindings: dma: ti: Add document for K3 BCDMA V2
2025-04-28 7:20 ` [PATCH 1/8] dt-bindings: dma: ti: Add document for K3 BCDMA V2 Sai Sree Kartheek Adivi
@ 2025-04-30 10:26 ` Krzysztof Kozlowski
0 siblings, 0 replies; 17+ messages in thread
From: Krzysztof Kozlowski @ 2025-04-30 10:26 UTC (permalink / raw)
To: Sai Sree Kartheek Adivi
Cc: peter.ujfalusi, vkoul, robh, krzk+dt, conor+dt, nm, ssantosh,
dmaengine, devicetree, linux-kernel, linux-arm-kernel, praneeth,
vigneshr, u-kumar1, a-chavda
On Mon, Apr 28, 2025 at 12:50:25PM GMT, Sai Sree Kartheek Adivi wrote:
> New binding document for
> Texas Instruments K3 Block Copy DMA (BCDMA) V2.
>
> BCDMA V2 is introduced as part of AM62L.
>
> Signed-off-by: Sai Sree Kartheek Adivi <s-adivi@ti.com>
> ---
> .../bindings/dma/ti/k3-bcdma-v2.yaml | 97 +++++++++++++++++++
> 1 file changed, 97 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/dma/ti/k3-bcdma-v2.yaml
>
> diff --git a/Documentation/devicetree/bindings/dma/ti/k3-bcdma-v2.yaml b/Documentation/devicetree/bindings/dma/ti/k3-bcdma-v2.yaml
> new file mode 100644
> index 0000000000000..af4aa3839fd66
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/ti/k3-bcdma-v2.yaml
> @@ -0,0 +1,97 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (C) 2024-2025 Texas Instruments Incorporated
> +# Author: Sai Sree Kartheek Adivi <s-adivi@ti.com>
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/dma/ti/k3-bcdma-v2.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Texas Instruments K3 DMSS BCDMA V2
> +
> +maintainers:
> + - Sai Sree Kartheek Adivi <s-adivi@ti.com>
> +
> +description: |
> + The BCDMA V2 is intended to perform similar functions as the TR
> + mode channels of K3 UDMA-P.
> + BCDMA V2 includes block copy channels and Split channels.
> +
> + Block copy channels mainly used for memory to memory transfers, but with
> + optional triggers a block copy channel can service peripherals by accessing
> + directly to memory mapped registers or area.
> +
> + Split channels can be used to service PSI-L based peripherals.
> + The peripherals can be PSI-L native or legacy, non PSI-L native peripherals
> + with PDMAs. PDMA is tasked to act as a bridge between the PSI-L fabric and the
> + legacy peripheral.
> +
> +allOf:
> + - $ref: /schemas/dma/dma-controller.yaml#
> +
> +properties:
> + compatible:
> + const: ti,dmss-bcdma-v2
SoC compatibles instead.
> +
> + reg:
> + items:
> + - description: BCDMA Control /Status Registers region
s/Registers region//
> + - description: Block Copy Channel Realtime Registers region
> + - description: Channel Realtime Registers region
> + - description: Ring Realtime Registers region
> +
> + reg-names:
> + items:
> + - const: gcfg
> + - const: bchanrt
> + - const: chanrt
> + - const: ringrt
> +
> + "#dma-cells":
> + const: 4
> + description: |
> + cell 1: Trigger type for the channel
> + 0 - disable / no trigger
> + 1 - internal channel event
> + 2 - external signal
> + 3 - timer manager event
> +
> + cell 2: parameter for the trigger:
> + if cell 1 is 0 (disable / no trigger):
> + Unused, ignored
> + if cell 1 is 1 (internal channel event):
> + channel number whose TR event should trigger the current channel.
> + if cell 1 is 2 or 3 (external signal or timer manager event):
> + index of global interfaces that come into the DMA.
> +
> + Please refer to the device documentation for global interface indexes.
> +
> + cell 3: Channel number for the peripheral
> +
> + Please refer to the device documentation for the channel map.
> +
> + cell 4: ASEL value for the channel
> +
> +required:
> + - compatible
> + - "#dma-cells"
> + - reg
> + - reg-names
Keep same order as in properties: block.
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |+
Drop +
> + cbass_main {
Follow DTS coding style... or just make it like all other SoC bindings.
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + main_bcdma: dma-controller@485c4000 {
Messed indentation.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 2/8] dt-bindings: dma: ti: Add document for K3 PKTDMA V2
2025-04-28 7:20 ` [PATCH 2/8] dt-bindings: dma: ti: Add document for K3 PKTDMA V2 Sai Sree Kartheek Adivi
@ 2025-04-30 10:26 ` Krzysztof Kozlowski
0 siblings, 0 replies; 17+ messages in thread
From: Krzysztof Kozlowski @ 2025-04-30 10:26 UTC (permalink / raw)
To: Sai Sree Kartheek Adivi
Cc: peter.ujfalusi, vkoul, robh, krzk+dt, conor+dt, nm, ssantosh,
dmaengine, devicetree, linux-kernel, linux-arm-kernel, praneeth,
vigneshr, u-kumar1, a-chavda
On Mon, Apr 28, 2025 at 12:50:26PM GMT, Sai Sree Kartheek Adivi wrote:
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |+
> + cbass_main {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
Same comments.
> + main_pktdma: dma-controller@485c0000 {
Also, drop unused label.
> + compatible = "ti,dmss-pktdma-v2";
> + reg = <0x00 0x485c0000 0x00 0x4000>,
> + <0x00 0x48900000 0x00 0x80000>,
> + <0x00 0x47200000 0x00 0x100000>;
> + reg-names = "gcfg", "chanrt", "ringrt";
> + #dma-cells = <2>;
> + };
> + };
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 3/8] drivers: dma: ti: Refactor TI K3 UDMA driver
[not found] ` <20250428072032.946008-4-s-adivi@ti.com>
@ 2025-04-30 10:28 ` Krzysztof Kozlowski
2025-05-09 14:25 ` Péter Ujfalusi
1 sibling, 0 replies; 17+ messages in thread
From: Krzysztof Kozlowski @ 2025-04-30 10:28 UTC (permalink / raw)
To: Sai Sree Kartheek Adivi
Cc: peter.ujfalusi, vkoul, robh, krzk+dt, conor+dt, nm, ssantosh,
dmaengine, devicetree, linux-kernel, linux-arm-kernel, praneeth,
vigneshr, u-kumar1, a-chavda
On Mon, Apr 28, 2025 at 12:50:27PM GMT, Sai Sree Kartheek Adivi wrote:
> Refactors and split the driver into common and device
> specific parts. There are no functional changes.
>
> Signed-off-by: Sai Sree Kartheek Adivi <s-adivi@ti.com>
Keep consistent subject prefixes, not random choices.
> ---
> drivers/dma/ti/Makefile | 2 +-
> drivers/dma/ti/k3-udma-common.c | 2909 ++++++++++++++++++++++++
> drivers/dma/ti/k3-udma.c | 3751 ++-----------------------------
That's way more removals than addons... Not sure how this can be easily
reviewed...
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 6/8] dmaengine: ti: New driver for K3 BCDMA_V2
2025-04-28 7:20 ` [PATCH 6/8] dmaengine: ti: New driver for K3 BCDMA_V2 Sai Sree Kartheek Adivi
2025-04-29 8:05 ` kernel test robot
@ 2025-05-07 7:31 ` kernel test robot
1 sibling, 0 replies; 17+ messages in thread
From: kernel test robot @ 2025-05-07 7:31 UTC (permalink / raw)
To: Sai Sree Kartheek Adivi, peter.ujfalusi, vkoul, robh, krzk+dt,
conor+dt, nm, ssantosh, dmaengine, devicetree, linux-kernel,
linux-arm-kernel, praneeth, vigneshr, u-kumar1, a-chavda
Cc: llvm, oe-kbuild-all
Hi Sai,
kernel test robot noticed the following build warnings:
[auto build test WARNING on vkoul-dmaengine/next]
[also build test WARNING on linus/master v6.15-rc5]
[cannot apply to next-20250506]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Sai-Sree-Kartheek-Adivi/dt-bindings-dma-ti-Add-document-for-K3-BCDMA-V2/20250428-152616
base: https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git next
patch link: https://lore.kernel.org/r/20250428072032.946008-7-s-adivi%40ti.com
patch subject: [PATCH 6/8] dmaengine: ti: New driver for K3 BCDMA_V2
config: arm64-allmodconfig (https://download.01.org/0day-ci/archive/20250507/202505071527.yZZNwWXf-lkp@intel.com/config)
compiler: clang version 19.1.7 (https://github.com/llvm/llvm-project cd708029e0b2869e80abe31ddb175f7c35361f90)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250507/202505071527.yZZNwWXf-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202505071527.yZZNwWXf-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/dma/ti/k3-udma-v2.c:147:14: warning: variable 'ret' set but not used [-Wunused-but-set-variable]
147 | int status, ret;
| ^
>> drivers/dma/ti/k3-udma-v2.c:1042:6: warning: variable 'cap2' set but not used [-Wunused-but-set-variable]
1042 | u32 cap2, cap3;
| ^
>> drivers/dma/ti/k3-udma-v2.c:1042:12: warning: variable 'cap3' set but not used [-Wunused-but-set-variable]
1042 | u32 cap2, cap3;
| ^
3 warnings generated.
vim +/ret +147 drivers/dma/ti/k3-udma-v2.c
142
143 static int udma_v2_start(struct udma_chan *uc)
144 {
145 struct virt_dma_desc *vd = vchan_next_desc(&uc->vc);
146 struct udma_dev *ud = uc->ud;
> 147 int status, ret;
148
149 if (!vd) {
150 uc->desc = NULL;
151 return -ENOENT;
152 }
153
154 list_del(&vd->node);
155
156 uc->desc = to_udma_desc(&vd->tx);
157
158 /* Channel is already running and does not need reconfiguration */
159 if (udma_is_chan_running(uc) && !udma_chan_needs_reconfiguration(uc)) {
160 udma_start_desc(uc);
161 goto out;
162 }
163
164 /* Make sure that we clear the teardown bit, if it is set */
165 ud->udma_reset_chan(uc, false);
166
167 /* Push descriptors before we start the channel */
168 udma_start_desc(uc);
169
170 switch (uc->desc->dir) {
171 case DMA_DEV_TO_MEM:
172 /* Config remote TR */
173 if (uc->config.ep_type == PSIL_EP_PDMA_XY) {
174 u32 val = PDMA_STATIC_TR_Y(uc->desc->static_tr.elcnt) |
175 PDMA_STATIC_TR_X(uc->desc->static_tr.elsize);
176 const struct udma_match_data *match_data =
177 uc->ud->match_data;
178
179 if (uc->config.enable_acc32)
180 val |= PDMA_STATIC_TR_XY_ACC32;
181 if (uc->config.enable_burst)
182 val |= PDMA_STATIC_TR_XY_BURST;
183
184 udma_chanrt_write(uc,
185 UDMA_CHAN_RT_STATIC_TR_XY_REG,
186 val);
187
188 udma_chanrt_write(uc,
189 UDMA_CHAN_RT_STATIC_TR_Z_REG,
190 PDMA_STATIC_TR_Z(uc->desc->static_tr.bstcnt,
191 match_data->statictr_z_mask));
192
193 /* save the current staticTR configuration */
194 memcpy(&uc->static_tr, &uc->desc->static_tr,
195 sizeof(uc->static_tr));
196 }
197
198 udma_chanrt_write(uc, UDMA_CHAN_RT_CTL_REG,
199 UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_AUTOPAIR);
200
201 /* Poll for autopair completion */
202 ret = read_poll_timeout_atomic(udma_v2_check_chan_autopair_completion,
203 status, status != 0, 100, 500, false, uc);
204
205 if (status <= 0)
206 return -ETIMEDOUT;
207
208 break;
209 case DMA_MEM_TO_DEV:
210 /* Config remote TR */
211 if (uc->config.ep_type == PSIL_EP_PDMA_XY) {
212 u32 val = PDMA_STATIC_TR_Y(uc->desc->static_tr.elcnt) |
213 PDMA_STATIC_TR_X(uc->desc->static_tr.elsize);
214
215 if (uc->config.enable_acc32)
216 val |= PDMA_STATIC_TR_XY_ACC32;
217 if (uc->config.enable_burst)
218 val |= PDMA_STATIC_TR_XY_BURST;
219
220 udma_chanrt_write(uc,
221 UDMA_CHAN_RT_STATIC_TR_XY_REG,
222 val);
223
224 /* save the current staticTR configuration */
225 memcpy(&uc->static_tr, &uc->desc->static_tr,
226 sizeof(uc->static_tr));
227 }
228
229 udma_chanrt_write(uc, UDMA_CHAN_RT_CTL_REG,
230 UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_AUTOPAIR);
231
232 /* Poll for autopair completion */
233 ret = read_poll_timeout_atomic(udma_v2_check_chan_autopair_completion,
234 status, status != 0, 100, 500, false, uc);
235
236 if (status <= 0)
237 return -ETIMEDOUT;
238
239 break;
240 case DMA_MEM_TO_MEM:
241 udma_bchanrt_write(uc, UDMA_CHAN_RT_CTL_REG,
242 UDMA_CHAN_RT_CTL_EN);
243 udma_bchanrt_write(uc, UDMA_CHAN_RT_CTL_REG,
244 UDMA_CHAN_RT_CTL_EN);
245
246 break;
247 default:
248 return -EINVAL;
249 }
250
251 uc->state = UDMA_CHAN_IS_ACTIVE;
252 out:
253
254 return 0;
255 }
256
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 3/8] drivers: dma: ti: Refactor TI K3 UDMA driver
[not found] ` <20250428072032.946008-4-s-adivi@ti.com>
2025-04-30 10:28 ` [PATCH 3/8] drivers: dma: ti: Refactor TI K3 UDMA driver Krzysztof Kozlowski
@ 2025-05-09 14:25 ` Péter Ujfalusi
2025-05-28 10:29 ` Adivi, Sai Sree Kartheek
1 sibling, 1 reply; 17+ messages in thread
From: Péter Ujfalusi @ 2025-05-09 14:25 UTC (permalink / raw)
To: Sai Sree Kartheek Adivi, vkoul, robh, krzk+dt, conor+dt, nm,
ssantosh, dmaengine, devicetree, linux-kernel, linux-arm-kernel,
praneeth, vigneshr, u-kumar1, a-chavda
Hi,
On 28/04/2025 10:20, Sai Sree Kartheek Adivi wrote:
> Refactors and split the driver into common and device
> specific parts. There are no functional changes.
>
> Signed-off-by: Sai Sree Kartheek Adivi <s-adivi@ti.com>
> ---
> drivers/dma/ti/Makefile | 2 +-
> drivers/dma/ti/k3-udma-common.c | 2909 ++++++++++++++++++++++++
> drivers/dma/ti/k3-udma.c | 3751 ++-----------------------------
I'm affraid you do need to break this one up a bit. It might be doing it
correctly, but it is impossible to check with the churn, like ....
> drivers/dma/ti/k3-udma.h | 548 ++++-
> 4 files changed, 3700 insertions(+), 3510 deletions(-)
> create mode 100644 drivers/dma/ti/k3-udma-common.c
...
> -static bool udma_is_chan_running(struct udma_chan *uc)
> -{
> - u32 trt_ctl = 0;
> - u32 rrt_ctl = 0;
> -
> - if (uc->tchan)
> - trt_ctl = udma_tchanrt_read(uc, UDMA_CHAN_RT_CTL_REG);
> - if (uc->rchan)
> - rrt_ctl = udma_rchanrt_read(uc, UDMA_CHAN_RT_CTL_REG);
> -
> - if (trt_ctl & UDMA_CHAN_RT_CTL_EN || rrt_ctl & UDMA_CHAN_RT_CTL_EN)
> - return true;
> -
> - return false;
> -}
> -
> static bool udma_is_chan_paused(struct udma_chan *uc)
> {
> u32 val, pause_mask;
> @@ -643,189 +88,73 @@ static bool udma_is_chan_paused(struct udma_chan *uc)
> return false;
> }
>
> -static inline dma_addr_t udma_get_rx_flush_hwdesc_paddr(struct udma_chan *uc)
> +static void udma_decrement_byte_counters(struct udma_chan *uc, u32 val)
These sort of diffs.
> {
> - return uc->ud->rx_flush.hwdescs[uc->config.pkt_mode].cppi5_desc_paddr;
> + if (uc->desc->dir == DMA_DEV_TO_MEM) {
> + udma_rchanrt_write(uc, UDMA_CHAN_RT_BCNT_REG, val);
> + udma_rchanrt_write(uc, UDMA_CHAN_RT_SBCNT_REG, val);
> + if (uc->config.ep_type != PSIL_EP_NATIVE)
> + udma_rchanrt_write(uc, UDMA_CHAN_RT_PEER_BCNT_REG, val);
> + } else {
> + udma_tchanrt_write(uc, UDMA_CHAN_RT_BCNT_REG, val);
> + udma_tchanrt_write(uc, UDMA_CHAN_RT_SBCNT_REG, val);
> + if (!uc->bchan && uc->config.ep_type != PSIL_EP_NATIVE)
> + udma_tchanrt_write(uc, UDMA_CHAN_RT_PEER_BCNT_REG, val);
> + }
> }
>
> -static int udma_push_to_ring(struct udma_chan *uc, int idx)
> +static void udma_reset_counters(struct udma_chan *uc)
> {
...
> +struct udma_dev {
> + struct dma_device ddev;
> + struct device *dev;
> + void __iomem *mmrs[MMR_LAST];
> + const struct udma_match_data *match_data;
> + const struct udma_soc_data *soc_data;
> +
> + struct udma_tpl bchan_tpl;
> + struct udma_tpl tchan_tpl;
> + struct udma_tpl rchan_tpl;
> +
> + size_t desc_align; /* alignment to use for descriptors */
> +
> + struct udma_tisci_rm tisci_rm;
> +
> + struct k3_ringacc *ringacc;
> +
> + struct work_struct purge_work;
> + struct list_head desc_to_purge;
> + spinlock_t lock;
> +
> + struct udma_rx_flush rx_flush;
> +
> + int bchan_cnt;
> + int tchan_cnt;
> + int echan_cnt;
> + int rchan_cnt;
> + int rflow_cnt;
> + int tflow_cnt;
> + unsigned long *bchan_map;
> + unsigned long *tchan_map;
> + unsigned long *rchan_map;
> + unsigned long *rflow_gp_map;
> + unsigned long *rflow_gp_map_allocated;
> + unsigned long *rflow_in_use;
> + unsigned long *tflow_map;
> +
> + struct udma_bchan *bchans;
> + struct udma_tchan *tchans;
> + struct udma_rchan *rchans;
> + struct udma_rflow *rflows;
> +
> + struct udma_chan *channels;
> + u32 psil_base;
> + u32 atype;
> + u32 asel;
> +
> + int (*udma_start)(struct udma_chan *uc);
> + int (*udma_stop)(struct udma_chan *uc);
> + int (*udma_reset_chan)(struct udma_chan *uc, bool hard);
> + bool (*udma_is_desc_really_done)(struct udma_chan *uc, struct udma_desc *d);
> + void (*udma_decrement_byte_counters)(struct udma_chan *uc, u32 val);
You can drop the udma_ prefix, it is clear that they are for udma..
> +};
--
Péter
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 5/8] drivers: soc: ti: k3-ringacc: handle absence of tisci
2025-04-28 7:20 ` [PATCH 5/8] drivers: soc: ti: k3-ringacc: handle absence of tisci Sai Sree Kartheek Adivi
2025-04-28 18:45 ` kernel test robot
@ 2025-05-09 16:29 ` Péter Ujfalusi
1 sibling, 0 replies; 17+ messages in thread
From: Péter Ujfalusi @ 2025-05-09 16:29 UTC (permalink / raw)
To: Sai Sree Kartheek Adivi, vkoul, robh, krzk+dt, conor+dt, nm,
ssantosh, dmaengine, devicetree, linux-kernel, linux-arm-kernel,
praneeth, vigneshr, u-kumar1, a-chavda
On 28/04/2025 10:20, Sai Sree Kartheek Adivi wrote:
> Handle absence of tisci with direct register writes. This will support
> platforms that do not have tisci firmware like AM62L.
>
> Signed-off-by: Sai Sree Kartheek Adivi <s-adivi@ti.com>
> ---
> drivers/soc/ti/k3-ringacc.c | 162 +++++++++++++++++++++++++-----
> include/linux/soc/ti/k3-ringacc.h | 4 +
> 2 files changed, 142 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/soc/ti/k3-ringacc.c b/drivers/soc/ti/k3-ringacc.c
> index 82a15cad1c6c4..49e0483676a14 100644
> --- a/drivers/soc/ti/k3-ringacc.c
> +++ b/drivers/soc/ti/k3-ringacc.c
> @@ -45,6 +45,38 @@ struct k3_ring_rt_regs {
> u32 hwindx;
> };
>
> +#define K3_RINGACC_RT_CFG_REGS_OFS 0x40
> +#define K3_DMARING_CFG_ADDR_HI_MASK GENMASK(3, 0)
> +#define K3_DMARING_CFG_ASEL_SHIFT 16
> +#define K3_DMARING_CFG_SIZE_MASK GENMASK(15, 0)
> +
> +/**
> + * struct k3_ring_cfg_regs - The RA Configuration Registers region
> + *
> + * @ba_lo: Ring Base Address Low Register
> + * @ba_hi: Ring Base Address High Register
> + * @size: Ring Size Register
> + */
> +struct k3_ring_cfg_regs {
> + u32 ba_lo;
> + u32 ba_hi;
> + u32 size;
> +};
> +
> +#define K3_RINGACC_RT_INT_REGS_OFS 0x140
> +#define K3_RINGACC_RT_INT_ENABLE_SET_COMPLETE BIT(0)
> +#define K3_RINGACC_RT_INT_ENABLE_SET_TR BIT(2)
> +
> +struct k3_ring_intr_regs {
> + u32 enable_set;
> + u32 resv_4;
> + u32 clr;
> + u32 resv_16;
> + u32 status_set;
> + u32 resv_8;
> + u32 status;
> +};
> +
> #define K3_RINGACC_RT_REGS_STEP 0x1000
> #define K3_DMARING_RT_REGS_STEP 0x2000
> #define K3_DMARING_RT_REGS_REVERSE_OFS 0x1000
> @@ -157,6 +189,8 @@ struct k3_ring_state {
> */
> struct k3_ring {
> struct k3_ring_rt_regs __iomem *rt;
> + struct k3_ring_cfg_regs __iomem *cfg;
> + struct k3_ring_intr_regs __iomem *intr;
> struct k3_ring_fifo_regs __iomem *fifos;
> struct k3_ringacc_proxy_target_regs __iomem *proxy;
> dma_addr_t ring_mem_dma;
> @@ -465,16 +499,30 @@ static void k3_ringacc_ring_reset_sci(struct k3_ring *ring)
> struct ti_sci_msg_rm_ring_cfg ring_cfg = { 0 };
> struct k3_ringacc *ringacc = ring->parent;
> int ret;
> + u32 reg;
>
> - ring_cfg.nav_id = ringacc->tisci_dev_id;
> - ring_cfg.index = ring->ring_id;
> - ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID;
> - ring_cfg.count = ring->size;
> + if (!ringacc->tisci) {
these are not in hot path, right?
The reg can be moved here and in other functions.
> + if (ring->cfg == NULL)
> + return;
> + reg = readl(&ring->cfg->size);
> + reg &= ~K3_DMARING_CFG_SIZE_MASK;
>
> - ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
> - if (ret)
> - dev_err(ringacc->dev, "TISCI reset ring fail (%d) ring_idx %d\n",
> - ret, ring->ring_id);
> + writel(reg, &ring->cfg->size);
> + wmb();
> + reg |= ring->size;
> +
> + writel(reg, &ring->cfg->size);
> + } else {
> + ring_cfg.nav_id = ringacc->tisci_dev_id;
> + ring_cfg.index = ring->ring_id;
> + ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID;
> + ring_cfg.count = ring->size;
> +
> + ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
> + if (ret)
> + dev_err(ringacc->dev, "TISCI reset ring fail (%d) ring_idx %d\n",
> + ret, ring->ring_id);
> + }
> }
>
> void k3_ringacc_ring_reset(struct k3_ring *ring)
> @@ -494,16 +542,30 @@ static void k3_ringacc_ring_reconfig_qmode_sci(struct k3_ring *ring,
> struct ti_sci_msg_rm_ring_cfg ring_cfg = { 0 };
> struct k3_ringacc *ringacc = ring->parent;
> int ret;
> + u32 reg;
>
> ring_cfg.nav_id = ringacc->tisci_dev_id;
> ring_cfg.index = ring->ring_id;
> ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_RING_MODE_VALID;
> ring_cfg.mode = mode;
>
> - ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
> - if (ret)
> - dev_err(ringacc->dev, "TISCI reconf qmode fail (%d) ring_idx %d\n",
> - ret, ring->ring_id);
> + if (!ringacc->tisci) {
> + writel(ring_cfg.addr_lo, &ring->cfg->ba_lo);
> + writel((ring_cfg.addr_hi & K3_DMARING_CFG_ADDR_HI_MASK) +
> + (ring_cfg.asel << K3_DMARING_CFG_ASEL_SHIFT),
> + &ring->cfg->ba_hi);
> +
> + reg = readl(&ring->cfg->size);
> + reg &= ~K3_DMARING_CFG_SIZE_MASK;
> + reg |= ring_cfg.count & K3_DMARING_CFG_SIZE_MASK;
> +
> + writel(reg, &ring->cfg->size);
> + } else {
> + ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
> + if (ret)
> + dev_err(ringacc->dev, "TISCI reconf qmode fail (%d) ring_idx %d\n",
> + ret, ring->ring_id);
> + }
> }
>
> void k3_ringacc_ring_reset_dma(struct k3_ring *ring, u32 occ)
> @@ -570,15 +632,29 @@ static void k3_ringacc_ring_free_sci(struct k3_ring *ring)
> struct ti_sci_msg_rm_ring_cfg ring_cfg = { 0 };
> struct k3_ringacc *ringacc = ring->parent;
> int ret;
> + u32 reg;
this can be added to if (!ringacc->tisci) { } scope.>
> ring_cfg.nav_id = ringacc->tisci_dev_id;
> ring_cfg.index = ring->ring_id;
> ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER;
>
> - ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
> - if (ret)
> - dev_err(ringacc->dev, "TISCI ring free fail (%d) ring_idx %d\n",
> - ret, ring->ring_id);
> + if (!ringacc->tisci) {
> + writel(ring_cfg.addr_lo, &ring->cfg->ba_lo);
> + writel((ring_cfg.addr_hi & K3_DMARING_CFG_ADDR_HI_MASK) +
> + (ring_cfg.asel << K3_DMARING_CFG_ASEL_SHIFT),
> + &ring->cfg->ba_hi);
> +
> + reg = readl(&ring->cfg->size);
> + reg &= ~K3_DMARING_CFG_SIZE_MASK;
> + reg |= ring_cfg.count & K3_DMARING_CFG_SIZE_MASK;
> +
> + writel(reg, &ring->cfg->size);
> + } else {
> + ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
> + if (ret)
> + dev_err(ringacc->dev, "TISCI ring free fail (%d) ring_idx %d\n",
> + ret, ring->ring_id);
> + }
> }
>
> int k3_ringacc_ring_free(struct k3_ring *ring)
> @@ -669,15 +745,31 @@ int k3_ringacc_get_ring_irq_num(struct k3_ring *ring)
> }
> EXPORT_SYMBOL_GPL(k3_ringacc_get_ring_irq_num);
>
> +u32 k3_ringacc_ring_get_irq_status(struct k3_ring *ring)
> +{
> + struct k3_ringacc *ringacc = ring->parent;
> + struct k3_ring *ring2 = &ringacc->rings[ring->ring_id];
> +
> + return readl(&ring2->intr->status);
> +}
> +EXPORT_SYMBOL_GPL(k3_ringacc_ring_get_irq_status);
> +
> +void k3_ringacc_ring_clear_irq(struct k3_ring *ring)
> +{
> + struct k3_ringacc *ringacc = ring->parent;
> + struct k3_ring *ring2 = &ringacc->rings[ring->ring_id];
> +
> + writel(0xFF, &ring2->intr->status);
> +}
> +EXPORT_SYMBOL_GPL(k3_ringacc_ring_clear_irq);
> +
> static int k3_ringacc_ring_cfg_sci(struct k3_ring *ring)
> {
> struct ti_sci_msg_rm_ring_cfg ring_cfg = { 0 };
> struct k3_ringacc *ringacc = ring->parent;
> + u32 reg;
> int ret;
>
> - if (!ringacc->tisci)
> - return -EINVAL;
> -
> ring_cfg.nav_id = ringacc->tisci_dev_id;
> ring_cfg.index = ring->ring_id;
> ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER;
> @@ -688,11 +780,26 @@ static int k3_ringacc_ring_cfg_sci(struct k3_ring *ring)
> ring_cfg.size = ring->elm_size;
> ring_cfg.asel = ring->asel;
>
> + if (!ringacc->tisci) {
> + writel(ring_cfg.addr_lo, &ring->cfg->ba_lo);
> + writel((ring_cfg.addr_hi & K3_DMARING_CFG_ADDR_HI_MASK) +
> + (ring_cfg.asel << K3_DMARING_CFG_ASEL_SHIFT),
> + &ring->cfg->ba_hi);
> +
> + reg = readl(&ring->cfg->size);
> + reg &= ~K3_DMARING_CFG_SIZE_MASK;
> + reg |= ring_cfg.count & K3_DMARING_CFG_SIZE_MASK;
> +
> + writel(reg, &ring->cfg->size);
> + writel(K3_RINGACC_RT_INT_ENABLE_SET_COMPLETE | K3_RINGACC_RT_INT_ENABLE_SET_TR,
> + &ring->intr->enable_set);
> + return 0;
> + }
> +
> ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
> if (ret)
> dev_err(ringacc->dev, "TISCI config ring fail (%d) ring_idx %d\n",
> - ret, ring->ring_id);
> -
> + ret, ring->ring_id);
suprious change? The alignment was correct.
> return ret;
> }
>
> @@ -1480,9 +1587,12 @@ struct k3_ringacc *k3_ringacc_dmarings_init(struct platform_device *pdev,
>
> mutex_init(&ringacc->req_lock);
>
> - base_rt = devm_platform_ioremap_resource_byname(pdev, "ringrt");
> - if (IS_ERR(base_rt))
> - return ERR_CAST(base_rt);
> + base_rt = data->base_rt;
> + if (!base_rt) {
> + base_rt = devm_platform_ioremap_resource_byname(pdev, "ringrt");
> + if (IS_ERR(base_rt))
> + return ERR_CAST(base_rt);
> + }
>
> ringacc->rings = devm_kzalloc(dev,
> sizeof(*ringacc->rings) *
> @@ -1498,6 +1608,10 @@ struct k3_ringacc *k3_ringacc_dmarings_init(struct platform_device *pdev,
> struct k3_ring *ring = &ringacc->rings[i];
>
> ring->rt = base_rt + K3_DMARING_RT_REGS_STEP * i;
> + ring->cfg = base_rt + K3_RINGACC_RT_CFG_REGS_OFS +
> + K3_DMARING_RT_REGS_STEP * i;
> + ring->intr = base_rt + K3_RINGACC_RT_INT_REGS_OFS +
> + K3_DMARING_RT_REGS_STEP * i;
> ring->parent = ringacc;
> ring->ring_id = i;
> ring->proxy_id = K3_RINGACC_PROXY_NOT_USED;
> diff --git a/include/linux/soc/ti/k3-ringacc.h b/include/linux/soc/ti/k3-ringacc.h
> index 39b022b925986..fcf6fbd4a8594 100644
> --- a/include/linux/soc/ti/k3-ringacc.h
> +++ b/include/linux/soc/ti/k3-ringacc.h
> @@ -158,6 +158,9 @@ u32 k3_ringacc_get_ring_id(struct k3_ring *ring);
> */
> int k3_ringacc_get_ring_irq_num(struct k3_ring *ring);
>
> +u32 k3_ringacc_ring_get_irq_status(struct k3_ring *ring);
> +void k3_ringacc_ring_clear_irq(struct k3_ring *ring);
> +
> /**
> * k3_ringacc_ring_cfg - ring configure
> * @ring: pointer on ring
> @@ -262,6 +265,7 @@ struct k3_ringacc_init_data {
> const struct ti_sci_handle *tisci;
> u32 tisci_dev_id;
> u32 num_rings;
> + void __iomem *base_rt;
> };
>
> struct k3_ringacc *k3_ringacc_dmarings_init(struct platform_device *pdev,
--
Péter
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 3/8] drivers: dma: ti: Refactor TI K3 UDMA driver
2025-05-09 14:25 ` Péter Ujfalusi
@ 2025-05-28 10:29 ` Adivi, Sai Sree Kartheek
0 siblings, 0 replies; 17+ messages in thread
From: Adivi, Sai Sree Kartheek @ 2025-05-28 10:29 UTC (permalink / raw)
To: Péter Ujfalusi, vkoul, robh, krzk+dt, conor+dt, nm, ssantosh,
dmaengine, devicetree, linux-kernel, linux-arm-kernel, praneeth,
vigneshr, u-kumar1, a-chavda
On 5/9/2025 7:55 PM, Péter Ujfalusi wrote:
> Hi,
>
> On 28/04/2025 10:20, Sai Sree Kartheek Adivi wrote:
>> Refactors and split the driver into common and device
>> specific parts. There are no functional changes.
>>
>> Signed-off-by: Sai Sree Kartheek Adivi <s-adivi@ti.com>
>> ---
>> drivers/dma/ti/Makefile | 2 +-
>> drivers/dma/ti/k3-udma-common.c | 2909 ++++++++++++++++++++++++
>> drivers/dma/ti/k3-udma.c | 3751 ++-----------------------------
>
> I'm affraid you do need to break this one up a bit. It might be doing it
> correctly, but it is impossible to check with the churn, like ....
noted. I'm working on splitting this. Will post a v2.
>
>> drivers/dma/ti/k3-udma.h | 548 ++++-
>> 4 files changed, 3700 insertions(+), 3510 deletions(-)
>> create mode 100644 drivers/dma/ti/k3-udma-common.c
>
> ...
>
>> -static bool udma_is_chan_running(struct udma_chan *uc)
>> -{
>> - u32 trt_ctl = 0;
>> - u32 rrt_ctl = 0;
>> -
>> - if (uc->tchan)
>> - trt_ctl = udma_tchanrt_read(uc, UDMA_CHAN_RT_CTL_REG);
>> - if (uc->rchan)
>> - rrt_ctl = udma_rchanrt_read(uc, UDMA_CHAN_RT_CTL_REG);
>> -
>> - if (trt_ctl & UDMA_CHAN_RT_CTL_EN || rrt_ctl & UDMA_CHAN_RT_CTL_EN)
>> - return true;
>> -
>> - return false;
>> -}
>> -
>> static bool udma_is_chan_paused(struct udma_chan *uc)
>> {
>> u32 val, pause_mask;
>> @@ -643,189 +88,73 @@ static bool udma_is_chan_paused(struct udma_chan *uc)
>> return false;
>> }
>>
>> -static inline dma_addr_t udma_get_rx_flush_hwdesc_paddr(struct udma_chan *uc)
>> +static void udma_decrement_byte_counters(struct udma_chan *uc, u32 val)
>
>
> These sort of diffs.
>
>> {
>> - return uc->ud->rx_flush.hwdescs[uc->config.pkt_mode].cppi5_desc_paddr;
>> + if (uc->desc->dir == DMA_DEV_TO_MEM) {
>> + udma_rchanrt_write(uc, UDMA_CHAN_RT_BCNT_REG, val);
>> + udma_rchanrt_write(uc, UDMA_CHAN_RT_SBCNT_REG, val);
>> + if (uc->config.ep_type != PSIL_EP_NATIVE)
>> + udma_rchanrt_write(uc, UDMA_CHAN_RT_PEER_BCNT_REG, val);
>> + } else {
>> + udma_tchanrt_write(uc, UDMA_CHAN_RT_BCNT_REG, val);
>> + udma_tchanrt_write(uc, UDMA_CHAN_RT_SBCNT_REG, val);
>> + if (!uc->bchan && uc->config.ep_type != PSIL_EP_NATIVE)
>> + udma_tchanrt_write(uc, UDMA_CHAN_RT_PEER_BCNT_REG, val);
>> + }
>> }
>>
>> -static int udma_push_to_ring(struct udma_chan *uc, int idx)
>> +static void udma_reset_counters(struct udma_chan *uc)
>> {
>
> ...
>
>> +struct udma_dev {
>> + struct dma_device ddev;
>> + struct device *dev;
>> + void __iomem *mmrs[MMR_LAST];
>> + const struct udma_match_data *match_data;
>> + const struct udma_soc_data *soc_data;
>> +
>> + struct udma_tpl bchan_tpl;
>> + struct udma_tpl tchan_tpl;
>> + struct udma_tpl rchan_tpl;
>> +
>> + size_t desc_align; /* alignment to use for descriptors */
>> +
>> + struct udma_tisci_rm tisci_rm;
>> +
>> + struct k3_ringacc *ringacc;
>> +
>> + struct work_struct purge_work;
>> + struct list_head desc_to_purge;
>> + spinlock_t lock;
>> +
>> + struct udma_rx_flush rx_flush;
>> +
>> + int bchan_cnt;
>> + int tchan_cnt;
>> + int echan_cnt;
>> + int rchan_cnt;
>> + int rflow_cnt;
>> + int tflow_cnt;
>> + unsigned long *bchan_map;
>> + unsigned long *tchan_map;
>> + unsigned long *rchan_map;
>> + unsigned long *rflow_gp_map;
>> + unsigned long *rflow_gp_map_allocated;
>> + unsigned long *rflow_in_use;
>> + unsigned long *tflow_map;
>> +
>> + struct udma_bchan *bchans;
>> + struct udma_tchan *tchans;
>> + struct udma_rchan *rchans;
>> + struct udma_rflow *rflows;
>> +
>> + struct udma_chan *channels;
>> + u32 psil_base;
>> + u32 atype;
>> + u32 asel;
>> +
>> + int (*udma_start)(struct udma_chan *uc);
>> + int (*udma_stop)(struct udma_chan *uc);
>> + int (*udma_reset_chan)(struct udma_chan *uc, bool hard);
>> + bool (*udma_is_desc_really_done)(struct udma_chan *uc, struct udma_desc *d);
>> + void (*udma_decrement_byte_counters)(struct udma_chan *uc, u32 val);
>
> You can drop the udma_ prefix, it is clear that they are for udma..
>
>> +};
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2025-05-28 10:31 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-04-28 7:20 [PATCH 0/8] dmaengine: ti: Add support for BCDMA v2 and PKTDMA v2 Sai Sree Kartheek Adivi
2025-04-28 7:20 ` [PATCH 1/8] dt-bindings: dma: ti: Add document for K3 BCDMA V2 Sai Sree Kartheek Adivi
2025-04-30 10:26 ` Krzysztof Kozlowski
2025-04-28 7:20 ` [PATCH 2/8] dt-bindings: dma: ti: Add document for K3 PKTDMA V2 Sai Sree Kartheek Adivi
2025-04-30 10:26 ` Krzysztof Kozlowski
2025-04-28 7:20 ` [PATCH 4/8] dmaengine: ti: k3-psil-am62l: Add AM62Lx PSIL and PDMA data Sai Sree Kartheek Adivi
2025-04-28 7:20 ` [PATCH 5/8] drivers: soc: ti: k3-ringacc: handle absence of tisci Sai Sree Kartheek Adivi
2025-04-28 18:45 ` kernel test robot
2025-05-09 16:29 ` Péter Ujfalusi
2025-04-28 7:20 ` [PATCH 6/8] dmaengine: ti: New driver for K3 BCDMA_V2 Sai Sree Kartheek Adivi
2025-04-29 8:05 ` kernel test robot
2025-05-07 7:31 ` kernel test robot
2025-04-28 7:20 ` [PATCH 7/8] dmaengine: ti: k3-udma-v2: Add support for PKTDMA V2 Sai Sree Kartheek Adivi
2025-04-28 7:20 ` [PATCH 8/8] dmaengine: ti: k3-udma-v2: Update glue layer to support " Sai Sree Kartheek Adivi
[not found] ` <20250428072032.946008-4-s-adivi@ti.com>
2025-04-30 10:28 ` [PATCH 3/8] drivers: dma: ti: Refactor TI K3 UDMA driver Krzysztof Kozlowski
2025-05-09 14:25 ` Péter Ujfalusi
2025-05-28 10:29 ` Adivi, Sai Sree Kartheek
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