From: Sudeep Holla <sudeep.holla@arm.com>
To: Sean Anderson <sean.anderson@linux.dev>
Cc: "Catalin Marinas" <catalin.marinas@arm.com>,
"Sudeep Holla" <sudeep.holla@arm.com>,
linux-arm-kernel@lists.infradead.org,
"Radu Rendec" <rrendec@redhat.com>,
"Will Deacon" <will@kernel.org>,
"Thomas Weißschuh" <thomas.weissschuh@linutronix.de>,
"Thomas Gleixner" <tglx@linutronix.de>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] arm64: cacheinfo: Report cache sets, ways, and line size
Date: Sat, 10 May 2025 08:04:56 +0100 [thread overview]
Message-ID: <20250510-fresh-magenta-owl-c36fb7@sudeepholla> (raw)
In-Reply-To: <20250509233735.641419-1-sean.anderson@linux.dev>
On Fri, May 09, 2025 at 07:37:35PM -0400, Sean Anderson wrote:
> Cache geometry is exposed through the Cache Size ID register. There is
> one register for each cache, and they are selected through the Cache
> Size Selection register. If FEAT_CCIDX is implemented, the layout of
> CCSIDR changes to allow a larger number of sets and ways.
>
Please refer
Commit a8d4636f96ad ("arm64: cacheinfo: Remove CCSIDR-based cache information probing")
--
Regards,
Sudeep
next prev parent reply other threads:[~2025-05-10 7:07 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-09 23:37 [PATCH] arm64: cacheinfo: Report cache sets, ways, and line size Sean Anderson
2025-05-10 7:04 ` Sudeep Holla [this message]
2025-05-12 15:28 ` Sean Anderson
2025-05-12 15:34 ` Sudeep Holla
2025-05-12 15:52 ` Sean Anderson
2025-05-12 15:36 ` Mark Rutland
2025-05-12 15:56 ` Sean Anderson
2025-05-14 12:38 ` Will Deacon
2025-05-19 20:50 ` Sean Anderson
2025-05-14 14:50 ` Rob Herring
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