From: Sudeep Holla <sudeep.holla@arm.com>
To: Sean Anderson <sean.anderson@linux.dev>
Cc: "Catalin Marinas" <catalin.marinas@arm.com>,
"Sudeep Holla" <sudeep.holla@arm.com>,
linux-arm-kernel@lists.infradead.org,
"Radu Rendec" <rrendec@redhat.com>,
"Will Deacon" <will@kernel.org>,
"Thomas Weißschuh" <thomas.weissschuh@linutronix.de>,
"Thomas Gleixner" <tglx@linutronix.de>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] arm64: cacheinfo: Report cache sets, ways, and line size
Date: Mon, 12 May 2025 16:34:35 +0100 [thread overview]
Message-ID: <20250512-straight-dexterous-oxpecker-fabbc8@sudeepholla> (raw)
In-Reply-To: <f63c2be5-50e4-4c47-8a56-9a570977a6cf@linux.dev>
On Mon, May 12, 2025 at 11:28:36AM -0400, Sean Anderson wrote:
> On 5/10/25 03:04, Sudeep Holla wrote:
> > On Fri, May 09, 2025 at 07:37:35PM -0400, Sean Anderson wrote:
> >> Cache geometry is exposed through the Cache Size ID register. There is
> >> one register for each cache, and they are selected through the Cache
> >> Size Selection register. If FEAT_CCIDX is implemented, the layout of
> >> CCSIDR changes to allow a larger number of sets and ways.
> >>
> >
> > Please refer
> > Commit a8d4636f96ad ("arm64: cacheinfo: Remove CCSIDR-based cache information probing")
> >
>
> | The CCSIDR_EL1.{NumSets,Associativity,LineSize} fields are only for use
> | in conjunction with set/way cache maintenance and are not guaranteed to
> | represent the actual microarchitectural features of a design.
> |
> | The architecture explicitly states:
> |
> | | You cannot make any inference about the actual sizes of caches based
> | | on these parameters.
>
> However, on many cores (A53, A72, and surely others that I haven't
> checked) these *do* expose the actual microarchitectural features of the
> design. Maybe a whitelist would be suitable.
>
> | Furthermore, CCSIDR_EL1.{WT,WB,RA,WA} have been removed retrospectively
> | from ARMv8 and are now considered to be UNKNOWN.
> |
> | Since the kernel doesn't make use of set/way cache maintenance and it is
> | not possible for userspace to execute these instructions, we have no
> | need for the CCSIDR information in the kernel.
>
> Actually, these parameters are directly visible (and useful) to
> userspace in the form of the cache size. Rather than make userspace
> perform benchmarks, we can expose this information in a standard way.
Yes that is already present, which is DT or ACPI.
> There is of course [id]cache-size, but these properties are absent more
> often than not:
>
> $ git grep arm,cortex- 'arch/arm64/**.dtsi' | wc -l
> 1248
> $ git grep d-cache-size 'arch/arm64/**.dtsi' | wc -l
> 320
>
Just to be clear, I am fine with exposing to the userspace, but just
not reading those registers as stated in the commit message I shared
earlier.
Why can't it be done via DT/ACPI ?
--
Regards,
Sudeep
next prev parent reply other threads:[~2025-05-12 15:54 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-09 23:37 [PATCH] arm64: cacheinfo: Report cache sets, ways, and line size Sean Anderson
2025-05-10 7:04 ` Sudeep Holla
2025-05-12 15:28 ` Sean Anderson
2025-05-12 15:34 ` Sudeep Holla [this message]
2025-05-12 15:52 ` Sean Anderson
2025-05-12 15:36 ` Mark Rutland
2025-05-12 15:56 ` Sean Anderson
2025-05-14 12:38 ` Will Deacon
2025-05-19 20:50 ` Sean Anderson
2025-05-14 14:50 ` Rob Herring
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