From: Bjorn Helgaas <helgaas@kernel.org>
To: Vincent Guittot <vincent.guittot@linaro.org>
Cc: chester62515@gmail.com, mbrugger@suse.com,
ghennadi.procopciuc@oss.nxp.com, s32@nxp.com,
lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
Ionut.Vicovan@nxp.com, larisa.grigore@nxp.com,
Ghennadi.Procopciuc@nxp.com, ciprianmarian.costea@nxp.com,
bogdan.hamciuc@nxp.com, linux-arm-kernel@lists.infradead.org,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/4] pcie: s32g: Add Phy clock definition
Date: Fri, 12 Sep 2025 17:18:17 -0500 [thread overview]
Message-ID: <20250912221817.GA1650405@bhelgaas> (raw)
In-Reply-To: <20250912141436.2347852-3-vincent.guittot@linaro.org>
On Fri, Sep 12, 2025 at 04:14:34PM +0200, Vincent Guittot wrote:
> From: Ciprian Costea <ciprianmarian.costea@nxp.com>
>
> Define the list of Clock mode supported by PCIe
>
> Signed-off-by: Ciprian Costea <ciprianmarian.costea@nxp.com>
> Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
> ---
> include/linux/pcie/nxp-s32g-pcie-phy-submode.h | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
> create mode 100644 include/linux/pcie/nxp-s32g-pcie-phy-submode.h
>
> diff --git a/include/linux/pcie/nxp-s32g-pcie-phy-submode.h b/include/linux/pcie/nxp-s32g-pcie-phy-submode.h
> new file mode 100644
> index 000000000000..2b96b5fd68c0
> --- /dev/null
> +++ b/include/linux/pcie/nxp-s32g-pcie-phy-submode.h
> @@ -0,0 +1,15 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/**
> + * Copyright 2021, 2025 NXP
> + */
> +#ifndef NXP_S32G_PCIE_PHY_SUBMODE_H
> +#define NXP_S32G_PCIE_PHY_SUBMODE_H
> +
> +enum pcie_phy_mode {
> + CRNS = 0, /* Common Reference Clock, No Spread Spectrum */
> + CRSS = 1, /* Common Reference Clock, Spread Spectrum */
> + SRNS = 2, /* Separate Reference Clock, No Spread Spectrum */
> + SRIS = 3 /* Separate Reference Clock, Independent Spread Spectrum */
> +};
> +
> +#endif
I doubt this belongs in include/linux/. It looks like it should be in
pci-s32g.c since that's the only use.
next prev parent reply other threads:[~2025-09-12 22:18 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-12 14:14 [PATCH 0/4] pcie: s32g: Add support for PCIe controller Vincent Guittot
2025-09-12 14:14 ` [PATCH 1/4] dt-bindings: pcie: Add the NXP " Vincent Guittot
2025-09-12 20:50 ` Frank Li
2025-09-14 12:34 ` Vincent Guittot
2025-09-12 22:50 ` Bjorn Helgaas
2025-09-14 12:35 ` Vincent Guittot
2025-09-16 8:10 ` Vincent Guittot
2025-09-16 14:23 ` Bjorn Helgaas
2025-09-17 17:11 ` Manivannan Sadhasivam
2025-09-17 21:28 ` Bjorn Helgaas
2025-09-18 9:54 ` Vincent Guittot
2025-09-18 11:27 ` Manivannan Sadhasivam
2025-09-17 8:42 ` Niklas Cassel
2025-09-17 17:21 ` Vincent Guittot
2025-09-17 21:18 ` Bjorn Helgaas
2025-09-18 5:55 ` Vincent Guittot
2025-09-12 14:14 ` [PATCH 2/4] pcie: s32g: Add Phy clock definition Vincent Guittot
2025-09-12 22:18 ` Bjorn Helgaas [this message]
2025-09-14 12:36 ` Vincent Guittot
2025-09-12 14:14 ` [PATCH 3/4] pcie: s32g: Add initial PCIe support (RC) Vincent Guittot
2025-09-12 21:30 ` Frank Li
2025-09-14 12:43 ` Vincent Guittot
2025-09-12 23:02 ` Bjorn Helgaas
2025-09-14 12:44 ` Vincent Guittot
2025-09-14 10:15 ` Krzysztof Kozlowski
2025-09-14 12:45 ` Vincent Guittot
2025-09-12 14:14 ` [PATCH 4/4] MAINTAINERS: Add MAINTAINER for NXP S32G PCIe driver Vincent Guittot
2025-09-12 20:52 ` Frank Li
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