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From: Conor Dooley <conor@kernel.org>
To: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Cc: "Michael Turquette" <mturquette@baylibre.com>,
	"Stephen Boyd" <sboyd@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Matthias Brugger" <matthias.bgg@gmail.com>,
	"AngeloGioacchino Del Regno"
	<angelogioacchino.delregno@collabora.com>,
	"Guangjie Song" <guangjie.song@mediatek.com>,
	"Laura Nao" <laura.nao@collabora.com>,
	"Nícolas F. R. A. Prado" <nfraprado@collabora.com>,
	"Yassine Oudjana" <y.oudjana@protonmail.com>,
	kernel@collabora.com,
	"Krzysztof Kozlowski" <krzysztof.kozlowski@linaro.org>,
	linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-mediatek@lists.infradead.org
Subject: Re: [PATCH 1/4] dt-bindings: clock: mediatek: Add clocks for MT8196 mfgpll
Date: Mon, 29 Sep 2025 18:31:36 +0100	[thread overview]
Message-ID: <20250929-whoops-kennel-5f54fb6559a8@spud> (raw)
In-Reply-To: <20250929-mtk-pll-rpm-v1-1-49541777878d@collabora.com>

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On Mon, Sep 29, 2025 at 02:13:20PM +0200, Nicolas Frattaroli wrote:
> The clock controllers for mfgpll, mfgpll-sc0, and mfgpll-sc1 all need
> CLK_TOP_MFG_EB to be on if their clock control registers are touched in
> any way.
> 
> This was not known at the time this binding was written, as this
> dependency only came to light when I started poking at the MFlexGraphics
> hardware, where this undocumented peculiarity made itself known through
> SErrors being thrown during register reads.
> 
> Add a clocks property to the binding to describe this relationship, and
> mark it as required for the affected clocks.
> 
> Fixes: dd240e95f1be ("dt-bindings: clock: mediatek: Describe MT8196 clock controllers")
> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
> ---
>  .../bindings/clock/mediatek,mt8196-sys-clock.yaml  | 28 ++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml
> index 660ab64f390d2e722b7d3e25cf057926da318bc0..41aacd8d5f69050eebdf8392f7b652427632f491 100644
> --- a/Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml
> +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml
> @@ -45,6 +45,9 @@ properties:
>    reg:
>      maxItems: 1
>  
> +  clocks:
> +    maxItems: 1
> +
>    '#clock-cells':
>      const: 1
>  
> @@ -90,6 +93,23 @@ required:
>  
>  additionalProperties: false
>  
> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - mediatek,mt8196-mfgpll-pll-ctrl
> +              - mediatek,mt8196-mfgpll-sc0-pll-ctrl
> +              - mediatek,mt8196-mfgpll-sc1-pll-ctrl
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: mfg_eb clock
> +      required:
> +        - clocks

Don't you want an else: properties: clocks: false here?

> +
>  examples:
>    - |
>      apmixedsys_clk: syscon@10000800 {
> @@ -104,4 +124,12 @@ examples:
>          mediatek,hardware-voter = <&scp_hwv>;
>          #clock-cells = <1>;
>      };
> +  - |
> +    #include <dt-bindings/clock/mediatek,mt8196-clock.h>
>  
> +    clock-controller@4b810000 {
> +        compatible = "mediatek,mt8196-mfgpll-pll-ctrl", "syscon";
> +        reg = <0x4b810000 0x400>;
> +        clocks = <&topckgen CLK_TOP_MFG_EB>;
> +        #clock-cells = <1>;
> +    };
> 
> -- 
> 2.51.0
> 

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  reply	other threads:[~2025-09-29 17:31 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-29 12:13 [PATCH 0/4] MediaTek Runtime Power Management Clocks for PLL Nicolas Frattaroli
2025-09-29 12:13 ` [PATCH 1/4] dt-bindings: clock: mediatek: Add clocks for MT8196 mfgpll Nicolas Frattaroli
2025-09-29 17:31   ` Conor Dooley [this message]
2025-09-30 15:57     ` Nicolas Frattaroli
2025-09-30 18:36       ` Conor Dooley
2025-09-29 12:13 ` [PATCH 2/4] clk: mediatek: Refactor pll registration to pass device Nicolas Frattaroli
2025-10-01 11:43   ` AngeloGioacchino Del Regno
2025-09-29 12:13 ` [PATCH 3/4] clk: mediatek: Pass device to clk_hw_register for PLLs Nicolas Frattaroli
2025-10-01 11:40   ` AngeloGioacchino Del Regno
2025-09-29 12:13 ` [PATCH 4/4] clk: mediatek: Add rpm clocks to clk-mt8196-mfg Nicolas Frattaroli
2025-10-01 11:49   ` AngeloGioacchino Del Regno
2025-10-01 13:17     ` Nicolas Frattaroli
2025-10-06 19:01       ` Nicolas Frattaroli
2025-10-07  7:36         ` AngeloGioacchino Del Regno

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