From: Conor Dooley <conor@kernel.org>
To: Elaine Zhang <zhangqing@rock-chips.com>
Cc: mturquette@baylibre.com, sboyd@kernel.org,
sugar.zhang@rock-chips.com, heiko@sntech.de, robh@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org,
linux-kernel@vger.kernel.org, huangtao@rock-chips.com
Subject: Re: [PATCH v3 4/5] dt-bindings: clock: Add support for rockchip pvtpll
Date: Mon, 20 Oct 2025 18:26:30 +0100 [thread overview]
Message-ID: <20251020-dose-treason-2a0ac50c6bb4@spud> (raw)
In-Reply-To: <20251020023724.2723372-5-zhangqing@rock-chips.com>
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On Mon, Oct 20, 2025 at 10:37:23AM +0800, Elaine Zhang wrote:
> Add pvtpll documentation for rockchip.
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> ---
> .../bindings/clock/rockchip,clk-pvtpll.yaml | 100 ++++++++++++++++++
> 1 file changed, 100 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/rockchip,clk-pvtpll.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/rockchip,clk-pvtpll.yaml b/Documentation/devicetree/bindings/clock/rockchip,clk-pvtpll.yaml
> new file mode 100644
> index 000000000000..8be34bcde7b0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/rockchip,clk-pvtpll.yaml
> @@ -0,0 +1,100 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/rockchip,clk-pvtpll.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip Pvtpll
> +
> +maintainers:
> + - Elaine Zhang <zhangqing@rock-chips.com>
> + - Heiko Stuebner <heiko@sntech.de>
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - rockchip,rv1103b-core-pvtpll
> + - rockchip,rv1103b-enc-pvtpll
> + - rockchip,rv1103b-isp-pvtpll
> + - rockchip,rv1103b-npu-pvtpll
> + - rockchip,rv1126b-core-pvtpll
> + - rockchip,rv1126b-isp-pvtpll
> + - rockchip,rv1126b-enc-pvtpll
> + - rockchip,rv1126b-aisp-pvtpll
> + - rockchip,rv1126b-npu-pvtpll
> + - rockchip,rk3506-core-pvtpll
> + - const: syscon
> +
> + reg:
> + maxItems: 1
> +
> + "#clock-cells":
> + const: 0
> +
> + clocks:
> + maxItems: 1
> +
> + clock-output-names:
> + maxItems: 1
> +
> + rockchip,cru:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: |
> + Phandle to the main Clock and Reset Unit (CRU) controller.
> + Required for PVTPLLs that need to interact with the main CRU
> + for clock management operations.
> +
> +required:
> + - "#clock-cells"
> + - compatible
> + - reg
> + - clock-output-names
Please follow the property definition order here.
pw-bot: changes-requested
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next prev parent reply other threads:[~2025-10-20 17:26 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-20 2:37 [PATCH v3 0/5] clk: rockchip: Add clock controller for the RV1126B Elaine Zhang
2025-10-20 2:37 ` [PATCH v3 1/5] clk: rockchip: Implement rockchip_clk_register_armclk_multi_pll() Elaine Zhang
2025-10-20 2:37 ` [PATCH v3 2/5] dt-bindings: clock, reset: Add support for rv1126b Elaine Zhang
2025-10-20 17:27 ` Conor Dooley
2025-10-20 2:37 ` [PATCH v3 3/5] clk: rockchip: Add clock controller for the RV1126B Elaine Zhang
2025-10-20 2:37 ` [PATCH v3 4/5] dt-bindings: clock: Add support for rockchip pvtpll Elaine Zhang
2025-10-20 9:38 ` Diederik de Haas
2025-10-20 17:25 ` Conor Dooley
2025-10-20 17:26 ` Conor Dooley [this message]
2025-10-20 2:37 ` [PATCH v3 5/5] clk: rockchip: add support for pvtpll clk Elaine Zhang
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