* [PATCH 1/2] dt-bindings: arm: fsl: Add PHYTEC phyBOARD-Segin-i.MX91 board @ 2025-10-21 9:37 Primoz Fiser 2025-10-21 9:37 ` [PATCH 2/2] arm64: dts: freescale: Add phyBOARD-Segin-i.MX91 support Primoz Fiser 2025-10-22 17:39 ` [PATCH 1/2] dt-bindings: arm: fsl: Add PHYTEC phyBOARD-Segin-i.MX91 board Conor Dooley 0 siblings, 2 replies; 7+ messages in thread From: Primoz Fiser @ 2025-10-21 9:37 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam Cc: devicetree, linux-kernel, imx, linux-arm-kernel, upstream Add device-tree bindings for PHYTEC phyBOARD-Segin-i.MX91 board based on the PHYTEC phyCORE-i.MX91 SoM (System-on-Module). Signed-off-by: Primoz Fiser <primoz.fiser@norik.com> --- Documentation/devicetree/bindings/arm/fsl.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 00cdf490b062..73987ba1d16a 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1492,6 +1492,13 @@ properties: - const: tq,imx93-tqma9352 # TQ-Systems GmbH i.MX93 TQMa93xxCA/LA SOM - const: fsl,imx93 + - description: PHYTEC phyCORE-i.MX91 SoM based boards + items: + - enum: + - phytec,imx91-phyboard-segin # phyBOARD-Segin with i.MX91 + - const: phytec,imx91-phycore-som # phyCORE-i.MX91 SoM + - const: fsl,imx91 + - description: PHYTEC phyCORE-i.MX93 SoM based boards items: - enum: -- 2.34.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/2] arm64: dts: freescale: Add phyBOARD-Segin-i.MX91 support 2025-10-21 9:37 [PATCH 1/2] dt-bindings: arm: fsl: Add PHYTEC phyBOARD-Segin-i.MX91 board Primoz Fiser @ 2025-10-21 9:37 ` Primoz Fiser 2025-10-21 9:50 ` Marc Kleine-Budde 2025-10-22 9:43 ` [Upstream] " Teresa Remmet 2025-10-22 17:39 ` [PATCH 1/2] dt-bindings: arm: fsl: Add PHYTEC phyBOARD-Segin-i.MX91 board Conor Dooley 1 sibling, 2 replies; 7+ messages in thread From: Primoz Fiser @ 2025-10-21 9:37 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam Cc: devicetree, linux-kernel, imx, linux-arm-kernel, upstream Add initial support for the PHYTEC phyBOARD-Segin-i.MX91 board [1] based on the PHYTEC phyCORE-i.MX91 SoM (System-on-Module) [2]. Supported features: * Audio * CAN * eMMC * Ethernet * I2C * RTC * SD-Card * UART * USB For more details see the product pages for the development board and the SoM: [1] https://www.phytec.eu/en/produkte/development-kits/phyboard-segin-kit/ [2] https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ Signed-off-by: Primoz Fiser <primoz.fiser@norik.com> --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx91-phyboard-segin.dts | 344 ++++++++++++++++++ .../boot/dts/freescale/imx91-phycore-som.dtsi | 304 ++++++++++++++++ 3 files changed, 649 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts create mode 100644 arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 525ef180481d..34a81d34de39 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -344,6 +344,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqps-mb-smarc-2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-9x9-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx91-phyboard-segin.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb diff --git a/arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts new file mode 100644 index 000000000000..bb631439f9cf --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts @@ -0,0 +1,344 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Author: Christoph Stoidner <c.stoidner@phytec.de> + * + * Product homepage: + * phyBOARD-Segin carrier board is reused for the i.MX91 design. + * https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/ + */ +/dts-v1/; + +#include "imx91-phycore-som.dtsi" + +/{ + model = "PHYTEC phyBOARD-Segin-i.MX91"; + compatible = "phytec,imx91-phyboard-segin", "phytec,imx91-phycore-som", + "fsl,imx91"; + + aliases { + ethernet1 = &eqos; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + rtc0 = &i2c_rtc; + rtc1 = &bbnsm_rtc; + serial0 = &lpuart1; + }; + + chosen { + stdout-path = &lpuart1; + }; + + flexcan1_tc: can-phy0 { + compatible = "ti,tcan1043"; + #phy-cells = <0>; + max-bitrate = <1000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1_tc>; + enable-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; + }; + + reg_sound_1v8: regulator-sound-1v8 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "VCC1V8_AUDIO"; + }; + + reg_sound_3v3: regulator-sound-3v3 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VCC3V3_ANALOG"; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + regulator-name = "USB_OTG1_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { + compatible = "regulator-fixed"; + regulator-name = "USB_OTG2_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "VCC_SD"; + }; + + sound: sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "phyBOARD-Segin-TLV320AIC3007"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,widgets = + "Line", "Line In", + "Line", "Line Out", + "Speaker", "Speaker"; + simple-audio-card,routing = + "Line Out", "LLOUT", + "Line Out", "RLOUT", + "Speaker", "SPOP", + "Speaker", "SPOM", + "LINE1L", "Line In", + "LINE1R", "Line In"; + + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&audio_codec>; + clocks = <&clk IMX93_CLK_SAI1>; + }; + }; +}; + +/* Ethernet */ +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rmii"; + phy-handle = <ðphy2>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <100000000>, <50000000>; + status = "okay"; +}; + +&mdio { + ethphy2: ethernet-phy@2 { + compatible = "ethernet-phy-id0022.1561"; + reg = <2>; + clocks = <&clk IMX91_CLK_ENET2_REGULAR>; + clock-names = "rmii-ref"; + micrel,led-mode = <1>; + }; +}; + +/* CAN */ +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + phys = <&flexcan1_tc>; + status = "okay"; +}; + +/* I2C2 */ +&lpi2c2 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-1 = <&pinctrl_lpi2c2_gpio>; + scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + /* Codec */ + audio_codec: audio-codec@18 { + compatible = "ti,tlv320aic3007"; + reg = <0x18>; + #sound-dai-cells = <0>; + AVDD-supply = <®_sound_3v3>; + IOVDD-supply = <®_sound_3v3>; + DRVDD-supply = <®_sound_3v3>; + DVDD-supply = <®_sound_1v8>; + }; + + /* RTC */ + i2c_rtc: rtc@68 { + compatible = "microcrystal,rv4162"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupt-parent = <&gpio4>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +/* Console */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* Audio */ +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <19200000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +/* USB */ +&usbphynop1 { + vbus-supply = <®_usb_otg1_vbus>; +}; + +&usbphynop2 { + vbus-supply = <®_usb_otg2_vbus>; +}; + +&usbotg1 { + disable-over-current; + dr_mode = "otg"; + status = "okay"; +}; + +&usbotg2 { + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +/* SD-Card */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_default>, <&pinctrl_usdhc2_cd>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; + bus-width = <4>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + disable-wp; + no-mmc; + no-sdio; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX91_PAD_ENET1_TD2__ENET_QOS_CLOCK_GENERATE_CLK 0x4000050e + MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x50e + MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x50e + MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x50e + MX91_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x57e + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e + MX91_PAD_PDM_CLK__CAN1_TX 0x139e + >; + }; + + pinctrl_flexcan1_tc: flexcan1tcgrp { + fsl,pins = < + MX91_PAD_ENET2_TD3__GPIO4_IO16 0x31e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c2_gpio: lpi2c2gpiogrp { + fsl,pins = < + MX91_PAD_I2C2_SCL__GPIO1_IO2 0x31e + MX91_PAD_I2C2_SDA__GPIO1_IO3 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX91_PAD_ENET2_RD2__GPIO4_IO26 0x31e + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX91_PAD_UART2_RXD__SAI1_MCLK 0x1202 + MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x1202 + MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x1202 + MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x1402 + MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x1402 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX91_PAD_UART1_RXD__LPUART1_RX 0x31e + MX91_PAD_UART1_TXD__LPUART1_TX 0x30e + >; + }; + + pinctrl_usdhc2_cd: usdhc2cdgrp { + fsl,pins = < + MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e + >; + }; + + pinctrl_usdhc2_default: usdhc2grp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382 + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1386 + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x139e + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x139e + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x159e + MX91_PAD_SD2_CMD__USDHC2_CMD 0x139e + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x139e + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x139e + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x139e + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x139e + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x139e + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x139e + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi new file mode 100644 index 000000000000..0d9310f86f45 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi @@ -0,0 +1,304 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Author: Christoph Stoidner <c.stoidner@phytec.de> + * + * Product homepage: + * https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ + */ + +#include <dt-bindings/leds/common.h> + +#include "imx91.dtsi" + +/ { + model = "PHYTEC phyCORE-i.MX91"; + compatible = "phytec,imx91-phycore-som", "fsl,imx91"; + + aliases { + ethernet0 = &fec; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + alloc-ranges = <0 0x80000000 0 0x40000000>; + size = <0 0x10000000>; + linux,cma-default; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-0 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_vdda_1v8: regulator-vdda-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VDDA_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&buck5>; + }; +}; + +/* ADC */ +&adc1 { + vref-supply = <®_vdda_1v8>; +}; + +/* Ethernet */ +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + + assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>, + <&clk IMX91_CLK_ENET2_REGULAR>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <100000000>, <50000000>; + status = "okay"; + + mdio: mdio { + clock-frequency = <5000000>; + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; + reset-assert-us = <30>; + }; + }; +}; + +/* I2C3 */ +&lpi2c3 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3_gpio>; + scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio4>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1: BUCK1 { + regulator-name = "VDD_SOC"; + regulator-min-microvolt = <610000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "VDDQ_0V6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <600000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4: BUCK4 { + regulator-name = "VDD_3V3_BUCK"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "VDD_1V1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "PMIC_SNVS_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "VDD_0V8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "NVCC_SD2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + /* EEPROM */ + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + vcc-supply = <&buck4>; + }; +}; + +/* eMMC */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + no-1-8-v; + status = "okay"; +}; + +/* Watchdog */ +&wdog3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_fec: fecgrp { + fsl,pins = < + MX91_PAD_ENET2_MDC__ENET2_MDC 0x50e + MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x502 + /* the three pins below are connected to PHYs straps, + * that is what the pull-up/down setting is for. + */ + MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x37e + MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x37e + MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x57e + MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x50e + MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x50e + MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x50e + MX91_PAD_ENET2_TD2__ENET2_TX_CLK2 0x4000050e + MX91_PAD_ENET2_RXC__GPIO4_IO23 0x51e + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX91_PAD_I2C1_SDA__GPIO1_IO1 0x11e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c3_gpio: lpi2c3gpiogrp { + fsl,pins = < + MX91_PAD_GPIO_IO28__GPIO2_IO28 0x31e + MX91_PAD_GPIO_IO29__GPIO2_IO29 0x31e + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX91_PAD_ENET2_RD3__GPIO4_IO27 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x179e + MX91_PAD_SD1_CMD__USDHC1_CMD 0x1386 + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1386 + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1386 + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1386 + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1386 + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1386 + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1386 + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x179e + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x17be + MX91_PAD_SD1_CMD__USDHC1_CMD 0x139e + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x139e + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13be + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x139e + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x139e + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x139e + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x139e + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x139e + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x179e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x17be + MX91_PAD_SD1_CMD__USDHC1_CMD 0x139e + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x139e + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13be + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13be + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13be + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13be + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13be + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13be + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13be + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x179e + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX91_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e + >; + }; +}; -- 2.34.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] arm64: dts: freescale: Add phyBOARD-Segin-i.MX91 support 2025-10-21 9:37 ` [PATCH 2/2] arm64: dts: freescale: Add phyBOARD-Segin-i.MX91 support Primoz Fiser @ 2025-10-21 9:50 ` Marc Kleine-Budde 2025-10-21 10:07 ` Primoz Fiser 2025-10-22 9:43 ` [Upstream] " Teresa Remmet 1 sibling, 1 reply; 7+ messages in thread From: Marc Kleine-Budde @ 2025-10-21 9:50 UTC (permalink / raw) To: Primoz Fiser Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, devicetree, upstream, linux-kernel, linux-arm-kernel, imx [-- Attachment #1: Type: text/plain, Size: 3677 bytes --] On 21.10.2025 11:37:04, Primoz Fiser wrote: > Add initial support for the PHYTEC phyBOARD-Segin-i.MX91 board [1] based > on the PHYTEC phyCORE-i.MX91 SoM (System-on-Module) [2]. > > Supported features: > * Audio > * CAN > * eMMC > * Ethernet > * I2C > * RTC > * SD-Card > * UART > * USB > > For more details see the product pages for the development board and the > SoM: > > [1] https://www.phytec.eu/en/produkte/development-kits/phyboard-segin-kit/ > [2] https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ > > Signed-off-by: Primoz Fiser <primoz.fiser@norik.com> > --- > arch/arm64/boot/dts/freescale/Makefile | 1 + > .../dts/freescale/imx91-phyboard-segin.dts | 344 ++++++++++++++++++ > .../boot/dts/freescale/imx91-phycore-som.dtsi | 304 ++++++++++++++++ > 3 files changed, 649 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts > create mode 100644 arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi > > diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile > index 525ef180481d..34a81d34de39 100644 > --- a/arch/arm64/boot/dts/freescale/Makefile > +++ b/arch/arm64/boot/dts/freescale/Makefile > @@ -344,6 +344,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqps-mb-smarc-2.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8ulp-9x9-evk.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb > dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-evk.dtb > +dtb-$(CONFIG_ARCH_MXC) += imx91-phyboard-segin.dtb > dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca.dtb > dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb > > diff --git a/arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts > new file mode 100644 > index 000000000000..bb631439f9cf > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts > @@ -0,0 +1,344 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2025 PHYTEC Messtechnik GmbH > + * Author: Christoph Stoidner <c.stoidner@phytec.de> > + * > + * Product homepage: > + * phyBOARD-Segin carrier board is reused for the i.MX91 design. > + * https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/ > + */ > +/dts-v1/; > + > +#include "imx91-phycore-som.dtsi" > + > +/{ > + model = "PHYTEC phyBOARD-Segin-i.MX91"; > + compatible = "phytec,imx91-phyboard-segin", "phytec,imx91-phycore-som", > + "fsl,imx91"; > + > + aliases { > + ethernet1 = &eqos; > + gpio0 = &gpio1; > + gpio1 = &gpio2; > + gpio2 = &gpio3; > + gpio3 = &gpio4; > + i2c0 = &lpi2c1; > + i2c1 = &lpi2c2; > + mmc0 = &usdhc1; > + mmc1 = &usdhc2; > + rtc0 = &i2c_rtc; > + rtc1 = &bbnsm_rtc; > + serial0 = &lpuart1; > + }; > + > + chosen { > + stdout-path = &lpuart1; > + }; > + > + flexcan1_tc: can-phy0 { > + compatible = "ti,tcan1043"; > + #phy-cells = <0>; > + max-bitrate = <1000000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_flexcan1_tc>; > + enable-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; > + }; I think the tcan1043 is a CAN-FD transceiver. According to the datasheet it support 2 MBit/s and 5 MBit/s in the "G" variant. However due to the board layout, etc, the actual bit rate might still be limited to 1 MBit/s. Ask the HW engineers if in doubt. regards, Marc -- Pengutronix e.K. | Marc Kleine-Budde | Embedded Linux | https://www.pengutronix.de | Vertretung Nürnberg | Phone: +49-5121-206917-129 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-9 | [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 488 bytes --] ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] arm64: dts: freescale: Add phyBOARD-Segin-i.MX91 support 2025-10-21 9:50 ` Marc Kleine-Budde @ 2025-10-21 10:07 ` Primoz Fiser 2025-10-21 10:13 ` Marc Kleine-Budde 0 siblings, 1 reply; 7+ messages in thread From: Primoz Fiser @ 2025-10-21 10:07 UTC (permalink / raw) To: Marc Kleine-Budde Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, devicetree, upstream, linux-kernel, linux-arm-kernel, imx Hi Marc, On 21. 10. 25 11:50, Marc Kleine-Budde wrote: > On 21.10.2025 11:37:04, Primoz Fiser wrote: >> Add initial support for the PHYTEC phyBOARD-Segin-i.MX91 board [1] based >> on the PHYTEC phyCORE-i.MX91 SoM (System-on-Module) [2]. >> >> Supported features: >> * Audio >> * CAN >> * eMMC >> * Ethernet >> * I2C >> * RTC >> * SD-Card >> * UART >> * USB >> >> For more details see the product pages for the development board and the >> SoM: >> >> [1] https://www.phytec.eu/en/produkte/development-kits/phyboard-segin-kit/ >> [2] https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ >> >> Signed-off-by: Primoz Fiser <primoz.fiser@norik.com> >> --- >> arch/arm64/boot/dts/freescale/Makefile | 1 + >> .../dts/freescale/imx91-phyboard-segin.dts | 344 ++++++++++++++++++ >> .../boot/dts/freescale/imx91-phycore-som.dtsi | 304 ++++++++++++++++ >> 3 files changed, 649 insertions(+) >> create mode 100644 arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts >> create mode 100644 arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi >> >> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile >> index 525ef180481d..34a81d34de39 100644 >> --- a/arch/arm64/boot/dts/freescale/Makefile >> +++ b/arch/arm64/boot/dts/freescale/Makefile >> @@ -344,6 +344,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqps-mb-smarc-2.dtb >> dtb-$(CONFIG_ARCH_MXC) += imx8ulp-9x9-evk.dtb >> dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb >> dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-evk.dtb >> +dtb-$(CONFIG_ARCH_MXC) += imx91-phyboard-segin.dtb >> dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca.dtb >> dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb >> >> diff --git a/arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts >> new file mode 100644 >> index 000000000000..bb631439f9cf >> --- /dev/null >> +++ b/arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts >> @@ -0,0 +1,344 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) >> +/* >> + * Copyright (C) 2025 PHYTEC Messtechnik GmbH >> + * Author: Christoph Stoidner <c.stoidner@phytec.de> >> + * >> + * Product homepage: >> + * phyBOARD-Segin carrier board is reused for the i.MX91 design. >> + * https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/ >> + */ >> +/dts-v1/; >> + >> +#include "imx91-phycore-som.dtsi" >> + >> +/{ >> + model = "PHYTEC phyBOARD-Segin-i.MX91"; >> + compatible = "phytec,imx91-phyboard-segin", "phytec,imx91-phycore-som", >> + "fsl,imx91"; >> + >> + aliases { >> + ethernet1 = &eqos; >> + gpio0 = &gpio1; >> + gpio1 = &gpio2; >> + gpio2 = &gpio3; >> + gpio3 = &gpio4; >> + i2c0 = &lpi2c1; >> + i2c1 = &lpi2c2; >> + mmc0 = &usdhc1; >> + mmc1 = &usdhc2; >> + rtc0 = &i2c_rtc; >> + rtc1 = &bbnsm_rtc; >> + serial0 = &lpuart1; >> + }; >> + >> + chosen { >> + stdout-path = &lpuart1; >> + }; >> + >> + flexcan1_tc: can-phy0 { >> + compatible = "ti,tcan1043"; >> + #phy-cells = <0>; >> + max-bitrate = <1000000>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_flexcan1_tc>; >> + enable-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; >> + }; > > I think the tcan1043 is a CAN-FD transceiver. According to the datasheet > it support 2 MBit/s and 5 MBit/s in the "G" variant. However due to the > board layout, etc, the actual bit rate might still be limited to 1 > MBit/s. Ask the HW engineers if in doubt. phyBOARD-Segin actually uses a TI SN65HVD234D CAN transceiver chip which supports up to 1MBps. See [1]. However since there is no direct support for SN65HVD234D we model the enable signal with the generic PHY driver and use "ti,tcan1043" jsut as compatible. Suggested by Frank and you in [2]. [1] https://lore.kernel.org/all/20250415043311.3385835-12-primoz.fiser@norik.com/ [2] https://lore.kernel.org/all/1571414e-5e7d-4c9e-b69d-11a6fdf454e2@norik.com/ BR, Primoz > > regards, > Marc > -- Primoz Fiser phone: +386-41-390-545 email: primoz.fiser@norik.com -- Norik systems d.o.o. Your embedded software partner Slovenia, EU phone: +386-41-540-545 email: info@norik.com ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] arm64: dts: freescale: Add phyBOARD-Segin-i.MX91 support 2025-10-21 10:07 ` Primoz Fiser @ 2025-10-21 10:13 ` Marc Kleine-Budde 0 siblings, 0 replies; 7+ messages in thread From: Marc Kleine-Budde @ 2025-10-21 10:13 UTC (permalink / raw) To: Primoz Fiser Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, devicetree, upstream, linux-kernel, linux-arm-kernel, imx [-- Attachment #1: Type: text/plain, Size: 1329 bytes --] On 21.10.2025 12:07:13, Primoz Fiser wrote: > >> + flexcan1_tc: can-phy0 { > >> + compatible = "ti,tcan1043"; > >> + #phy-cells = <0>; > >> + max-bitrate = <1000000>; > >> + pinctrl-names = "default"; > >> + pinctrl-0 = <&pinctrl_flexcan1_tc>; > >> + enable-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; > >> + }; > > > > I think the tcan1043 is a CAN-FD transceiver. According to the datasheet > > it support 2 MBit/s and 5 MBit/s in the "G" variant. However due to the > > board layout, etc, the actual bit rate might still be limited to 1 > > MBit/s. Ask the HW engineers if in doubt. > > phyBOARD-Segin actually uses a TI SN65HVD234D CAN transceiver chip which > supports up to 1MBps. See [1]. > > However since there is no direct support for SN65HVD234D we model the > enable signal with the generic PHY driver and use "ti,tcan1043" jsut as > compatible. Suggested by Frank and you in [2]. hmmm, okay - I suggest to add a comment that mentions the actual transceiver and that it's a 1 MBit/s CAN-CC transceiver. regards, Marc -- Pengutronix e.K. | Marc Kleine-Budde | Embedded Linux | https://www.pengutronix.de | Vertretung Nürnberg | Phone: +49-5121-206917-129 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-9 | [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 488 bytes --] ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Upstream] [PATCH 2/2] arm64: dts: freescale: Add phyBOARD-Segin-i.MX91 support 2025-10-21 9:37 ` [PATCH 2/2] arm64: dts: freescale: Add phyBOARD-Segin-i.MX91 support Primoz Fiser 2025-10-21 9:50 ` Marc Kleine-Budde @ 2025-10-22 9:43 ` Teresa Remmet 1 sibling, 0 replies; 7+ messages in thread From: Teresa Remmet @ 2025-10-22 9:43 UTC (permalink / raw) To: kernel@pengutronix.de, s.hauer@pengutronix.de, festevam@gmail.com, robh@kernel.org, shawnguo@kernel.org, krzk+dt@kernel.org, Primoz Fiser, conor+dt@kernel.org Cc: imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, upstream@lists.phytec.de Hello Primoz, Am Dienstag, dem 21.10.2025 um 11:37 +0200 schrieb Primoz Fiser: > Add initial support for the PHYTEC phyBOARD-Segin-i.MX91 board [1] > based > on the PHYTEC phyCORE-i.MX91 SoM (System-on-Module) [2]. > > Supported features: > * Audio > * CAN > * eMMC > * Ethernet > * I2C > * RTC > * SD-Card > * UART > * USB > > For more details see the product pages for the development board and > the > SoM: > > [1] > https://www.phytec.eu/en/produkte/development-kits/phyboard-segin-kit/ > [2] > https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ > > Signed-off-by: Primoz Fiser <primoz.fiser@norik.com> > --- > arch/arm64/boot/dts/freescale/Makefile | 1 + > .../dts/freescale/imx91-phyboard-segin.dts | 344 > ++++++++++++++++++ > .../boot/dts/freescale/imx91-phycore-som.dtsi | 304 ++++++++++++++++ > 3 files changed, 649 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/imx91-phyboard- > segin.dts > create mode 100644 arch/arm64/boot/dts/freescale/imx91-phycore- > som.dtsi > > diff --git a/arch/arm64/boot/dts/freescale/Makefile > b/arch/arm64/boot/dts/freescale/Makefile > index 525ef180481d..34a81d34de39 100644 > --- a/arch/arm64/boot/dts/freescale/Makefile > +++ b/arch/arm64/boot/dts/freescale/Makefile > @@ -344,6 +344,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqps-mb- > smarc-2.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8ulp-9x9-evk.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb > dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-evk.dtb > +dtb-$(CONFIG_ARCH_MXC) += imx91-phyboard-segin.dtb > dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca.dtb > dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb > > diff --git a/arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts > b/arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts > new file mode 100644 > index 000000000000..bb631439f9cf > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts > @@ -0,0 +1,344 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2025 PHYTEC Messtechnik GmbH > + * Author: Christoph Stoidner <c.stoidner@phytec.de> > + * > + * Product homepage: > + * phyBOARD-Segin carrier board is reused for the i.MX91 design. > + * > https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/ > + */ > +/dts-v1/; > + > +#include "imx91-phycore-som.dtsi" > + > +/{ > + model = "PHYTEC phyBOARD-Segin-i.MX91"; > + compatible = "phytec,imx91-phyboard-segin", "phytec,imx91- > phycore-som", > + "fsl,imx91"; > + > + aliases { > + ethernet1 = &eqos; > + gpio0 = &gpio1; > + gpio1 = &gpio2; > + gpio2 = &gpio3; > + gpio3 = &gpio4; > + i2c0 = &lpi2c1; > + i2c1 = &lpi2c2; > + mmc0 = &usdhc1; > + mmc1 = &usdhc2; > + rtc0 = &i2c_rtc; > + rtc1 = &bbnsm_rtc; > + serial0 = &lpuart1; > + }; > + > + chosen { > + stdout-path = &lpuart1; > + }; > + > + flexcan1_tc: can-phy0 { > + compatible = "ti,tcan1043"; > + #phy-cells = <0>; > + max-bitrate = <1000000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_flexcan1_tc>; > + enable-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; > + }; > + > + reg_sound_1v8: regulator-sound-1v8 { > + compatible = "regulator-fixed"; > + regulator-max-microvolt = <1800000>; > + regulator-min-microvolt = <1800000>; > + regulator-name = "VCC1V8_AUDIO"; > + }; > + > + reg_sound_3v3: regulator-sound-3v3 { > + compatible = "regulator-fixed"; > + regulator-max-microvolt = <3300000>; > + regulator-min-microvolt = <3300000>; > + regulator-name = "VCC3V3_ANALOG"; > + }; > + > + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { > + compatible = "regulator-fixed"; > + regulator-name = "USB_OTG1_VBUS"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; Set max value first to be consistent. Same for some other regulators. Check the SoM dsti, too. Teresa > + regulator-always-on; > + }; > + > + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { > + compatible = "regulator-fixed"; > + regulator-name = "USB_OTG2_VBUS"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + regulator-always-on; > + }; > + > + reg_usdhc2_vmmc: regulator-usdhc2 { > + compatible = "regulator-fixed"; > + enable-active-high; > + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-name = "VCC_SD"; > + }; > + > + sound: sound { > + compatible = "simple-audio-card"; > + simple-audio-card,name = "phyBOARD-Segin- > TLV320AIC3007"; > + simple-audio-card,format = "i2s"; > + simple-audio-card,bitclock-master = > <&dailink_master>; > + simple-audio-card,frame-master = <&dailink_master>; > + simple-audio-card,widgets = > + "Line", "Line In", > + "Line", "Line Out", > + "Speaker", "Speaker"; > + simple-audio-card,routing = > + "Line Out", "LLOUT", > + "Line Out", "RLOUT", > + "Speaker", "SPOP", > + "Speaker", "SPOM", > + "LINE1L", "Line In", > + "LINE1R", "Line In"; > + > + simple-audio-card,cpu { > + sound-dai = <&sai1>; > + }; > + > + dailink_master: simple-audio-card,codec { > + sound-dai = <&audio_codec>; > + clocks = <&clk IMX93_CLK_SAI1>; > + }; > + }; > +}; > + > +/* Ethernet */ > +&eqos { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_eqos>; > + phy-mode = "rmii"; > + phy-handle = <ðphy2>; > + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, > + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; > + assigned-clock-rates = <100000000>, <50000000>; > + status = "okay"; > +}; > + > +&mdio { > + ethphy2: ethernet-phy@2 { > + compatible = "ethernet-phy-id0022.1561"; > + reg = <2>; > + clocks = <&clk IMX91_CLK_ENET2_REGULAR>; > + clock-names = "rmii-ref"; > + micrel,led-mode = <1>; > + }; > +}; > + > +/* CAN */ > +&flexcan1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_flexcan1>; > + phys = <&flexcan1_tc>; > + status = "okay"; > +}; > + > +/* I2C2 */ > +&lpi2c2 { > + clock-frequency = <400000>; > + pinctrl-names = "default", "gpio"; > + pinctrl-0 = <&pinctrl_lpi2c2>; > + pinctrl-1 = <&pinctrl_lpi2c2_gpio>; > + scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; > + sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; > + status = "okay"; > + > + /* Codec */ > + audio_codec: audio-codec@18 { > + compatible = "ti,tlv320aic3007"; > + reg = <0x18>; > + #sound-dai-cells = <0>; > + AVDD-supply = <®_sound_3v3>; > + IOVDD-supply = <®_sound_3v3>; > + DRVDD-supply = <®_sound_3v3>; > + DVDD-supply = <®_sound_1v8>; > + }; > + > + /* RTC */ > + i2c_rtc: rtc@68 { > + compatible = "microcrystal,rv4162"; > + reg = <0x68>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_rtc>; > + interrupt-parent = <&gpio4>; > + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; > + }; > +}; > + > +/* Console */ > +&lpuart1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart1>; > + status = "okay"; > +}; > + > +/* Audio */ > +&sai1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_sai1>; > + assigned-clocks = <&clk IMX93_CLK_SAI1>; > + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; > + assigned-clock-rates = <19200000>; > + fsl,sai-mclk-direction-output; > + status = "okay"; > +}; > + > +/* USB */ > +&usbphynop1 { > + vbus-supply = <®_usb_otg1_vbus>; > +}; > + > +&usbphynop2 { > + vbus-supply = <®_usb_otg2_vbus>; > +}; > + > +&usbotg1 { > + disable-over-current; > + dr_mode = "otg"; > + status = "okay"; > +}; > + > +&usbotg2 { > + disable-over-current; > + dr_mode = "host"; > + status = "okay"; > +}; > + > +/* SD-Card */ > +&usdhc2 { > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > + pinctrl-0 = <&pinctrl_usdhc2_default>, <&pinctrl_usdhc2_cd>; > + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; > + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; > + bus-width = <4>; > + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; > + disable-wp; > + no-mmc; > + no-sdio; > + vmmc-supply = <®_usdhc2_vmmc>; > + status = "okay"; > +}; > + > +&iomuxc { > + pinctrl_eqos: eqosgrp { > + fsl,pins = < > + MX91_PAD_ENET1_TD2__ENET_QOS_CLOCK_GENERATE_C > LK 0x4000050e > + MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 > 0x57e > + MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 > 0x57e > + MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 > 0x50e > + MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 > 0x50e > + MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL > 0x57e > + MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL > 0x50e > + MX91_PAD_ENET1_RXC__ENET_QOS_RX_ER > 0x57e > + >; > + }; > + > + pinctrl_flexcan1: flexcan1grp { > + fsl,pins = < > + MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139 > e > + MX91_PAD_PDM_CLK__CAN1_TX 0x139 > e > + >; > + }; > + > + pinctrl_flexcan1_tc: flexcan1tcgrp { > + fsl,pins = < > + MX91_PAD_ENET2_TD3__GPIO4_IO16 0x31e > + >; > + }; > + > + pinctrl_lpi2c2: lpi2c2grp { > + fsl,pins = < > + MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x400 > 00b9e > + MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x400 > 00b9e > + >; > + }; > + > + pinctrl_lpi2c2_gpio: lpi2c2gpiogrp { > + fsl,pins = < > + MX91_PAD_I2C2_SCL__GPIO1_IO2 0x31e > + MX91_PAD_I2C2_SDA__GPIO1_IO3 0x31e > + >; > + }; > + > + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { > + fsl,pins = < > + MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e > + >; > + }; > + > + pinctrl_rtc: rtcgrp { > + fsl,pins = < > + MX91_PAD_ENET2_RD2__GPIO4_IO26 0x31e > + >; > + }; > + > + pinctrl_sai1: sai1grp { > + fsl,pins = < > + MX91_PAD_UART2_RXD__SAI1_MCLK 0x120 > 2 > + MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x120 > 2 > + MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x120 > 2 > + MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x140 > 2 > + MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x140 > 2 > + >; > + }; > + > + pinctrl_uart1: uart1grp { > + fsl,pins = < > + MX91_PAD_UART1_RXD__LPUART1_RX 0x31e > + MX91_PAD_UART1_TXD__LPUART1_TX 0x30e > + >; > + }; > + > + pinctrl_usdhc2_cd: usdhc2cdgrp { > + fsl,pins = < > + MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e > + >; > + }; > + > + pinctrl_usdhc2_default: usdhc2grp { > + fsl,pins = < > + MX91_PAD_SD2_CLK__USDHC2_CLK 0x158 > e > + MX91_PAD_SD2_CMD__USDHC2_CMD 0x138 > 2 > + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138 > 6 > + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138 > e > + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x139 > e > + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x139 > e > + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e > + >; > + }; > + > + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { > + fsl,pins = < > + MX91_PAD_SD2_CLK__USDHC2_CLK 0x159 > e > + MX91_PAD_SD2_CMD__USDHC2_CMD 0x139 > e > + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138 > e > + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138 > e > + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x139 > e > + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x139 > e > + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e > + >; > + }; > + > + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { > + fsl,pins = < > + MX91_PAD_SD2_CLK__USDHC2_CLK 0x158 > e > + MX91_PAD_SD2_CMD__USDHC2_CMD 0x138 > e > + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x139 > e > + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x139 > e > + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x139 > e > + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x139 > e > + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e > + >; > + }; > +}; > diff --git a/arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi > b/arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi > new file mode 100644 > index 000000000000..0d9310f86f45 > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi > @@ -0,0 +1,304 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2025 PHYTEC Messtechnik GmbH > + * Author: Christoph Stoidner <c.stoidner@phytec.de> > + * > + * Product homepage: > + * > https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ > + */ > + > +#include <dt-bindings/leds/common.h> > + > +#include "imx91.dtsi" > + > +/ { > + model = "PHYTEC phyCORE-i.MX91"; > + compatible = "phytec,imx91-phycore-som", "fsl,imx91"; > + > + aliases { > + ethernet0 = &fec; > + }; > + > + reserved-memory { > + ranges; > + #address-cells = <2>; > + #size-cells = <2>; > + > + linux,cma { > + compatible = "shared-dma-pool"; > + reusable; > + alloc-ranges = <0 0x80000000 0 0x40000000>; > + size = <0 0x10000000>; > + linux,cma-default; > + }; > + }; > + > + leds { > + compatible = "gpio-leds"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_leds>; > + > + led-0 { > + color = <LED_COLOR_ID_GREEN>; > + function = LED_FUNCTION_HEARTBEAT; > + gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; > + linux,default-trigger = "heartbeat"; > + }; > + }; > + > + reg_vdda_1v8: regulator-vdda-1v8 { > + compatible = "regulator-fixed"; > + regulator-name = "VDDA_1V8"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + vin-supply = <&buck5>; > + }; > +}; > + > +/* ADC */ > +&adc1 { > + vref-supply = <®_vdda_1v8>; > +}; > + > +/* Ethernet */ > +&fec { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_fec>; > + phy-mode = "rmii"; > + phy-handle = <ðphy1>; > + > + assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>, > + <&clk IMX91_CLK_ENET2_REGULAR>; > + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, > + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; > + assigned-clock-rates = <100000000>, <50000000>; > + status = "okay"; > + > + mdio: mdio { > + clock-frequency = <5000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + ethphy1: ethernet-phy@1 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <1>; > + reset-gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; > + reset-assert-us = <30>; > + }; > + }; > +}; > + > +/* I2C3 */ > +&lpi2c3 { > + clock-frequency = <400000>; > + pinctrl-names = "default", "gpio"; > + pinctrl-0 = <&pinctrl_lpi2c3>; > + pinctrl-1 = <&pinctrl_lpi2c3_gpio>; > + scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; > + sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; > + status = "okay"; > + > + pmic@25 { > + compatible = "nxp,pca9451a"; > + reg = <0x25>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pmic>; > + interrupt-parent = <&gpio4>; > + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; > + > + regulators { > + buck1: BUCK1 { > + regulator-name = "VDD_SOC"; > + regulator-min-microvolt = <610000>; > + regulator-max-microvolt = <950000>; > + regulator-boot-on; > + regulator-always-on; > + regulator-ramp-delay = <3125>; > + }; > + > + buck2: BUCK2 { > + regulator-name = "VDDQ_0V6"; > + regulator-min-microvolt = <600000>; > + regulator-max-microvolt = <600000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + buck4: BUCK4 { > + regulator-name = "VDD_3V3_BUCK"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + buck5: BUCK5 { > + regulator-name = "VDD_1V8"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + buck6: BUCK6 { > + regulator-name = "VDD_1V1"; > + regulator-min-microvolt = <1100000>; > + regulator-max-microvolt = <1100000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + ldo1: LDO1 { > + regulator-name = "PMIC_SNVS_1V8"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + ldo4: LDO4 { > + regulator-name = "VDD_0V8"; > + regulator-min-microvolt = <800000>; > + regulator-max-microvolt = <800000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + ldo5: LDO5 { > + regulator-name = "NVCC_SD2"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <3300000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + }; > + }; > + > + /* EEPROM */ > + eeprom@50 { > + compatible = "atmel,24c32"; > + reg = <0x50>; > + pagesize = <32>; > + vcc-supply = <&buck4>; > + }; > +}; > + > +/* eMMC */ > +&usdhc1 { > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > + pinctrl-0 = <&pinctrl_usdhc1>; > + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; > + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; > + bus-width = <8>; > + non-removable; > + no-1-8-v; > + status = "okay"; > +}; > + > +/* Watchdog */ > +&wdog3 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_wdog>; > + fsl,ext-reset-output; > + status = "okay"; > +}; > + > +&iomuxc { > + pinctrl_fec: fecgrp { > + fsl,pins = < > + MX91_PAD_ENET2_MDC__ENET2_MDC > 0x50e > + MX91_PAD_ENET2_MDIO__ENET2_MDIO > 0x502 > + /* the three pins below are connected to PHYs > straps, > + * that is what the pull-up/down setting is > for. > + */ > + MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 > 0x37e > + MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 > 0x37e > + MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL > 0x57e > + MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 > 0x50e > + MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 > 0x50e > + MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL > 0x50e > + MX91_PAD_ENET2_TD2__ENET2_TX_CLK2 > 0x4000050e > + MX91_PAD_ENET2_RXC__GPIO4_IO23 > 0x51e > + >; > + }; > + > + pinctrl_leds: ledsgrp { > + fsl,pins = < > + MX91_PAD_I2C1_SDA__GPIO1_IO1 0x11e > + >; > + }; > + > + pinctrl_lpi2c3: lpi2c3grp { > + fsl,pins = < > + MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x400 > 00b9e > + MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x400 > 00b9e > + >; > + }; > + > + pinctrl_lpi2c3_gpio: lpi2c3gpiogrp { > + fsl,pins = < > + MX91_PAD_GPIO_IO28__GPIO2_IO28 0x31e > + MX91_PAD_GPIO_IO29__GPIO2_IO29 0x31e > + >; > + }; > + > + pinctrl_pmic: pmicgrp { > + fsl,pins = < > + MX91_PAD_ENET2_RD3__GPIO4_IO27 0x31e > + >; > + }; > + > + pinctrl_usdhc1: usdhc1grp { > + fsl,pins = < > + MX91_PAD_SD1_CLK__USDHC1_CLK 0x179 > e > + MX91_PAD_SD1_CMD__USDHC1_CMD 0x138 > 6 > + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138 > e > + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138 > 6 > + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138 > e > + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138 > 6 > + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x138 > 6 > + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x138 > 6 > + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138 > 6 > + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138 > 6 > + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x179 > e > + >; > + }; > + > + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { > + fsl,pins = < > + MX91_PAD_SD1_CLK__USDHC1_CLK 0x17b > e > + MX91_PAD_SD1_CMD__USDHC1_CMD 0x139 > e > + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138 > e > + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x139 > e > + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13b > e > + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x139 > e > + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x139 > e > + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x139 > e > + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x139 > e > + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x139 > e > + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x179 > e > + >; > + }; > + > + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { > + fsl,pins = < > + MX91_PAD_SD1_CLK__USDHC1_CLK 0x17b > e > + MX91_PAD_SD1_CMD__USDHC1_CMD 0x139 > e > + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x139 > e > + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13b > e > + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13b > e > + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13b > e > + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13b > e > + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13b > e > + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13b > e > + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13b > e > + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x179 > e > + >; > + }; > + > + pinctrl_wdog: wdoggrp { > + fsl,pins = < > + MX91_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e > + >; > + }; > +}; -- PHYTEC Messtechnik GmbH | Barcelona-Allee 1 | 55129 Mainz, Germany Geschäftsführer: Dipl.-Ing. Michael Mitezki, Dipl.-Ing. Bodo Huber, Dipl.-Ing. (FH) Markus Lickes | Handelsregister Mainz HRB 4656 | Finanzamt Mainz | St.Nr. 26/665/00608, DE 149059855 ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] dt-bindings: arm: fsl: Add PHYTEC phyBOARD-Segin-i.MX91 board 2025-10-21 9:37 [PATCH 1/2] dt-bindings: arm: fsl: Add PHYTEC phyBOARD-Segin-i.MX91 board Primoz Fiser 2025-10-21 9:37 ` [PATCH 2/2] arm64: dts: freescale: Add phyBOARD-Segin-i.MX91 support Primoz Fiser @ 2025-10-22 17:39 ` Conor Dooley 1 sibling, 0 replies; 7+ messages in thread From: Conor Dooley @ 2025-10-22 17:39 UTC (permalink / raw) To: Primoz Fiser Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, devicetree, linux-kernel, imx, linux-arm-kernel, upstream [-- Attachment #1: Type: text/plain, Size: 331 bytes --] On Tue, Oct 21, 2025 at 11:37:03AM +0200, Primoz Fiser wrote: > Add device-tree bindings for PHYTEC phyBOARD-Segin-i.MX91 board based on > the PHYTEC phyCORE-i.MX91 SoM (System-on-Module). > > Signed-off-by: Primoz Fiser <primoz.fiser@norik.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> pw-bot: not-applicable [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2025-10-22 17:39 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-10-21 9:37 [PATCH 1/2] dt-bindings: arm: fsl: Add PHYTEC phyBOARD-Segin-i.MX91 board Primoz Fiser 2025-10-21 9:37 ` [PATCH 2/2] arm64: dts: freescale: Add phyBOARD-Segin-i.MX91 support Primoz Fiser 2025-10-21 9:50 ` Marc Kleine-Budde 2025-10-21 10:07 ` Primoz Fiser 2025-10-21 10:13 ` Marc Kleine-Budde 2025-10-22 9:43 ` [Upstream] " Teresa Remmet 2025-10-22 17:39 ` [PATCH 1/2] dt-bindings: arm: fsl: Add PHYTEC phyBOARD-Segin-i.MX91 board Conor Dooley
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