From: Jacky Chou <jacky_chou@aspeedtech.com>
To: <lpieralisi@kernel.org>, <kwilczynski@kernel.org>,
<mani@kernel.org>, <robh@kernel.org>, <bhelgaas@google.com>,
<krzk+dt@kernel.org>, <conor+dt@kernel.org>, <joel@jms.id.au>,
<andrew@codeconstruct.com.au>, <vkoul@kernel.org>,
<kishon@kernel.org>, <linus.walleij@linaro.org>,
<p.zabel@pengutronix.de>, <linux-aspeed@lists.ozlabs.org>,
<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <linux-phy@lists.infradead.org>,
<openbmc@lists.ozlabs.org>, <linux-gpio@vger.kernel.org>
Cc: <jacky_chou@aspeedtech.com>
Subject: [PATCH v4 5/9] ARM: dts: aspeed-g6: Add PCIe RC and PCIe PHY node
Date: Mon, 27 Oct 2025 17:58:21 +0800 [thread overview]
Message-ID: <20251027095825.181161-6-jacky_chou@aspeedtech.com> (raw)
In-Reply-To: <20251027095825.181161-1-jacky_chou@aspeedtech.com>
The AST2600 has one PCIe RC and add the PCIe PHY for RC.
Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
---
arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 54 +++++++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
index f8662c8ac089..916e68fedc5a 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
@@ -379,6 +379,60 @@ rng: hwrng@1e6e2524 {
quality = <100>;
};
+ pcie_phy1: phy@1e6ed200 {
+ compatible = "aspeed,ast2600-pcie-phy";
+ reg = <0x1e6ed200 0x100>;
+ #phy-cells = <0>;
+ };
+
+ pcie0: pcie@1e770000 {
+ compatible = "aspeed,ast2600-pcie";
+ device_type = "pci";
+ reg = <0x1e770000 0x100>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ bus-range = <0x00 0xff>;
+
+ ranges = <0x01000000 0x0 0x00018000 0x00018000 0x0 0x00008000
+ 0x02000000 0x0 0x60000000 0x60000000 0x0 0x20000000>;
+
+ status = "disabled";
+
+ resets = <&syscon ASPEED_RESET_H2X>;
+ reset-names = "h2x";
+ pinctrl-0 = <&pinctrl_pcierc1_default>;
+ pinctrl-names = "default";
+
+ #interrupt-cells = <1>;
+ msi-controller;
+
+ aspeed,ahbc = <&ahbc>;
+
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+ <0 0 0 2 &pcie_intc0 1>,
+ <0 0 0 3 &pcie_intc0 2>,
+ <0 0 0 4 &pcie_intc0 3>;
+ pcie_intc0: legacy-interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+
+ pcie@8,0 {
+ reg = <0x804000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ resets = <&syscon ASPEED_RESET_PCIE_RC_O>;
+ reset-names = "perst";
+ clocks = <&syscon ASPEED_CLK_GATE_BCLK>;
+ phys = <&pcie_phy1>;
+ ranges;
+ };
+ };
+
gfx: display@1e6e6000 {
compatible = "aspeed,ast2600-gfx", "syscon";
reg = <0x1e6e6000 0x1000>;
--
2.34.1
next prev parent reply other threads:[~2025-10-27 9:58 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-27 9:58 [PATCH v4 0/9] Add ASPEED PCIe Root Complex support Jacky Chou
2025-10-27 9:58 ` [PATCH v4 1/9] dt-bindings: phy: aspeed: Add ASPEED PCIe PHY Jacky Chou
2025-10-27 9:58 ` [PATCH v4 2/9] dt-bindings: PCI: Add ASPEED PCIe RC support Jacky Chou
2025-10-28 13:46 ` Bjorn Helgaas
2025-10-29 5:43 ` Jacky Chou
2025-10-27 9:58 ` [PATCH v4 3/9] dt-bindings: pinctrl: aspeed,ast2600-pinctrl: Add PCIe RC PERST# group Jacky Chou
2025-10-27 9:58 ` [PATCH v4 4/9] ARM: dts: aspeed-g6: Add AST2600 PCIe RC PERST# Jacky Chou
2025-10-28 7:53 ` Krzysztof Kozlowski
2025-10-28 8:41 ` Jacky Chou
2025-10-27 9:58 ` Jacky Chou [this message]
2025-10-27 9:58 ` [PATCH v4 6/9] PHY: aspeed: Add ASPEED PCIe PHY driver Jacky Chou
2025-10-27 9:58 ` [PATCH v4 7/9] PCI: Add FMT, TYPE and CPL status definition for TLP header Jacky Chou
2025-10-27 9:58 ` [PATCH v4 8/9] PCI: aspeed: Add ASPEED PCIe RC driver Jacky Chou
2025-10-28 5:27 ` kernel test robot
2025-10-28 14:22 ` kernel test robot
2025-10-28 17:13 ` Bjorn Helgaas
2025-10-30 5:53 ` 回覆: " Jacky Chou
2025-10-27 9:58 ` [PATCH v4 9/9] MAINTAINERS: " Jacky Chou
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