* [PATCH v9 1/3] dt-bindings: PCI: dwc: Add external reference clock input
2025-10-31 3:19 [PATCH v9 0/3] PCI: imx6: Add external reference clock mode support Richard Zhu
@ 2025-10-31 3:19 ` Richard Zhu
2025-10-31 3:19 ` [PATCH v9 2/3] dt-bindings: PCI: pci-imx6: " Richard Zhu
2025-10-31 3:19 ` [PATCH v9 3/3] PCI: imx6: Add external reference clock input mode support Richard Zhu
2 siblings, 0 replies; 6+ messages in thread
From: Richard Zhu @ 2025-10-31 3:19 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, bhelgaas, frank.li, l.stach, lpieralisi,
kwilczynski, mani, shawnguo, s.hauer, kernel, festevam
Cc: linux-pci, linux-arm-kernel, devicetree, imx, linux-kernel,
Richard Zhu, Frank Li, Conor Dooley
Add external reference clock input "extref" for a reference clock that
comes from external crystal oscillator.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
.../devicetree/bindings/pci/snps,dw-pcie-common.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
index 34594972d8dbe..0134a759185ec 100644
--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
+++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
@@ -105,6 +105,12 @@ properties:
define it with this name (for instance pipe, core and aux can
be connected to a single source of the periodic signal).
const: ref
+ - description:
+ Some dwc wrappers (like i.MX95 PCIes) have two reference clock
+ inputs, one from an internal PLL, the other from an off-chip crystal
+ oscillator. If present, 'extref' refers to a reference clock from
+ an external oscillator.
+ const: extref
- description:
Clock for the PHY registers interface. Originally this is
a PHY-viewport-based interface, but some platform may have
--
2.37.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v9 2/3] dt-bindings: PCI: pci-imx6: Add external reference clock input
2025-10-31 3:19 [PATCH v9 0/3] PCI: imx6: Add external reference clock mode support Richard Zhu
2025-10-31 3:19 ` [PATCH v9 1/3] dt-bindings: PCI: dwc: Add external reference clock input Richard Zhu
@ 2025-10-31 3:19 ` Richard Zhu
2025-11-02 16:04 ` Krzysztof Kozlowski
2025-10-31 3:19 ` [PATCH v9 3/3] PCI: imx6: Add external reference clock input mode support Richard Zhu
2 siblings, 1 reply; 6+ messages in thread
From: Richard Zhu @ 2025-10-31 3:19 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, bhelgaas, frank.li, l.stach, lpieralisi,
kwilczynski, mani, shawnguo, s.hauer, kernel, festevam
Cc: linux-pci, linux-arm-kernel, devicetree, imx, linux-kernel,
Richard Zhu, Frank Li
i.MX95 PCIes have two reference clock inputs: one from internal PLL, the
other from off chip crystal oscillator. The "extref" clock refers to a
reference clock from an external crystal oscillator.
Add external reference clock input for i.MX95 PCIes.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
index ca5f2970f217c..703c776d28e6f 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
@@ -44,7 +44,7 @@ properties:
clock-names:
minItems: 3
- maxItems: 5
+ maxItems: 6
interrupts:
minItems: 1
@@ -212,14 +212,17 @@ allOf:
then:
properties:
clocks:
- maxItems: 5
+ minItems: 4
+ maxItems: 6
clock-names:
+ minItems: 4
items:
- const: pcie
- const: pcie_bus
- const: pcie_phy
- const: pcie_aux
- const: ref
+ - const: extref # Optional
unevaluatedProperties: false
--
2.37.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v9 2/3] dt-bindings: PCI: pci-imx6: Add external reference clock input
2025-10-31 3:19 ` [PATCH v9 2/3] dt-bindings: PCI: pci-imx6: " Richard Zhu
@ 2025-11-02 16:04 ` Krzysztof Kozlowski
2025-11-04 9:02 ` Hongxing Zhu
0 siblings, 1 reply; 6+ messages in thread
From: Krzysztof Kozlowski @ 2025-11-02 16:04 UTC (permalink / raw)
To: Richard Zhu
Cc: robh, krzk+dt, conor+dt, bhelgaas, frank.li, l.stach, lpieralisi,
kwilczynski, mani, shawnguo, s.hauer, kernel, festevam, linux-pci,
linux-arm-kernel, devicetree, imx, linux-kernel
On Fri, Oct 31, 2025 at 11:19:06AM +0800, Richard Zhu wrote:
> i.MX95 PCIes have two reference clock inputs: one from internal PLL, the
> other from off chip crystal oscillator. The "extref" clock refers to a
> reference clock from an external crystal oscillator.
>
> Add external reference clock input for i.MX95 PCIes.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> Reviewed-by: Frank Li <Frank.Li@nxp.com>
> ---
> Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> index ca5f2970f217c..703c776d28e6f 100644
> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> @@ -44,7 +44,7 @@ properties:
>
> clock-names:
> minItems: 3
> - maxItems: 5
> + maxItems: 6
>
> interrupts:
> minItems: 1
> @@ -212,14 +212,17 @@ allOf:
> then:
> properties:
> clocks:
> - maxItems: 5
> + minItems: 4
> + maxItems: 6
> clock-names:
> + minItems: 4
> items:
> - const: pcie
> - const: pcie_bus
> - const: pcie_phy
> - const: pcie_aux
> - const: ref
This was required last time. Nothing in commit msg explained changing
that.
> + - const: extref # Optional
Drop the comment, do not repeat the schema. And why only this is marked
as optional if 'ref' is optional as well now.
It is v9, can you please really think thoroughly what you are sending,
so obvious issues won't be there?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH v9 2/3] dt-bindings: PCI: pci-imx6: Add external reference clock input
2025-11-02 16:04 ` Krzysztof Kozlowski
@ 2025-11-04 9:02 ` Hongxing Zhu
0 siblings, 0 replies; 6+ messages in thread
From: Hongxing Zhu @ 2025-11-04 9:02 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
bhelgaas@google.com, Frank Li, l.stach@pengutronix.de,
lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org,
shawnguo@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com,
linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org, imx@lists.linux.dev,
linux-kernel@vger.kernel.org
> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: 2025年11月3日 0:05
> To: Hongxing Zhu <hongxing.zhu@nxp.com>
> Cc: robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org;
> bhelgaas@google.com; Frank Li <frank.li@nxp.com>; l.stach@pengutronix.de;
> lpieralisi@kernel.org; kwilczynski@kernel.org; mani@kernel.org;
> shawnguo@kernel.org; s.hauer@pengutronix.de; kernel@pengutronix.de;
> festevam@gmail.com; linux-pci@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org;
> imx@lists.linux.dev; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v9 2/3] dt-bindings: PCI: pci-imx6: Add external reference
> clock input
>
> On Fri, Oct 31, 2025 at 11:19:06AM +0800, Richard Zhu wrote:
> > i.MX95 PCIes have two reference clock inputs: one from internal PLL,
> > the other from off chip crystal oscillator. The "extref" clock refers
> > to a reference clock from an external crystal oscillator.
> >
> > Add external reference clock input for i.MX95 PCIes.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > Reviewed-by: Frank Li <Frank.Li@nxp.com>
> > ---
> > Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 7 +++++--
> > 1 file changed, 5 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > index ca5f2970f217c..703c776d28e6f 100644
> > --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > @@ -44,7 +44,7 @@ properties:
> >
> > clock-names:
> > minItems: 3
> > - maxItems: 5
> > + maxItems: 6
> >
> > interrupts:
> > minItems: 1
> > @@ -212,14 +212,17 @@ allOf:
> > then:
> > properties:
> > clocks:
> > - maxItems: 5
> > + minItems: 4
> > + maxItems: 6
> > clock-names:
> > + minItems: 4
> > items:
> > - const: pcie
> > - const: pcie_bus
> > - const: pcie_phy
> > - const: pcie_aux
> > - const: ref
>
> This was required last time. Nothing in commit msg explained changing that.
>
> > + - const: extref # Optional
>
> Drop the comment, do not repeat the schema. And why only this is marked
> as optional if 'ref' is optional as well now.
Hi Krzysztof:
Thanks for your comments, I know what's the problem in this patch.
Firstly, the minItem and maxItem of i.MX95 PCIe clocks should be 5 and 6.
Because that the "ref" clock is not an optional clock for i.MX95 PCIes.
How about to update the commits as follows?
"
i.MX95 PCIes have two reference clock inputs: one from internal PLL. It's
wired inside chip and present as "ref" clock. It's not an optional clock.
The other from off chip crystal oscillator. The "extref" clock refers to a
reference clock from an external crystal oscillator through the CLKIN_N/P pair
PADs. It is an optional clock, relied on the board design.
Add additional optional external reference clock input for i.MX95 PCIes.
"
Thanks.
Best Regards
Richard Zhu
>
> It is v9, can you please really think thoroughly what you are sending, so
> obvious issues won't be there?
>
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v9 3/3] PCI: imx6: Add external reference clock input mode support
2025-10-31 3:19 [PATCH v9 0/3] PCI: imx6: Add external reference clock mode support Richard Zhu
2025-10-31 3:19 ` [PATCH v9 1/3] dt-bindings: PCI: dwc: Add external reference clock input Richard Zhu
2025-10-31 3:19 ` [PATCH v9 2/3] dt-bindings: PCI: pci-imx6: " Richard Zhu
@ 2025-10-31 3:19 ` Richard Zhu
2 siblings, 0 replies; 6+ messages in thread
From: Richard Zhu @ 2025-10-31 3:19 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, bhelgaas, frank.li, l.stach, lpieralisi,
kwilczynski, mani, shawnguo, s.hauer, kernel, festevam
Cc: linux-pci, linux-arm-kernel, devicetree, imx, linux-kernel,
Richard Zhu, Frank Li
i.MX95 PCIes have two reference clock inputs: one from internal PLL, the
other from off chip crystal oscillator. The "extref" clock refers to a
reference clock from an external crystal oscillator.
Add external reference clock input mode support for i.MX95 PCIes.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 19 ++++++++++++-------
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 4668fc9648bff..a6db1f0f73c36 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -149,6 +149,7 @@ struct imx_pcie {
struct gpio_desc *reset_gpiod;
struct clk_bulk_data *clks;
int num_clks;
+ bool enable_ext_refclk;
struct regmap *iomuxc_gpr;
u16 msi_ctrl;
u32 controller_id;
@@ -241,6 +242,8 @@ static unsigned int imx_pcie_grp_offset(const struct imx_pcie *imx_pcie)
static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
{
+ bool ext = imx_pcie->enable_ext_refclk;
+
/*
* ERR051624: The Controller Without Vaux Cannot Exit L23 Ready
* Through Beacon or PERST# De-assertion
@@ -259,13 +262,12 @@ static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
IMX95_PCIE_PHY_CR_PARA_SEL,
IMX95_PCIE_PHY_CR_PARA_SEL);
- regmap_update_bits(imx_pcie->iomuxc_gpr,
- IMX95_PCIE_PHY_GEN_CTRL,
- IMX95_PCIE_REF_USE_PAD, 0);
- regmap_update_bits(imx_pcie->iomuxc_gpr,
- IMX95_PCIE_SS_RW_REG_0,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_GEN_CTRL,
+ ext ? IMX95_PCIE_REF_USE_PAD : 0,
+ IMX95_PCIE_REF_USE_PAD);
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_0,
IMX95_PCIE_REF_CLKEN,
- IMX95_PCIE_REF_CLKEN);
+ ext ? 0 : IMX95_PCIE_REF_CLKEN);
return 0;
}
@@ -1602,7 +1604,7 @@ static int imx_pcie_probe(struct platform_device *pdev)
struct imx_pcie *imx_pcie;
struct device_node *np;
struct device_node *node = dev->of_node;
- int ret, domain;
+ int i, ret, domain;
u16 val;
imx_pcie = devm_kzalloc(dev, sizeof(*imx_pcie), GFP_KERNEL);
@@ -1653,6 +1655,9 @@ static int imx_pcie_probe(struct platform_device *pdev)
if (imx_pcie->num_clks < 0)
return dev_err_probe(dev, imx_pcie->num_clks,
"failed to get clocks\n");
+ for (i = 0; i < imx_pcie->num_clks; i++)
+ if (strncmp(imx_pcie->clks[i].id, "extref", 6) == 0)
+ imx_pcie->enable_ext_refclk = true;
if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_PHYDRV)) {
imx_pcie->phy = devm_phy_get(dev, "pcie-phy");
--
2.37.1
^ permalink raw reply related [flat|nested] 6+ messages in thread