[PATCH 3/4] clk: imx95-blk-ctl: Add one clock mux for HSIO block

[Xu Yang <xu.yang_2@nxp.com>]

The GPR_REG0 register has an USB_PHY_REF_CLK_SEL (bit 6) to select USB 3.0
PHY reference clock.

USB_PHY_REF_CLK_SEL:
bit[6]   - 0b 24 MHz external oscillator
         - 1b 100 MHz high performance PLL

Add a clock multiplexer to support USB3.0 PHY clock selection.

Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
---
 drivers/clk/imx/clk-imx95-blk-ctl.c | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/imx/clk-imx95-blk-ctl.c b/drivers/clk/imx/clk-imx95-blk-ctl.c
index 3c2019f428c9..ca06eee00e52 100644
--- a/drivers/clk/imx/clk-imx95-blk-ctl.c
+++ b/drivers/clk/imx/clk-imx95-blk-ctl.c
@@ -284,7 +284,7 @@ static const struct imx95_blk_ctl_dev_data netcmix_dev_data = {
 };
 
 static const struct imx95_blk_ctl_clk_dev_data hsio_blk_ctl_clk_dev_data[] = {
-	[0] = {
+	[IMX95_CLK_HSIOMIX_PCIE_CLK_GATE] = {
 		.name = "hsio_pcie_clk_gate",
 		.parent_names = (const char *[]){ "hsio_pll", },
 		.num_parents = 1,
@@ -293,11 +293,21 @@ static const struct imx95_blk_ctl_clk_dev_data hsio_blk_ctl_clk_dev_data[] = {
 		.bit_width = 1,
 		.type = CLK_GATE,
 		.flags = CLK_SET_RATE_PARENT,
-	}
+	},
+	[IMX95_CLK_HSIOMIX_USB_PHY_CLK_SEL] = {
+		.name = "usb_phy_ref_clk_sel",
+		.parent_names = (const char *[]){"osc24m", "hsiopll"},
+		.num_parents = 2,
+		.reg = 0,
+		.bit_idx = 6,
+		.bit_width = 1,
+		.type = CLK_MUX,
+		.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
+	},
 };
 
 static const struct imx95_blk_ctl_dev_data hsio_blk_ctl_dev_data = {
-	.num_clks = 1,
+	.num_clks = ARRAY_SIZE(hsio_blk_ctl_clk_dev_data),
 	.clk_dev_data = hsio_blk_ctl_clk_dev_data,
 	.clk_reg_offset = 0,
 };
-- 
2.34.1