* [PATCH v3 0/3] Add support for Cix Sky1 resets
@ 2025-11-24 6:32 Gary Yang
2025-11-24 6:32 ` [PATCH v3 1/3] dt-bindings: reset: add sky1 reset controller Gary Yang
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Gary Yang @ 2025-11-24 6:32 UTC (permalink / raw)
To: p.zabel, robh, krzk+dt, conor+dt
Cc: devicetree, linux-kernel, linux-arm-kernel, cix-kernel-upstream,
Gary Yang
Patch 1: Add yaml file for Cix Sky1 resets
Patch 2: Add driver codes for Cix Sky1 resets
Patch 3: Add dts nodes for Cix Sky1 resets
v3 changes:
- Pass dts build check with below commands:
make O=$OUTKNL dt_binding_check
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-rst.yaml
scripts/checkpatch.pl 000*.patch
make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb
- remove syscon
v2 changes:
- Pass dts build check with below commands:
make O=$OUTKNL dt_binding_check
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-rst.yaml
scripts/checkpatch.pl 000*.patch
make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb
- fix dt-bindings style
- refine reset driver
Gary Yang (3):
dt-bindings: reset: add sky1 reset controller
reset: cix: add support for cix sky1 resets
arm64: dts: cix: add support for cix sky1 resets
.../bindings/reset/cix,sky1-rst.yaml | 50 ++
arch/arm64/boot/dts/cix/sky1.dtsi | 14 +
drivers/reset/Kconfig | 7 +
drivers/reset/Makefile | 1 +
drivers/reset/reset-sky1.c | 426 ++++++++++++++++++
include/dt-bindings/reset/cix,sky1-rst-fch.h | 42 ++
include/dt-bindings/reset/cix,sky1-rst.h | 164 +++++++
7 files changed, 704 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/cix,sky1-rst.yaml
create mode 100644 drivers/reset/reset-sky1.c
create mode 100644 include/dt-bindings/reset/cix,sky1-rst-fch.h
create mode 100644 include/dt-bindings/reset/cix,sky1-rst.h
--
2.49.0
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3 1/3] dt-bindings: reset: add sky1 reset controller
2025-11-24 6:32 [PATCH v3 0/3] Add support for Cix Sky1 resets Gary Yang
@ 2025-11-24 6:32 ` Gary Yang
2025-11-24 19:54 ` Conor Dooley
2025-11-24 6:32 ` [PATCH v3 2/3] reset: cix: add support for cix sky1 resets Gary Yang
2025-11-24 6:32 ` [PATCH v3 3/3] arm64: dts: " Gary Yang
2 siblings, 1 reply; 9+ messages in thread
From: Gary Yang @ 2025-11-24 6:32 UTC (permalink / raw)
To: p.zabel, robh, krzk+dt, conor+dt
Cc: devicetree, linux-kernel, linux-arm-kernel, cix-kernel-upstream,
Gary Yang
There are two reset controllers on Cix sky1 Soc.
One is located in S0 domain, and the other is located
in S5 domain.
Signed-off-by: Gary Yang <gary.yang@cixtech.com>
---
.../bindings/reset/cix,sky1-rst.yaml | 50 ++++++
include/dt-bindings/reset/cix,sky1-rst-fch.h | 42 +++++
include/dt-bindings/reset/cix,sky1-rst.h | 164 ++++++++++++++++++
3 files changed, 256 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/cix,sky1-rst.yaml
create mode 100644 include/dt-bindings/reset/cix,sky1-rst-fch.h
create mode 100644 include/dt-bindings/reset/cix,sky1-rst.h
diff --git a/Documentation/devicetree/bindings/reset/cix,sky1-rst.yaml b/Documentation/devicetree/bindings/reset/cix,sky1-rst.yaml
new file mode 100644
index 000000000000..a28f938a283d
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/cix,sky1-rst.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/cix,sky1-rst.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: CIX Sky1 Reset Controller
+
+maintainers:
+ - Gary Yang <gary.yang@cixtech.com>
+
+description: |
+ CIX Sky1 reset controller can be used to reset various set of peripherals.
+ There are two reset controllers, one is located in S0 domain, the other
+ is located in S5 domain.
+
+ See also:
+ - include/dt-bindings/reset/cix,sky1-rst.h
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - cix,sky1-rst
+ - cix,sky1-rst-fch
+
+ reg:
+ minItems: 1
+ maxItems: 3
+
+ '#reset-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/reset/cix,sky1-rst.h>
+ reset-controller@16000304 {
+ compatible = "cix,sky1-rst";
+ reg = <0x16000304 0xc>,
+ <0x16000400 0x10>,
+ <0x16000800 0x8>;
+ #reset-cells = <1>;
+ };
diff --git a/include/dt-bindings/reset/cix,sky1-rst-fch.h b/include/dt-bindings/reset/cix,sky1-rst-fch.h
new file mode 100644
index 000000000000..8e67d7eb92aa
--- /dev/null
+++ b/include/dt-bindings/reset/cix,sky1-rst-fch.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/* Author: Jerry Zhu <jerry.zhu@cixtech.com> */
+#ifndef DT_BINDING_RESET_FCH_SKY1_H
+#define DT_BINDING_RESET_FCH_SKY1_H
+
+/* func reset for sky1 fch */
+
+#define SW_I3C0_RST_FUNC_G_N 0
+#define SW_I3C0_RST_FUNC_I_N 1
+#define SW_I3C1_RST_FUNC_G_N 2
+#define SW_I3C1_RST_FUNC_I_N 3
+#define SW_UART0_RST_FUNC_N 4
+#define SW_UART1_RST_FUNC_N 5
+#define SW_UART2_RST_FUNC_N 6
+#define SW_UART3_RST_FUNC_N 7
+#define SW_TIMER_RST_FUNC_N 8
+
+/* apb reset for sky1 fch */
+#define SW_I3C0_RST_APB_N 9
+#define SW_I3C1_RST_APB_N 10
+#define SW_DMA_RST_AXI_N 11
+#define SW_UART0_RST_APB_N 12
+#define SW_UART1_RST_APB_N 13
+#define SW_UART2_RST_APB_N 14
+#define SW_UART3_RST_APB_N 15
+#define SW_SPI0_RST_APB_N 16
+#define SW_SPI1_RST_APB_N 17
+#define SW_I2C0_RST_APB_N 18
+#define SW_I2C1_RST_APB_N 19
+#define SW_I2C2_RST_APB_N 20
+#define SW_I2C3_RST_APB_N 21
+#define SW_I2C4_RST_APB_N 22
+#define SW_I2C5_RST_APB_N 23
+#define SW_I2C6_RST_APB_N 24
+#define SW_I2C7_RST_APB_N 25
+#define SW_GPIO_RST_APB_N 26
+
+/* fch rst for xspi */
+#define SW_XSPI_REG_RST_N 27
+#define SW_XSPI_SYS_RST_N 28
+
+#endif
diff --git a/include/dt-bindings/reset/cix,sky1-rst.h b/include/dt-bindings/reset/cix,sky1-rst.h
new file mode 100644
index 000000000000..2f0990922aad
--- /dev/null
+++ b/include/dt-bindings/reset/cix,sky1-rst.h
@@ -0,0 +1,164 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/* Author: Jerry Zhu <jerry.zhu@cixtech.com> */
+#ifndef DT_BINDING_RESET_SKY1_H
+#define DT_BINDING_RESET_SKY1_H
+
+/* reset for csu_pm */
+
+#define SKY1_CSU_PM_RESET_N 0
+#define SKY1_SENSORFUSION_RESET_N 1
+#define SKY1_SENSORFUSION_NOC_RESET_N 2
+
+/* reset group0 for s0 domain modules */
+#define SKY1_DDRC_RESET_N 3
+#define SKY1_GIC_RESET_N 4
+#define SKY1_CI700_RESET_N 5
+#define SKY1_SYS_NI700_RESET_N 6
+#define SKY1_MM_NI700_RESET_N 7
+#define SKY1_PCIE_NI700_RESET_N 8
+#define SKY1_GPU_RESET_N 9
+#define SKY1_NPUTOP_RESET_N 10
+#define SKY1_NPUCORE0_RESET_N 11
+#define SKY1_NPUCORE1_RESET_N 12
+#define SKY1_NPUCORE2_RESET_N 13
+#define SKY1_VPU_RESET_N 14
+#define SKY1_ISP_SRESET_N 15
+#define SKY1_ISP_ARESET_N 16
+#define SKY1_ISP_HRESET_N 17
+#define SKY1_ISP_GDCRESET_N 18
+#define SKY1_DPU_RESET0_N 19
+#define SKY1_DPU_RESET1_N 20
+#define SKY1_DPU_RESET2_N 21
+#define SKY1_DPU_RESET3_N 22
+#define SKY1_DPU_RESET4_N 23
+#define SKY1_DP_RESET0_N 24
+#define SKY1_DP_RESET1_N 25
+#define SKY1_DP_RESET2_N 26
+#define SKY1_DP_RESET3_N 27
+#define SKY1_DP_RESET4_N 28
+#define SKY1_DP_PHY_RST_N 29
+
+/* reset group1 for s0 domain modules */
+#define SKY1_AUDIO_HIFI5_RESET_N 30
+#define SKY1_AUDIO_HIFI5_NOC_RESET_N 31
+#define SKY1_CSIDPHY_PRST0_N 32
+#define SKY1_CSIDPHY_CMNRST0_N 33
+#define SKY1_CSI0_RST_N 34
+#define SKY1_CSIDPHY_PRST1_N 35
+#define SKY1_CSIDPHY_CMNRST1_N 36
+#define SKY1_CSI1_RST_N 37
+#define SKY1_CSI2_RST_N 38
+#define SKY1_CSI3_RST_N 39
+#define SKY1_CSIBRDGE0_RST_N 40
+#define SKY1_CSIBRDGE1_RST_N 41
+#define SKY1_CSIBRDGE2_RST_N 42
+#define SKY1_CSIBRDGE3_RST_N 43
+#define SKY1_GMAC0_RST_N 44
+#define SKY1_GMAC1_RST_N 45
+#define SKY1_PCIE0_RESET_N 46
+#define SKY1_PCIE1_RESET_N 47
+#define SKY1_PCIE2_RESET_N 48
+#define SKY1_PCIE3_RESET_N 49
+#define SKY1_PCIE4_RESET_N 50
+
+/* reset group1 for usb phys */
+#define SKY1_USB_DP_PHY0_PRST_N 51
+#define SKY1_USB_DP_PHY1_PRST_N 52
+#define SKY1_USB_DP_PHY2_PRST_N 53
+#define SKY1_USB_DP_PHY3_PRST_N 54
+#define SKY1_USB_DP_PHY0_RST_N 55
+#define SKY1_USB_DP_PHY1_RST_N 56
+#define SKY1_USB_DP_PHY2_RST_N 57
+#define SKY1_USB_DP_PHY3_RST_N 58
+#define SKY1_USBPHY_SS_PST_N 59
+#define SKY1_USBPHY_SS_RST_N 60
+#define SKY1_USBPHY_HS0_PRST_N 61
+#define SKY1_USBPHY_HS1_PRST_N 62
+#define SKY1_USBPHY_HS2_PRST_N 63
+#define SKY1_USBPHY_HS3_PRST_N 64
+#define SKY1_USBPHY_HS4_PRST_N 65
+#define SKY1_USBPHY_HS5_PRST_N 66
+#define SKY1_USBPHY_HS6_PRST_N 67
+#define SKY1_USBPHY_HS7_PRST_N 68
+#define SKY1_USBPHY_HS8_PRST_N 69
+#define SKY1_USBPHY_HS9_PRST_N 70
+
+/* reset group1 for usb controllers */
+#define SKY1_USBC_SS0_PRST_N 71
+#define SKY1_USBC_SS1_PRST_N 72
+#define SKY1_USBC_SS2_PRST_N 73
+#define SKY1_USBC_SS3_PRST_N 74
+#define SKY1_USBC_SS4_PRST_N 75
+#define SKY1_USBC_SS5_PRST_N 76
+#define SKY1_USBC_SS0_RST_N 77
+#define SKY1_USBC_SS1_RST_N 78
+#define SKY1_USBC_SS2_RST_N 79
+#define SKY1_USBC_SS3_RST_N 80
+#define SKY1_USBC_SS4_RST_N 81
+#define SKY1_USBC_SS5_RST_N 82
+#define SKY1_USBC_HS0_PRST_N 83
+#define SKY1_USBC_HS1_PRST_N 84
+#define SKY1_USBC_HS2_PRST_N 85
+#define SKY1_USBC_HS3_PRST_N 86
+#define SKY1_USBC_HS0_RST_N 87
+#define SKY1_USBC_HS1_RST_N 88
+#define SKY1_USBC_HS2_RST_N 89
+#define SKY1_USBC_HS3_RST_N 90
+
+/* reset group0 for rcsu */
+#define SKY1_AUDIO_RCSU_RESET_N 91
+#define SKY1_CI700_RCSU_RESET_N 92
+#define SKY1_CSI_RCSU0_RESET_N 93
+#define SKY1_CSI_RCSU1_RESET_N 94
+#define SKY1_CSU_PM_RCSU_RESET_N 95
+#define SKY1_DDR_BROADCAST_RCSU_RESET_N 96
+#define SKY1_DDR_CTRL_RCSU_0_RESET_N 97
+#define SKY1_DDR_CTRL_RCSU_1_RESET_N 98
+#define SKY1_DDR_CTRL_RCSU_2_RESET_N 99
+#define SKY1_DDR_CTRL_RCSU_3_RESET_N 100
+#define SKY1_DDR_TZC400_RCSU_0_RESET_N 101
+#define SKY1_DDR_TZC400_RCSU_1_RESET_N 102
+#define SKY1_DDR_TZC400_RCSU_2_RESET_N 103
+#define SKY1_DDR_TZC400_RCSU_3_RESET_N 104
+#define SKY1_DP0_RCSU_RESET_N 105
+#define SKY1_DP1_RCSU_RESET_N 106
+#define SKY1_DP2_RCSU_RESET_N 107
+#define SKY1_DP3_RCSU_RESET_N 108
+#define SKY1_DP4_RCSU_RESET_N 109
+#define SKY1_DPU0_RCSU_RESET_N 110
+#define SKY1_DPU1_RCSU_RESET_N 111
+#define SKY1_DPU2_RCSU_RESET_N 112
+#define SKY1_DPU3_RCSU_RESET_N 113
+#define SKY1_DPU4_RCSU_RESET_N 114
+#define SKY1_DSU_RCSU_RESET_N 115
+#define SKY1_FCH_RCSU_RESET_N 116
+#define SKY1_GICD_RCSU_RESET_N 117
+#define SKY1_GMAC_RCSU_RESET_N 118
+#define SKY1_GPU_RCSU_RESET_N 119
+#define SKY1_ISP_RCSU0_RESET_N 120
+#define SKY1_ISP_RCSU1_RESET_N 121
+#define SKY1_NI700_MMHUB_RCSU_RESET_N 122
+
+/* reset group1 for rcsu */
+#define SKY1_NPU_RCSU_RESET_N 123
+#define SKY1_NI700_PCIE_RCSU_RESET_N 124
+#define SKY1_PCIE_X421_RCSU_RESET_N 125
+#define SKY1_PCIE_X8_RCSU_RESET_N 126
+#define SKY1_SF_RCSU_RESET_N 127
+#define SKY1_RCSU_SMMU_MMHUB_RESET_N 128
+#define SKY1_RCSU_SMMU_PCIEHUB_RESET_N 129
+#define SKY1_RCSU_SYSHUB_RESET_N 130
+#define SKY1_NI700_SMN_RCSU_RESET_N 131
+#define SKY1_NI700_SYSHUB_RCSU_RESET_N 132
+#define SKY1_RCSU_USB2_HOST0_RESET_N 133
+#define SKY1_RCSU_USB2_HOST1_RESET_N 134
+#define SKY1_RCSU_USB2_HOST2_RESET_N 135
+#define SKY1_RCSU_USB2_HOST3_RESET_N 136
+#define SKY1_RCSU_USB3_TYPEA_DRD_RESET_N 137
+#define SKY1_RCSU_USB3_TYPEC_DRD_RESET_N 138
+#define SKY1_RCSU_USB3_TYPEC_HOST0_RESET_N 139
+#define SKY1_RCSU_USB3_TYPEC_HOST1_RESET_N 140
+#define SKY1_RCSU_USB3_TYPEC_HOST2_RESET_N 141
+#define SKY1_VPU_RCSU_RESET_N 142
+
+#endif
--
2.49.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v3 2/3] reset: cix: add support for cix sky1 resets
2025-11-24 6:32 [PATCH v3 0/3] Add support for Cix Sky1 resets Gary Yang
2025-11-24 6:32 ` [PATCH v3 1/3] dt-bindings: reset: add sky1 reset controller Gary Yang
@ 2025-11-24 6:32 ` Gary Yang
2025-11-24 6:32 ` [PATCH v3 3/3] arm64: dts: " Gary Yang
2 siblings, 0 replies; 9+ messages in thread
From: Gary Yang @ 2025-11-24 6:32 UTC (permalink / raw)
To: p.zabel, robh, krzk+dt, conor+dt
Cc: devicetree, linux-kernel, linux-arm-kernel, cix-kernel-upstream,
Gary Yang
There are two reset controllers on Cix Sky1 Soc.
One is located in S0 domain, and the other is located
in S5 domain.
Signed-off-by: Gary Yang <gary.yang@cixtech.com>
---
drivers/reset/Kconfig | 7 +
drivers/reset/Makefile | 1 +
drivers/reset/reset-sky1.c | 426 +++++++++++++++++++++++++++++++++++++
3 files changed, 434 insertions(+)
create mode 100644 drivers/reset/reset-sky1.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 78b7078478d4..45768cd3b135 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -278,6 +278,13 @@ config RESET_SIMPLE
- SiFive FU740 SoCs
- Sophgo SoCs
+config RESET_SKY1
+ bool "Cix Sky1 reset controller"
+ depends on HAS_IOMEM
+ depends on ARCH_CIX || COMPILE_TEST
+ help
+ This enables the reset controller for Cix Sky1.
+
config RESET_SOCFPGA
bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA)
default ARM && ARCH_INTEL_SOCFPGA
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index f7934f9fb90b..a878ac4a6e4b 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o
obj-$(CONFIG_RESET_RZV2H_USB2PHY) += reset-rzv2h-usb2phy.o
obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
+obj-$(CONFIG_RESET_SKY1) += reset-sky1.o
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_RESET_SPACEMIT) += reset-spacemit.o
obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o
diff --git a/drivers/reset/reset-sky1.c b/drivers/reset/reset-sky1.c
new file mode 100644
index 000000000000..06f35e561799
--- /dev/null
+++ b/drivers/reset/reset-sky1.c
@@ -0,0 +1,426 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ *
+ * CIX System Reset Controller (SRC) driver
+ *
+ * Author: Jerry Zhu <jerry.zhu@cixtech.com>
+ */
+
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/reset/cix,sky1-rst.h>
+#include <dt-bindings/reset/cix,sky1-rst-fch.h>
+
+#define SKY1_RESET_REG_MAX_NUM 3
+#define SKY1_RESET_SLEEP_MIN_US 50
+#define SKY1_RESET_SLEEP_MAX_US 100
+
+struct sky1_src_signal {
+ unsigned int offset;
+ unsigned int bit;
+};
+
+struct sky1_src_variant {
+ const struct sky1_src_signal *signals;
+ unsigned int signals_num;
+ unsigned int domain;
+};
+
+struct sky1_src {
+ struct reset_controller_dev rcdev;
+ const struct sky1_src_signal *signals;
+ void __iomem *base[SKY1_RESET_REG_MAX_NUM];
+ struct regmap *regmap[SKY1_RESET_REG_MAX_NUM];
+ unsigned int domain;
+};
+
+enum {
+ CSU_PM_RESET = 0x0,
+ SENSORFUSION_RESET = 0x4,
+ SENSORFUSION_NOC_RESET = 0x8,
+ RESET_GROUP0_S0_DOMAIN_0 = 0x0,
+ RESET_GROUP0_S0_DOMAIN_1 = 0x4,
+ RESET_GROUP1_USB_PHYS = 0x8,
+ RESET_GROUP1_USB_CONTROLLERS = 0xc,
+ RESET_GROUP0_RCSU = 0x0,
+ RESET_GROUP1_RCSU = 0x4,
+};
+
+static const struct sky1_src_signal sky1_src_signals[] = {
+ /* reset group1 for s0 domain modules */
+ [SKY1_CSU_PM_RESET_N] = { CSU_PM_RESET, BIT(0) },
+ [SKY1_SENSORFUSION_RESET_N] = { SENSORFUSION_RESET, BIT(0) },
+ [SKY1_SENSORFUSION_NOC_RESET_N] = { SENSORFUSION_NOC_RESET, BIT(0) },
+ [SKY1_DDRC_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(0) },
+ [SKY1_GIC_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(1) },
+ [SKY1_CI700_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(2) },
+ [SKY1_SYS_NI700_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(3) },
+ [SKY1_MM_NI700_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(4) },
+ [SKY1_PCIE_NI700_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(5) },
+ [SKY1_GPU_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(6) },
+ [SKY1_NPUTOP_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(7) },
+ [SKY1_NPUCORE0_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(8) },
+ [SKY1_NPUCORE1_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(9) },
+ [SKY1_NPUCORE2_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(10) },
+ [SKY1_VPU_RESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(11) },
+ [SKY1_ISP_SRESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(12) },
+ [SKY1_ISP_ARESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(13) },
+ [SKY1_ISP_HRESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(14) },
+ [SKY1_ISP_GDCRESET_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(15) },
+ [SKY1_DPU_RESET0_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(16) },
+ [SKY1_DPU_RESET1_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(17) },
+ [SKY1_DPU_RESET2_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(18) },
+ [SKY1_DPU_RESET3_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(19) },
+ [SKY1_DPU_RESET4_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(20) },
+ [SKY1_DP_RESET0_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(21) },
+ [SKY1_DP_RESET1_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(22) },
+ [SKY1_DP_RESET2_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(23) },
+ [SKY1_DP_RESET3_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(24) },
+ [SKY1_DP_RESET4_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(25) },
+ [SKY1_DP_PHY_RST_N] = { RESET_GROUP0_S0_DOMAIN_0, BIT(26) },
+
+ /* reset group1 for s0 domain modules */
+ [SKY1_AUDIO_HIFI5_RESET_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(0) },
+ [SKY1_AUDIO_HIFI5_NOC_RESET_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(1) },
+ [SKY1_CSIDPHY_PRST0_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(2) },
+ [SKY1_CSIDPHY_CMNRST0_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(3) },
+ [SKY1_CSI0_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(4) },
+ [SKY1_CSIDPHY_PRST1_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(5) },
+ [SKY1_CSIDPHY_CMNRST1_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(6) },
+ [SKY1_CSI1_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(7) },
+ [SKY1_CSI2_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(8) },
+ [SKY1_CSI3_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(9) },
+ [SKY1_CSIBRDGE0_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(10) },
+ [SKY1_CSIBRDGE1_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(11) },
+ [SKY1_CSIBRDGE2_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(12) },
+ [SKY1_CSIBRDGE3_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(13) },
+ [SKY1_GMAC0_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(14) },
+ [SKY1_GMAC1_RST_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(15) },
+ [SKY1_PCIE0_RESET_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(16) },
+ [SKY1_PCIE1_RESET_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(17) },
+ [SKY1_PCIE2_RESET_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(18) },
+ [SKY1_PCIE3_RESET_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(19) },
+ [SKY1_PCIE4_RESET_N] = { RESET_GROUP0_S0_DOMAIN_1, BIT(20) },
+
+ /* reset group1 for usb phys */
+ [SKY1_USB_DP_PHY0_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(0) },
+ [SKY1_USB_DP_PHY1_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(1) },
+ [SKY1_USB_DP_PHY2_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(2) },
+ [SKY1_USB_DP_PHY3_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(3) },
+ [SKY1_USB_DP_PHY0_RST_N] = { RESET_GROUP1_USB_PHYS, BIT(4) },
+ [SKY1_USB_DP_PHY1_RST_N] = { RESET_GROUP1_USB_PHYS, BIT(5) },
+ [SKY1_USB_DP_PHY2_RST_N] = { RESET_GROUP1_USB_PHYS, BIT(6) },
+ [SKY1_USB_DP_PHY3_RST_N] = { RESET_GROUP1_USB_PHYS, BIT(7) },
+ [SKY1_USBPHY_SS_PST_N] = { RESET_GROUP1_USB_PHYS, BIT(8) },
+ [SKY1_USBPHY_SS_RST_N] = { RESET_GROUP1_USB_PHYS, BIT(9) },
+ [SKY1_USBPHY_HS0_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(10) },
+ [SKY1_USBPHY_HS1_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(11) },
+ [SKY1_USBPHY_HS2_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(12) },
+ [SKY1_USBPHY_HS3_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(13) },
+ [SKY1_USBPHY_HS4_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(14) },
+ [SKY1_USBPHY_HS5_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(15) },
+ [SKY1_USBPHY_HS6_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(16) },
+ [SKY1_USBPHY_HS7_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(17) },
+ [SKY1_USBPHY_HS8_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(18) },
+ [SKY1_USBPHY_HS9_PRST_N] = { RESET_GROUP1_USB_PHYS, BIT(19) },
+
+ /* reset group1 for usb controllers */
+ [SKY1_USBC_SS0_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(0) },
+ [SKY1_USBC_SS1_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(1) },
+ [SKY1_USBC_SS2_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(2) },
+ [SKY1_USBC_SS3_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(3) },
+ [SKY1_USBC_SS4_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(4) },
+ [SKY1_USBC_SS5_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(5) },
+ [SKY1_USBC_SS0_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(6) },
+ [SKY1_USBC_SS1_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(7) },
+ [SKY1_USBC_SS2_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(8) },
+ [SKY1_USBC_SS3_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(9) },
+ [SKY1_USBC_SS4_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(10) },
+ [SKY1_USBC_SS5_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(11) },
+ [SKY1_USBC_HS0_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(12) },
+ [SKY1_USBC_HS1_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(13) },
+ [SKY1_USBC_HS2_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(14) },
+ [SKY1_USBC_HS3_PRST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(15) },
+ [SKY1_USBC_HS0_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(16) },
+ [SKY1_USBC_HS1_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(17) },
+ [SKY1_USBC_HS2_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(18) },
+ [SKY1_USBC_HS3_RST_N] = { RESET_GROUP1_USB_CONTROLLERS, BIT(19) },
+
+ /* reset group0 for rcsu */
+ [SKY1_AUDIO_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(0) },
+ [SKY1_CI700_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(1) },
+ [SKY1_CSI_RCSU0_RESET_N] = { RESET_GROUP0_RCSU, BIT(2) },
+ [SKY1_CSI_RCSU1_RESET_N] = { RESET_GROUP0_RCSU, BIT(3) },
+ [SKY1_CSU_PM_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(4) },
+ [SKY1_DDR_BROADCAST_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(5) },
+ [SKY1_DDR_CTRL_RCSU_0_RESET_N] = { RESET_GROUP0_RCSU, BIT(6) },
+ [SKY1_DDR_CTRL_RCSU_1_RESET_N] = { RESET_GROUP0_RCSU, BIT(7) },
+ [SKY1_DDR_CTRL_RCSU_2_RESET_N] = { RESET_GROUP0_RCSU, BIT(8) },
+ [SKY1_DDR_CTRL_RCSU_3_RESET_N] = { RESET_GROUP0_RCSU, BIT(9) },
+ [SKY1_DDR_TZC400_RCSU_0_RESET_N] = { RESET_GROUP0_RCSU, BIT(10) },
+ [SKY1_DDR_TZC400_RCSU_1_RESET_N] = { RESET_GROUP0_RCSU, BIT(11) },
+ [SKY1_DDR_TZC400_RCSU_2_RESET_N] = { RESET_GROUP0_RCSU, BIT(12) },
+ [SKY1_DDR_TZC400_RCSU_3_RESET_N] = { RESET_GROUP0_RCSU, BIT(13) },
+ [SKY1_DP0_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(14) },
+ [SKY1_DP1_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(15) },
+ [SKY1_DP2_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(16) },
+ [SKY1_DP3_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(17) },
+ [SKY1_DP4_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(18) },
+ [SKY1_DPU0_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(19) },
+ [SKY1_DPU1_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(20) },
+ [SKY1_DPU2_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(21) },
+ [SKY1_DPU3_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(22) },
+ [SKY1_DPU4_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(23) },
+ [SKY1_DSU_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(24) },
+ [SKY1_FCH_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(25) },
+ [SKY1_GICD_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(26) },
+ [SKY1_GMAC_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(27) },
+ [SKY1_GPU_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(28) },
+ [SKY1_ISP_RCSU0_RESET_N] = { RESET_GROUP0_RCSU, BIT(29) },
+ [SKY1_ISP_RCSU1_RESET_N] = { RESET_GROUP0_RCSU, BIT(30) },
+ [SKY1_NI700_MMHUB_RCSU_RESET_N] = { RESET_GROUP0_RCSU, BIT(31) },
+
+ /* reset group1 for rcsu */
+ [SKY1_NPU_RCSU_RESET_N] = { RESET_GROUP1_RCSU, BIT(0) },
+ [SKY1_NI700_PCIE_RCSU_RESET_N] = { RESET_GROUP1_RCSU, BIT(1) },
+ [SKY1_PCIE_X421_RCSU_RESET_N] = { RESET_GROUP1_RCSU, BIT(2) },
+ [SKY1_PCIE_X8_RCSU_RESET_N] = { RESET_GROUP1_RCSU, BIT(3) },
+ [SKY1_SF_RCSU_RESET_N] = { RESET_GROUP1_RCSU, BIT(4) },
+ [SKY1_RCSU_SMMU_MMHUB_RESET_N] = { RESET_GROUP1_RCSU, BIT(5) },
+ [SKY1_RCSU_SMMU_PCIEHUB_RESET_N] = { RESET_GROUP1_RCSU, BIT(6) },
+ [SKY1_RCSU_SYSHUB_RESET_N] = { RESET_GROUP1_RCSU, BIT(7) },
+ [SKY1_NI700_SMN_RCSU_RESET_N] = { RESET_GROUP1_RCSU, BIT(8) },
+ [SKY1_NI700_SYSHUB_RCSU_RESET_N] = { RESET_GROUP1_RCSU, BIT(9) },
+ [SKY1_RCSU_USB2_HOST0_RESET_N] = { RESET_GROUP1_RCSU, BIT(10) },
+ [SKY1_RCSU_USB2_HOST1_RESET_N] = { RESET_GROUP1_RCSU, BIT(11) },
+ [SKY1_RCSU_USB2_HOST2_RESET_N] = { RESET_GROUP1_RCSU, BIT(12) },
+ [SKY1_RCSU_USB2_HOST3_RESET_N] = { RESET_GROUP1_RCSU, BIT(13) },
+ [SKY1_RCSU_USB3_TYPEA_DRD_RESET_N] = { RESET_GROUP1_RCSU, BIT(14) },
+ [SKY1_RCSU_USB3_TYPEC_DRD_RESET_N] = { RESET_GROUP1_RCSU, BIT(15) },
+ [SKY1_RCSU_USB3_TYPEC_HOST0_RESET_N] = { RESET_GROUP1_RCSU, BIT(16) },
+ [SKY1_RCSU_USB3_TYPEC_HOST1_RESET_N] = { RESET_GROUP1_RCSU, BIT(17) },
+ [SKY1_RCSU_USB3_TYPEC_HOST2_RESET_N] = { RESET_GROUP1_RCSU, BIT(18) },
+ [SKY1_VPU_RCSU_RESET_N] = { RESET_GROUP1_RCSU, BIT(19) },
+};
+
+enum {
+ FCH_SW_RST_FUNC = 0x0,
+ FCH_SW_RST_BUS = 0x4,
+ FCH_SW_XSPI = 0x8,
+};
+
+static const struct sky1_src_signal sky1_src_fch_signals[] = {
+ /* resets for fch_sw_rst_func */
+ [SW_I3C0_RST_FUNC_G_N] = { FCH_SW_RST_FUNC, BIT(0) },
+ [SW_I3C0_RST_FUNC_I_N] = { FCH_SW_RST_FUNC, BIT(1) },
+ [SW_I3C1_RST_FUNC_G_N] = { FCH_SW_RST_FUNC, BIT(2) },
+ [SW_I3C1_RST_FUNC_I_N] = { FCH_SW_RST_FUNC, BIT(3) },
+ [SW_UART0_RST_FUNC_N] = { FCH_SW_RST_FUNC, BIT(4) },
+ [SW_UART1_RST_FUNC_N] = { FCH_SW_RST_FUNC, BIT(5) },
+ [SW_UART2_RST_FUNC_N] = { FCH_SW_RST_FUNC, BIT(6) },
+ [SW_UART3_RST_FUNC_N] = { FCH_SW_RST_FUNC, BIT(7) },
+ [SW_TIMER_RST_FUNC_N] = { FCH_SW_RST_FUNC, BIT(20) },
+
+ /* resets for fch_sw_rst_bus */
+ [SW_I3C0_RST_APB_N] = { FCH_SW_RST_BUS, BIT(0) },
+ [SW_I3C1_RST_APB_N] = { FCH_SW_RST_BUS, BIT(1) },
+ [SW_DMA_RST_AXI_N] = { FCH_SW_RST_BUS, BIT(2) },
+ [SW_UART0_RST_APB_N] = { FCH_SW_RST_BUS, BIT(4) },
+ [SW_UART1_RST_APB_N] = { FCH_SW_RST_BUS, BIT(5) },
+ [SW_UART2_RST_APB_N] = { FCH_SW_RST_BUS, BIT(6) },
+ [SW_UART3_RST_APB_N] = { FCH_SW_RST_BUS, BIT(7) },
+ [SW_SPI0_RST_APB_N] = { FCH_SW_RST_BUS, BIT(8) },
+ [SW_SPI1_RST_APB_N] = { FCH_SW_RST_BUS, BIT(9) },
+ [SW_I2C0_RST_APB_N] = { FCH_SW_RST_BUS, BIT(12) },
+ [SW_I2C1_RST_APB_N] = { FCH_SW_RST_BUS, BIT(13) },
+ [SW_I2C2_RST_APB_N] = { FCH_SW_RST_BUS, BIT(14) },
+ [SW_I2C3_RST_APB_N] = { FCH_SW_RST_BUS, BIT(15) },
+ [SW_I2C4_RST_APB_N] = { FCH_SW_RST_BUS, BIT(16) },
+ [SW_I2C5_RST_APB_N] = { FCH_SW_RST_BUS, BIT(17) },
+ [SW_I2C6_RST_APB_N] = { FCH_SW_RST_BUS, BIT(18) },
+ [SW_I2C7_RST_APB_N] = { FCH_SW_RST_BUS, BIT(19) },
+ [SW_GPIO_RST_APB_N] = { FCH_SW_RST_BUS, BIT(21) },
+
+ /* resets for fch_sw_xspi */
+ [SW_XSPI_REG_RST_N] = { FCH_SW_XSPI, BIT(0) },
+ [SW_XSPI_SYS_RST_N] = { FCH_SW_XSPI, BIT(1) },
+};
+
+static struct sky1_src *to_sky1_src(struct reset_controller_dev *rcdev)
+{
+ return container_of(rcdev, struct sky1_src, rcdev);
+}
+
+static struct regmap *sky1_get_regmap_by_id(struct sky1_src *sky1src,
+ unsigned long id)
+{
+ struct regmap *base = NULL;
+
+ if (!sky1src->domain)
+ return sky1src->regmap[0];
+
+ switch (id) {
+ case SKY1_CSU_PM_RESET_N...SKY1_SENSORFUSION_NOC_RESET_N:
+ base = sky1src->regmap[0];
+ break;
+ case SKY1_DDRC_RESET_N...SKY1_USBC_HS3_RST_N:
+ base = sky1src->regmap[1];
+ break;
+ default:
+ base = sky1src->regmap[2];
+ break;
+ }
+ return base;
+}
+
+static int sky1_reset_set(struct reset_controller_dev *rcdev,
+ unsigned long id, bool assert)
+{
+ struct sky1_src *sky1src = to_sky1_src(rcdev);
+ const struct sky1_src_signal *signal = &sky1src->signals[id];
+ unsigned int value = assert ? 0 : sky1src->signals[id].bit;
+ struct regmap *base = sky1_get_regmap_by_id(sky1src, id);
+
+ return regmap_update_bits(base,
+ signal->offset, signal->bit, value);
+}
+
+static int sky1_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ sky1_reset_set(rcdev, id, true);
+ usleep_range(SKY1_RESET_SLEEP_MIN_US,
+ SKY1_RESET_SLEEP_MAX_US);
+ return 0;
+}
+
+static int sky1_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ sky1_reset_set(rcdev, id, false);
+ usleep_range(SKY1_RESET_SLEEP_MIN_US,
+ SKY1_RESET_SLEEP_MAX_US);
+ return 0;
+}
+
+static int sky1_reset(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ sky1_reset_assert(rcdev, id);
+ sky1_reset_deassert(rcdev, id);
+ return 0;
+}
+
+static int sky1_reset_status(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ unsigned int value = 0;
+ struct sky1_src *sky1src = to_sky1_src(rcdev);
+ const struct sky1_src_signal *signal = &sky1src->signals[id];
+ struct regmap *base = sky1_get_regmap_by_id(sky1src, id);
+
+ regmap_read(base, signal->offset, &value);
+ return !(value & signal->bit);
+}
+
+static const struct reset_control_ops sky1_src_ops = {
+ .reset = sky1_reset,
+ .assert = sky1_reset_assert,
+ .deassert = sky1_reset_deassert,
+ .status = sky1_reset_status
+};
+
+static const struct sky1_src_variant variant_sky1 = {
+ .signals = sky1_src_signals,
+ .signals_num = ARRAY_SIZE(sky1_src_signals),
+ .domain = 5,
+};
+
+static const struct sky1_src_variant variant_sky1_fch = {
+ .signals = sky1_src_fch_signals,
+ .signals_num = ARRAY_SIZE(sky1_src_fch_signals),
+ .domain = 0,
+};
+
+static const struct regmap_config sky1_src_config[] = {
+ {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .name = "src1",
+ },
+ {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .name = "src2",
+ },
+ {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .name = "src3",
+ },
+};
+
+static int sky1_reset_probe(struct platform_device *pdev)
+{
+ struct sky1_src *sky1src;
+ struct device *dev = &pdev->dev;
+ const struct sky1_src_variant *variant = device_get_match_data(dev);
+ int i;
+
+ sky1src = devm_kzalloc(dev, sizeof(*sky1src), GFP_KERNEL);
+ if (!sky1src)
+ return -ENOMEM;
+
+ for (i = 0; i < SKY1_RESET_REG_MAX_NUM; i++) {
+ sky1src->base[i] = devm_platform_ioremap_resource(pdev, i);
+ if (IS_ERR(sky1src->base[i]))
+ return PTR_ERR(sky1src->base[i]);
+ sky1src->regmap[i] = devm_regmap_init_mmio(dev, sky1src->base[i],
+ &sky1_src_config[i]);
+ if (IS_ERR(sky1src->regmap[i])) {
+ return dev_err_probe(dev, PTR_ERR(sky1src->regmap[i]),
+ "Unable to get sky1-src regmap");
+ }
+ if (!variant->domain)
+ break;
+ }
+
+ sky1src->signals = variant->signals;
+ sky1src->rcdev.owner = THIS_MODULE;
+ sky1src->rcdev.nr_resets = variant->signals_num;
+ sky1src->rcdev.ops = &sky1_src_ops;
+ sky1src->rcdev.of_node = dev->of_node;
+ sky1src->rcdev.dev = dev;
+ sky1src->domain = variant->domain;
+
+ return devm_reset_controller_register(dev, &sky1src->rcdev);
+}
+
+static const struct of_device_id sky1_reset_dt_ids[] = {
+ { .compatible = "cix,sky1-rst", .data = &variant_sky1 },
+ { .compatible = "cix,sky1-rst-fch", .data = &variant_sky1_fch },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, sky1_reset_dt_ids);
+
+static struct platform_driver sky1_reset_driver = {
+ .probe = sky1_reset_probe,
+ .driver = {
+ .name = KBUILD_MODNAME,
+ .of_match_table = sky1_reset_dt_ids,
+ },
+};
+module_platform_driver(sky1_reset_driver)
+
+MODULE_AUTHOR("Jerry Zhu <jerry.zhu@cixtech.com>");
+MODULE_DESCRIPTION("Cix Sky1 reset driver");
+MODULE_LICENSE("GPL");
--
2.49.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v3 3/3] arm64: dts: cix: add support for cix sky1 resets
2025-11-24 6:32 [PATCH v3 0/3] Add support for Cix Sky1 resets Gary Yang
2025-11-24 6:32 ` [PATCH v3 1/3] dt-bindings: reset: add sky1 reset controller Gary Yang
2025-11-24 6:32 ` [PATCH v3 2/3] reset: cix: add support for cix sky1 resets Gary Yang
@ 2025-11-24 6:32 ` Gary Yang
2 siblings, 0 replies; 9+ messages in thread
From: Gary Yang @ 2025-11-24 6:32 UTC (permalink / raw)
To: p.zabel, robh, krzk+dt, conor+dt
Cc: devicetree, linux-kernel, linux-arm-kernel, cix-kernel-upstream,
Gary Yang
There are two reset conctrollers on Cix Sky1 Soc.
One is located in S0 domain, and the other is located
in S5 domain.
Signed-off-by: Gary Yang <gary.yang@cixtech.com>
---
arch/arm64/boot/dts/cix/sky1.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi
index d21387224e79..72ebffe05ef7 100644
--- a/arch/arm64/boot/dts/cix/sky1.dtsi
+++ b/arch/arm64/boot/dts/cix/sky1.dtsi
@@ -348,6 +348,12 @@ i3c1: i3c@4100000 {
status = "disabled";
};
+ src_fch: reset-controller@4160008 {
+ compatible = "cix,sky1-rst-fch";
+ reg = <0x0 0x04160008 0x0 0xc>;
+ #reset-cells = <1>;
+ };
+
iomuxc: pinctrl@4170000 {
compatible = "cix,sky1-iomuxc";
reg = <0x0 0x04170000 0x0 0x1000>;
@@ -568,6 +574,14 @@ ppi_partition1: interrupt-partition-1 {
};
};
+ src: reset-controller@16000304 {
+ compatible = "cix,sky1-rst";
+ reg = <0x0 0x16000304 0x0 0xc>,
+ <0x0 0x16000400 0x0 0x10>,
+ <0x0 0x16000800 0x0 0x8>;
+ #reset-cells = <1>;
+ };
+
iomuxc_s5: pinctrl@16007000 {
compatible = "cix,sky1-iomuxc-s5";
reg = <0x0 0x16007000 0x0 0x1000>;
--
2.49.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v3 1/3] dt-bindings: reset: add sky1 reset controller
2025-11-24 6:32 ` [PATCH v3 1/3] dt-bindings: reset: add sky1 reset controller Gary Yang
@ 2025-11-24 19:54 ` Conor Dooley
2025-11-25 14:12 ` 回复: " Gary Yang
0 siblings, 1 reply; 9+ messages in thread
From: Conor Dooley @ 2025-11-24 19:54 UTC (permalink / raw)
To: Gary Yang
Cc: p.zabel, robh, krzk+dt, conor+dt, devicetree, linux-kernel,
linux-arm-kernel, cix-kernel-upstream
[-- Attachment #1: Type: text/plain, Size: 2896 bytes --]
On Mon, Nov 24, 2025 at 02:32:33PM +0800, Gary Yang wrote:
> There are two reset controllers on Cix sky1 Soc.
> One is located in S0 domain, and the other is located
> in S5 domain.
>
> Signed-off-by: Gary Yang <gary.yang@cixtech.com>
> ---
> .../bindings/reset/cix,sky1-rst.yaml | 50 ++++++
> include/dt-bindings/reset/cix,sky1-rst-fch.h | 42 +++++
> include/dt-bindings/reset/cix,sky1-rst.h | 164 ++++++++++++++++++
> 3 files changed, 256 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/cix,sky1-rst.yaml
> create mode 100644 include/dt-bindings/reset/cix,sky1-rst-fch.h
> create mode 100644 include/dt-bindings/reset/cix,sky1-rst.h
>
> diff --git a/Documentation/devicetree/bindings/reset/cix,sky1-rst.yaml b/Documentation/devicetree/bindings/reset/cix,sky1-rst.yaml
> new file mode 100644
> index 000000000000..a28f938a283d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/cix,sky1-rst.yaml
> @@ -0,0 +1,50 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/reset/cix,sky1-rst.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: CIX Sky1 Reset Controller
> +
> +maintainers:
> + - Gary Yang <gary.yang@cixtech.com>
> +
> +description: |
> + CIX Sky1 reset controller can be used to reset various set of peripherals.
> + There are two reset controllers, one is located in S0 domain, the other
> + is located in S5 domain.
> +
> + See also:
> + - include/dt-bindings/reset/cix,sky1-rst.h
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - cix,sky1-rst
> + - cix,sky1-rst-fch
You've not addressed my v2 commentary:
https://lore.kernel.org/all/20251114-problem-overbook-383f8e45cd0b@spud/
I asked what else the device does, but you didn't answer me. Dropping the
syscon doesn't make sense if the device genuinely has other functions.
> +
> + reg:
> + minItems: 1
> + maxItems: 3
> +
> + '#reset-cells':
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> + - '#reset-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/reset/cix,sky1-rst.h>
> + reset-controller@16000304 {
> + compatible = "cix,sky1-rst";
> + reg = <0x16000304 0xc>,
> + <0x16000400 0x10>,
> + <0x16000800 0x8>;
This is also highly suspect, and I believe what you had before was
probably much more realistic.
Do things properly and fully *now*, rather than pay the price of
unravelling it all later. I just did this for one of my own platforms,
and putting in the effort to completely describe stuff up front is
actually worth it rather than having to refactor years down the line.
Cheers,
Conor.
pw-bot: changes-requested
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* 回复: [PATCH v3 1/3] dt-bindings: reset: add sky1 reset controller
2025-11-24 19:54 ` Conor Dooley
@ 2025-11-25 14:12 ` Gary Yang
2025-11-26 19:15 ` Conor Dooley
0 siblings, 1 reply; 9+ messages in thread
From: Gary Yang @ 2025-11-25 14:12 UTC (permalink / raw)
To: Conor Dooley
Cc: p.zabel@pengutronix.de, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, cix-kernel-upstream
Hi Conor:
Thanks for your comments
> -----邮件原件-----
> 发件人: Conor Dooley <conor@kernel.org>
> 发送时间: 2025年11月25日 3:54
> 收件人: Gary Yang <gary.yang@cixtech.com>
> 抄送: p.zabel@pengutronix.de; robh@kernel.org; krzk+dt@kernel.org;
> conor+dt@kernel.org; devicetree@vger.kernel.org;
> linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> cix-kernel-upstream <cix-kernel-upstream@cixtech.com>
> 主题: Re: [PATCH v3 1/3] dt-bindings: reset: add sky1 reset controller
>
> On Mon, Nov 24, 2025 at 02:32:33PM +0800, Gary Yang wrote:
> > There are two reset controllers on Cix sky1 Soc.
> > One is located in S0 domain, and the other is located in S5 domain.
> >
> > Signed-off-by: Gary Yang <gary.yang@cixtech.com>
> > ---
> > .../bindings/reset/cix,sky1-rst.yaml | 50 ++++++
> > include/dt-bindings/reset/cix,sky1-rst-fch.h | 42 +++++
> > include/dt-bindings/reset/cix,sky1-rst.h | 164 ++++++++++++++++++
> > 3 files changed, 256 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/reset/cix,sky1-rst.yaml
> > create mode 100644 include/dt-bindings/reset/cix,sky1-rst-fch.h
> > create mode 100644 include/dt-bindings/reset/cix,sky1-rst.h
> >
> > diff --git a/Documentation/devicetree/bindings/reset/cix,sky1-rst.yaml
> > b/Documentation/devicetree/bindings/reset/cix,sky1-rst.yaml
> > new file mode 100644
> > index 000000000000..a28f938a283d
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/reset/cix,sky1-rst.yaml
> > @@ -0,0 +1,50 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/reset/cix,sky1-rst.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: CIX Sky1 Reset Controller
> > +
> > +maintainers:
> > + - Gary Yang <gary.yang@cixtech.com>
> > +
> > +description: |
> > + CIX Sky1 reset controller can be used to reset various set of peripherals.
> > + There are two reset controllers, one is located in S0 domain, the
> > +other
> > + is located in S5 domain.
> > +
> > + See also:
> > + - include/dt-bindings/reset/cix,sky1-rst.h
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - cix,sky1-rst
> > + - cix,sky1-rst-fch
>
> You've not addressed my v2 commentary:
> https://lore.kernel.org/all/20251114-problem-overbook-383f8e45cd0b@spud
> /
> I asked what else the device does, but you didn't answer me. Dropping the
> syscon doesn't make sense if the device genuinely has other functions.
>
First I'm sorry for not responding your questions earlier. We agree the fact the register space of reset should not depends on other modules.
We found that while the reset register spaces on the sky1 platform are non-contiguous, a specific register space among them is exclusively used by reset.
So we can remove syscon property and split serval register spaces. All right?
> > +
> > + reg:
> > + minItems: 1
> > + maxItems: 3
> > +
> > + '#reset-cells':
> > + const: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - '#reset-cells'
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/reset/cix,sky1-rst.h>
> > + reset-controller@16000304 {
> > + compatible = "cix,sky1-rst";
>
> > + reg = <0x16000304 0xc>,
> > + <0x16000400 0x10>,
> > + <0x16000800 0x8>;
>
> This is also highly suspect, and I believe what you had before was probably
> much more realistic.
> Do things properly and fully *now*, rather than pay the price of unravelling it
> all later. I just did this for one of my own platforms, and putting in the effort to
> completely describe stuff up front is actually worth it rather than having to
> refactor years down the line.
>
> Cheers,
> Conor.
>
Yes, I agree your view.
This scheme is discussed in our team. It is our decision, not only mine.
There are some modules here that haven't been pushed upstream yet.
If we take them as our internal names, maybe make you confuse. For example,
The register space based 0x16000000 belongs to PMCTRL_S5. It is a system power control module, not SCP.
It not only includes reset controller, but also some usb control, wakeup sources, clk gates, sleep states settings,
generic registers for software, and so on. But In kernel, we mainly focus on reset controller and usb control.
They are controlled by the different registers. So we decide to adopt this scheme.
If you have any questions, please let us know. If make any mistakes, please remind me kindly.
Thanks
Best wishes
Gary
> pw-bot: changes-requested
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: 回复: [PATCH v3 1/3] dt-bindings: reset: add sky1 reset controller
2025-11-25 14:12 ` 回复: " Gary Yang
@ 2025-11-26 19:15 ` Conor Dooley
2025-12-01 3:13 ` 回复: " Gary Yang
0 siblings, 1 reply; 9+ messages in thread
From: Conor Dooley @ 2025-11-26 19:15 UTC (permalink / raw)
To: Gary Yang
Cc: p.zabel@pengutronix.de, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, cix-kernel-upstream
[-- Attachment #1: Type: text/plain, Size: 6159 bytes --]
On Tue, Nov 25, 2025 at 02:12:23PM +0000, Gary Yang wrote:
> Hi Conor:
>
> Thanks for your comments
>
> > -----邮件原件-----
> > 发件人: Conor Dooley <conor@kernel.org>
> > 发送时间: 2025年11月25日 3:54
> > 收件人: Gary Yang <gary.yang@cixtech.com>
> > 抄送: p.zabel@pengutronix.de; robh@kernel.org; krzk+dt@kernel.org;
> > conor+dt@kernel.org; devicetree@vger.kernel.org;
> > linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > cix-kernel-upstream <cix-kernel-upstream@cixtech.com>
> > 主题: Re: [PATCH v3 1/3] dt-bindings: reset: add sky1 reset controller
> >
> > On Mon, Nov 24, 2025 at 02:32:33PM +0800, Gary Yang wrote:
> > > There are two reset controllers on Cix sky1 Soc.
> > > One is located in S0 domain, and the other is located in S5 domain.
> > >
> > > Signed-off-by: Gary Yang <gary.yang@cixtech.com>
> > > ---
> > > .../bindings/reset/cix,sky1-rst.yaml | 50 ++++++
> > > include/dt-bindings/reset/cix,sky1-rst-fch.h | 42 +++++
> > > include/dt-bindings/reset/cix,sky1-rst.h | 164 ++++++++++++++++++
> > > 3 files changed, 256 insertions(+)
> > > create mode 100644
> > > Documentation/devicetree/bindings/reset/cix,sky1-rst.yaml
> > > create mode 100644 include/dt-bindings/reset/cix,sky1-rst-fch.h
> > > create mode 100644 include/dt-bindings/reset/cix,sky1-rst.h
> > >
> > > diff --git a/Documentation/devicetree/bindings/reset/cix,sky1-rst.yaml
> > > b/Documentation/devicetree/bindings/reset/cix,sky1-rst.yaml
> > > new file mode 100644
> > > index 000000000000..a28f938a283d
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/reset/cix,sky1-rst.yaml
> > > @@ -0,0 +1,50 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/reset/cix,sky1-rst.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: CIX Sky1 Reset Controller
> > > +
> > > +maintainers:
> > > + - Gary Yang <gary.yang@cixtech.com>
> > > +
> > > +description: |
> > > + CIX Sky1 reset controller can be used to reset various set of peripherals.
> > > + There are two reset controllers, one is located in S0 domain, the
> > > +other
> > > + is located in S5 domain.
> > > +
> > > + See also:
> > > + - include/dt-bindings/reset/cix,sky1-rst.h
> > > +
> > > +properties:
> > > + compatible:
> > > + items:
> > > + - enum:
> > > + - cix,sky1-rst
> > > + - cix,sky1-rst-fch
> >
> > You've not addressed my v2 commentary:
> > https://lore.kernel.org/all/20251114-problem-overbook-383f8e45cd0b@spud
> > /
> > I asked what else the device does, but you didn't answer me. Dropping the
> > syscon doesn't make sense if the device genuinely has other functions.
> >
>
> First I'm sorry for not responding your questions earlier. We agree the fact the register space of reset should not depends on other modules.
> We found that while the reset register spaces on the sky1 platform are non-contiguous, a specific register space among them is exclusively used by reset.
> So we can remove syscon property and split serval register spaces. All right?
No, not all right, sorry.
It's perfectly okay for some region to do multiple things, most SoCs have
multiple regions exactly like this.
The normal thing to do is to treat these regions as a syscon like your
earlier version did. The problem with your v1 was that you called the
whole thing a reset, when it isn't just that.
There's plenty of examples using mfd for how these kinds of devices are
handled in the kernel. There's some using the simple-mfd compatible,
which is for when there are subdevices with their own nodes and other
defining mfd_cells and calling mfd_add_devices() when the subdevices do
not have enough complexity for a node (like your reset controller that
has one property and is unlikely to be reusable on another platform).
> > > + reg:
> > > + minItems: 1
> > > + maxItems: 3
> > > +
> > > + '#reset-cells':
> > > + const: 1
> > > +
> > > +required:
> > > + - compatible
> > > + - reg
> > > + - '#reset-cells'
> > > +
> > > +additionalProperties: false
> > > +
> > > +examples:
> > > + - |
> > > + #include <dt-bindings/reset/cix,sky1-rst.h>
> > > + reset-controller@16000304 {
> > > + compatible = "cix,sky1-rst";
> >
> > > + reg = <0x16000304 0xc>,
> > > + <0x16000400 0x10>,
> > > + <0x16000800 0x8>;
> >
> > This is also highly suspect, and I believe what you had before was probably
> > much more realistic.
> > Do things properly and fully *now*, rather than pay the price of unravelling it
> > all later. I just did this for one of my own platforms, and putting in the effort to
> > completely describe stuff up front is actually worth it rather than having to
> > refactor years down the line.
> Yes, I agree your view.
> This scheme is discussed in our team. It is our decision, not only mine.
> There are some modules here that haven't been pushed upstream yet.
> If we take them as our internal names, maybe make you confuse. For example,
If the naming is going to be confusing, then explain things in the
description property.
> The register space based 0x16000000 belongs to PMCTRL_S5. It is a system power control module, not SCP.
> It not only includes reset controller, but also some usb control, wakeup sources, clk gates, sleep states settings,
> generic registers for software, and so on. But In kernel, we mainly focus on reset controller and usb control.
> They are controlled by the different registers. So we decide to adopt this scheme.
This is all very normal stuff that syscons are used for on other
platforms. Describe the register region based on what it contains, not
based on what you currently thing that linux is going to use. Maybe
later you'll need the other functions either in linux, or in other
projects (like u-boot) that import our devicetrees.
> If you have any questions, please let us know. If make any mistakes, please remind me kindly.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* 回复: 回复: [PATCH v3 1/3] dt-bindings: reset: add sky1 reset controller
2025-11-26 19:15 ` Conor Dooley
@ 2025-12-01 3:13 ` Gary Yang
2025-12-02 21:45 ` Conor Dooley
0 siblings, 1 reply; 9+ messages in thread
From: Gary Yang @ 2025-12-01 3:13 UTC (permalink / raw)
To: Conor Dooley
Cc: p.zabel@pengutronix.de, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, cix-kernel-upstream
Hi Conor:
Thanks for your comments.
> -----邮件原件-----
> 发件人: Conor Dooley <conor@kernel.org>
> 发送时间: 2025年11月27日 3:15
> 收件人: Gary Yang <gary.yang@cixtech.com>
> 抄送: p.zabel@pengutronix.de; robh@kernel.org; krzk+dt@kernel.org;
> conor+dt@kernel.org; devicetree@vger.kernel.org;
> linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> cix-kernel-upstream <cix-kernel-upstream@cixtech.com>
> 主题: Re: 回复: [PATCH v3 1/3] dt-bindings: reset: add sky1 reset controller
>
> On Tue, Nov 25, 2025 at 02:12:23PM +0000, Gary Yang wrote:
> > Hi Conor:
> >
> > Thanks for your comments
> >
> > > -----邮件原件-----
> > > 发件人: Conor Dooley <conor@kernel.org>
> > > 发送时间: 2025年11月25日 3:54
> > > 收件人: Gary Yang <gary.yang@cixtech.com>
> > > 抄送: p.zabel@pengutronix.de; robh@kernel.org; krzk+dt@kernel.org;
> > > conor+dt@kernel.org; devicetree@vger.kernel.org;
> > > linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > > cix-kernel-upstream <cix-kernel-upstream@cixtech.com>
> > > 主题: Re: [PATCH v3 1/3] dt-bindings: reset: add sky1 reset controller
> > >
> > > On Mon, Nov 24, 2025 at 02:32:33PM +0800, Gary Yang wrote:
> > > > There are two reset controllers on Cix sky1 Soc.
> > > > One is located in S0 domain, and the other is located in S5 domain.
> > > >
> > > > Signed-off-by: Gary Yang <gary.yang@cixtech.com>
> > > > ---
> > > > .../bindings/reset/cix,sky1-rst.yaml | 50 ++++++
> > > > include/dt-bindings/reset/cix,sky1-rst-fch.h | 42 +++++
> > > > include/dt-bindings/reset/cix,sky1-rst.h | 164
> ++++++++++++++++++
> > > > 3 files changed, 256 insertions(+) create mode 100644
> > > > Documentation/devicetree/bindings/reset/cix,sky1-rst.yaml
> > > > create mode 100644 include/dt-bindings/reset/cix,sky1-rst-fch.h
> > > > create mode 100644 include/dt-bindings/reset/cix,sky1-rst.h
> > > >
> > > > diff --git
> > > > a/Documentation/devicetree/bindings/reset/cix,sky1-rst.yaml
> > > > b/Documentation/devicetree/bindings/reset/cix,sky1-rst.yaml
> > > > new file mode 100644
> > > > index 000000000000..a28f938a283d
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/reset/cix,sky1-rst.yaml
> > > > @@ -0,0 +1,50 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML
> > > > +1.2
> > > > +---
> > > > +$id: http://devicetree.org/schemas/reset/cix,sky1-rst.yaml#
> > > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > > +
> > > > +title: CIX Sky1 Reset Controller
> > > > +
> > > > +maintainers:
> > > > + - Gary Yang <gary.yang@cixtech.com>
> > > > +
> > > > +description: |
> > > > + CIX Sky1 reset controller can be used to reset various set of
> peripherals.
> > > > + There are two reset controllers, one is located in S0 domain,
> > > > +the other
> > > > + is located in S5 domain.
> > > > +
> > > > + See also:
> > > > + - include/dt-bindings/reset/cix,sky1-rst.h
> > > > +
> > > > +properties:
> > > > + compatible:
> > > > + items:
> > > > + - enum:
> > > > + - cix,sky1-rst
> > > > + - cix,sky1-rst-fch
> > >
> > > You've not addressed my v2 commentary:
> > > https://lore.kernel.org/all/20251114-problem-overbook-383f8e45cd0b@s
> > > pud
> > > /
> > > I asked what else the device does, but you didn't answer me.
> > > Dropping the syscon doesn't make sense if the device genuinely has other
> functions.
> > >
> >
> > First I'm sorry for not responding your questions earlier. We agree the fact
> the register space of reset should not depends on other modules.
> > We found that while the reset register spaces on the sky1 platform are
> non-contiguous, a specific register space among them is exclusively used by
> reset.
> > So we can remove syscon property and split serval register spaces. All right?
>
> No, not all right, sorry.
> It's perfectly okay for some region to do multiple things, most SoCs have
> multiple regions exactly like this.
> The normal thing to do is to treat these regions as a syscon like your earlier
> version did. The problem with your v1 was that you called the whole thing a
> reset, when it isn't just that.
> There's plenty of examples using mfd for how these kinds of devices are
> handled in the kernel. There's some using the simple-mfd compatible, which is
> for when there are subdevices with their own nodes and other defining
> mfd_cells and calling mfd_add_devices() when the subdevices do not have
> enough complexity for a node (like your reset controller that has one property
> and is unlikely to be reusable on another platform).
>
> > > > + reg:
> > > > + minItems: 1
> > > > + maxItems: 3
> > > > +
> > > > + '#reset-cells':
> > > > + const: 1
> > > > +
> > > > +required:
> > > > + - compatible
> > > > + - reg
> > > > + - '#reset-cells'
> > > > +
> > > > +additionalProperties: false
> > > > +
> > > > +examples:
> > > > + - |
> > > > + #include <dt-bindings/reset/cix,sky1-rst.h>
> > > > + reset-controller@16000304 {
> > > > + compatible = "cix,sky1-rst";
> > >
> > > > + reg = <0x16000304 0xc>,
> > > > + <0x16000400 0x10>,
> > > > + <0x16000800 0x8>;
> > >
> > > This is also highly suspect, and I believe what you had before was
> > > probably much more realistic.
> > > Do things properly and fully *now*, rather than pay the price of
> > > unravelling it all later. I just did this for one of my own
> > > platforms, and putting in the effort to completely describe stuff up
> > > front is actually worth it rather than having to refactor years down the line.
>
> > Yes, I agree your view.
> > This scheme is discussed in our team. It is our decision, not only mine.
> > There are some modules here that haven't been pushed upstream yet.
> > If we take them as our internal names, maybe make you confuse. For
> > example,
>
> If the naming is going to be confusing, then explain things in the description
> property.
>
> > The register space based 0x16000000 belongs to PMCTRL_S5. It is a system
> power control module, not SCP.
> > It not only includes reset controller, but also some usb control,
> > wakeup sources, clk gates, sleep states settings, generic registers for software,
> and so on. But In kernel, we mainly focus on reset controller and usb control.
> > They are controlled by the different registers. So we decide to adopt this
> scheme.
>
> This is all very normal stuff that syscons are used for on other platforms.
> Describe the register region based on what it contains, not based on what you
> currently thing that linux is going to use. Maybe later you'll need the other
> functions either in linux, or in other projects (like u-boot) that import our
> devicetrees.
>
Yes，First we agree syscon scheme. It is very common in kernel. We want to verify the next actions with you.
One, we add a node syscon@16000000 as pmctrl_s5 an example.
Two, the reset node and usb node both contain a phandle used to point to syscon node
Three, In corresponding driver files, we can get the regmap pointers via syscon API.
All right? By the way, How should we describe syscon in yaml file? Are there some files used to refer?
Please show us your suggestions. Thanks
Best regards
Gary
> > If you have any questions, please let us know. If make any mistakes, please
> remind me kindly.
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: 回复: 回复: [PATCH v3 1/3] dt-bindings: reset: add sky1 reset controller
2025-12-01 3:13 ` 回复: " Gary Yang
@ 2025-12-02 21:45 ` Conor Dooley
0 siblings, 0 replies; 9+ messages in thread
From: Conor Dooley @ 2025-12-02 21:45 UTC (permalink / raw)
To: Gary Yang
Cc: p.zabel@pengutronix.de, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, cix-kernel-upstream
[-- Attachment #1: Type: text/plain, Size: 8965 bytes --]
On Mon, Dec 01, 2025 at 03:13:44AM +0000, Gary Yang wrote:
> Hi Conor:
>
> Thanks for your comments.
>
> > -----邮件原件-----
> > 发件人: Conor Dooley <conor@kernel.org>
> > 发送时间: 2025年11月27日 3:15
> > 收件人: Gary Yang <gary.yang@cixtech.com>
> > 抄送: p.zabel@pengutronix.de; robh@kernel.org; krzk+dt@kernel.org;
> > conor+dt@kernel.org; devicetree@vger.kernel.org;
> > linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > cix-kernel-upstream <cix-kernel-upstream@cixtech.com>
> > 主题: Re: 回复: [PATCH v3 1/3] dt-bindings: reset: add sky1 reset controller
> >
> > On Tue, Nov 25, 2025 at 02:12:23PM +0000, Gary Yang wrote:
> > > Hi Conor:
> > >
> > > Thanks for your comments
> > >
> > > > -----邮件原件-----
> > > > 发件人: Conor Dooley <conor@kernel.org>
> > > > 发送时间: 2025年11月25日 3:54
> > > > 收件人: Gary Yang <gary.yang@cixtech.com>
> > > > 抄送: p.zabel@pengutronix.de; robh@kernel.org; krzk+dt@kernel.org;
> > > > conor+dt@kernel.org; devicetree@vger.kernel.org;
> > > > linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > > > cix-kernel-upstream <cix-kernel-upstream@cixtech.com>
> > > > 主题: Re: [PATCH v3 1/3] dt-bindings: reset: add sky1 reset controller
> > > >
> > > > On Mon, Nov 24, 2025 at 02:32:33PM +0800, Gary Yang wrote:
> > > > > There are two reset controllers on Cix sky1 Soc.
> > > > > One is located in S0 domain, and the other is located in S5 domain.
> > > > >
> > > > > Signed-off-by: Gary Yang <gary.yang@cixtech.com>
> > > > > ---
> > > > > .../bindings/reset/cix,sky1-rst.yaml | 50 ++++++
> > > > > include/dt-bindings/reset/cix,sky1-rst-fch.h | 42 +++++
> > > > > include/dt-bindings/reset/cix,sky1-rst.h | 164
> > ++++++++++++++++++
> > > > > 3 files changed, 256 insertions(+) create mode 100644
> > > > > Documentation/devicetree/bindings/reset/cix,sky1-rst.yaml
> > > > > create mode 100644 include/dt-bindings/reset/cix,sky1-rst-fch.h
> > > > > create mode 100644 include/dt-bindings/reset/cix,sky1-rst.h
> > > > >
> > > > > diff --git
> > > > > a/Documentation/devicetree/bindings/reset/cix,sky1-rst.yaml
> > > > > b/Documentation/devicetree/bindings/reset/cix,sky1-rst.yaml
> > > > > new file mode 100644
> > > > > index 000000000000..a28f938a283d
> > > > > --- /dev/null
> > > > > +++ b/Documentation/devicetree/bindings/reset/cix,sky1-rst.yaml
> > > > > @@ -0,0 +1,50 @@
> > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML
> > > > > +1.2
> > > > > +---
> > > > > +$id: http://devicetree.org/schemas/reset/cix,sky1-rst.yaml#
> > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > > > +
> > > > > +title: CIX Sky1 Reset Controller
> > > > > +
> > > > > +maintainers:
> > > > > + - Gary Yang <gary.yang@cixtech.com>
> > > > > +
> > > > > +description: |
> > > > > + CIX Sky1 reset controller can be used to reset various set of
> > peripherals.
> > > > > + There are two reset controllers, one is located in S0 domain,
> > > > > +the other
> > > > > + is located in S5 domain.
> > > > > +
> > > > > + See also:
> > > > > + - include/dt-bindings/reset/cix,sky1-rst.h
> > > > > +
> > > > > +properties:
> > > > > + compatible:
> > > > > + items:
> > > > > + - enum:
> > > > > + - cix,sky1-rst
> > > > > + - cix,sky1-rst-fch
> > > >
> > > > You've not addressed my v2 commentary:
> > > > https://lore.kernel.org/all/20251114-problem-overbook-383f8e45cd0b@s
> > > > pud
> > > > /
> > > > I asked what else the device does, but you didn't answer me.
> > > > Dropping the syscon doesn't make sense if the device genuinely has other
> > functions.
> > > >
> > >
> > > First I'm sorry for not responding your questions earlier. We agree the fact
> > the register space of reset should not depends on other modules.
> > > We found that while the reset register spaces on the sky1 platform are
> > non-contiguous, a specific register space among them is exclusively used by
> > reset.
> > > So we can remove syscon property and split serval register spaces. All right?
> >
> > No, not all right, sorry.
> > It's perfectly okay for some region to do multiple things, most SoCs have
> > multiple regions exactly like this.
> > The normal thing to do is to treat these regions as a syscon like your earlier
> > version did. The problem with your v1 was that you called the whole thing a
> > reset, when it isn't just that.
> > There's plenty of examples using mfd for how these kinds of devices are
> > handled in the kernel. There's some using the simple-mfd compatible, which is
> > for when there are subdevices with their own nodes and other defining
> > mfd_cells and calling mfd_add_devices() when the subdevices do not have
> > enough complexity for a node (like your reset controller that has one property
> > and is unlikely to be reusable on another platform).
> >
> > > > > + reg:
> > > > > + minItems: 1
> > > > > + maxItems: 3
> > > > > +
> > > > > + '#reset-cells':
> > > > > + const: 1
> > > > > +
> > > > > +required:
> > > > > + - compatible
> > > > > + - reg
> > > > > + - '#reset-cells'
> > > > > +
> > > > > +additionalProperties: false
> > > > > +
> > > > > +examples:
> > > > > + - |
> > > > > + #include <dt-bindings/reset/cix,sky1-rst.h>
> > > > > + reset-controller@16000304 {
> > > > > + compatible = "cix,sky1-rst";
> > > >
> > > > > + reg = <0x16000304 0xc>,
> > > > > + <0x16000400 0x10>,
> > > > > + <0x16000800 0x8>;
> > > >
> > > > This is also highly suspect, and I believe what you had before was
> > > > probably much more realistic.
> > > > Do things properly and fully *now*, rather than pay the price of
> > > > unravelling it all later. I just did this for one of my own
> > > > platforms, and putting in the effort to completely describe stuff up
> > > > front is actually worth it rather than having to refactor years down the line.
> >
> > > Yes, I agree your view.
> > > This scheme is discussed in our team. It is our decision, not only mine.
> > > There are some modules here that haven't been pushed upstream yet.
> > > If we take them as our internal names, maybe make you confuse. For
> > > example,
> >
> > If the naming is going to be confusing, then explain things in the description
> > property.
> >
> > > The register space based 0x16000000 belongs to PMCTRL_S5. It is a system
> > power control module, not SCP.
> > > It not only includes reset controller, but also some usb control,
> > > wakeup sources, clk gates, sleep states settings, generic registers for software,
> > and so on. But In kernel, we mainly focus on reset controller and usb control.
> > > They are controlled by the different registers. So we decide to adopt this
> > scheme.
> >
> > This is all very normal stuff that syscons are used for on other platforms.
> > Describe the register region based on what it contains, not based on what you
> > currently thing that linux is going to use. Maybe later you'll need the other
> > functions either in linux, or in other projects (like u-boot) that import our
> > devicetrees.
> >
>
> Yes，First we agree syscon scheme. It is very common in kernel. We want to verify the next actions with you.
> One, we add a node syscon@16000000 as pmctrl_s5 an example.
> Two, the reset node and usb node both contain a phandle used to point to syscon node
Not quite. The rest node would be empty, other than the phandle, and is
therefore pointless. The #reset-cells property should go in the syscon
node itself. For usb, because it sounds like the syscon is only
providing some control registers and is not the usb controller itself, a
phandle is okay. It's a case by case thing, but if the syscon node
provides an entire feature then a phandle is not suitable and instead
either a child node of the syscon (which would make it a simple-mfd too)
should be used or the properties should go directly into the syscon
node. That depends on how complex the feature is and how likely it is to
be reused between devices. reset is very unlikely to be suitable for
reuse, for example.
> Three, In corresponding driver files, we can get the regmap pointers via syscon API.
> All right? By the way, How should we describe syscon in yaml file? Are there some files used to refer?
microchip,mpfs-mss-top-sysreg.yaml is one I wrote recently. Going to the
corresponding driver you will be able to see how the reset controller
driver is probed. You should be able to find it in linux-next.
sophgo,sg2044-top-syscon.yaml is another that works in the same way.
> Please show us your suggestions. Thanks
>
> Best regards
> Gary
>
> > > If you have any questions, please let us know. If make any mistakes, please
> > remind me kindly.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2025-12-02 21:46 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-11-24 6:32 [PATCH v3 0/3] Add support for Cix Sky1 resets Gary Yang
2025-11-24 6:32 ` [PATCH v3 1/3] dt-bindings: reset: add sky1 reset controller Gary Yang
2025-11-24 19:54 ` Conor Dooley
2025-11-25 14:12 ` 回复: " Gary Yang
2025-11-26 19:15 ` Conor Dooley
2025-12-01 3:13 ` 回复: " Gary Yang
2025-12-02 21:45 ` Conor Dooley
2025-11-24 6:32 ` [PATCH v3 2/3] reset: cix: add support for cix sky1 resets Gary Yang
2025-11-24 6:32 ` [PATCH v3 3/3] arm64: dts: " Gary Yang
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox