From: Rui Wang <rui.wang@ideasonboard.com>
To: linux-media@vger.kernel.org, dafna@fastmail.com,
laurent.pinchart@ideasonboard.com, mchehab@kernel.org,
heiko@sntech.de, linux-rockchip@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Cc: libcamera-devel@lists.libcamera.org,
Rui Wang <rui.wang@ideasonboard.com>
Subject: [PATCH v1 0/1] Fix filter mode register issue
Date: Mon, 1 Dec 2025 20:50:24 -0500 [thread overview]
Message-ID: <20251202015025.601549-1-rui.wang@ideasonboard.com> (raw)
Hi,
This series contains a single patch that fixes an issue in the rkisp1
filter mode configuration logic.
The rkisp1_flt_config() function performs a direct write to the
FILT_MODE register before the read/modify/write update. This write
does not include the RKISP1_CIF_ISP_FLT_ENA bit, which clears the
enable bit in hardware. After that, the read/modify/write sequence
cannot restore the original enable state, causing the filter to be
disabled unintentionally.
The patch removes the redundant direct write. The remaining
read/modify/write sequence correctly updates the mode fields while
preserving the existing enable bit.
Please review.
Thanks,
Rui Wang
Rui Wang (1):
media: rkisp1: Fix filter mode register configuration
drivers/media/platform/rockchip/rkisp1/rkisp1-params.c | 6 ------
1 file changed, 6 deletions(-)
--
2.43.0
next reply other threads:[~2025-12-02 1:50 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-02 1:50 Rui Wang [this message]
2025-12-02 1:50 ` [PATCH v1 1/1] media: rkisp1: Fix filter mode register configuration Rui Wang
2025-12-02 6:42 ` Stefan Klug
2026-01-05 11:29 ` Kieran Bingham
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